TWI690917B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a substrate, a pixel and a touch trace. The pixel is disposed on the substrate. The pixel includes a thin film transistor, a data line, a scan line, a conductive pattern, a pixel electrode and a common electrode. The thin film transistor has a gate, a semiconductor pattern, a gate insulating layer disposed between the gate and the semiconductor pattern, a source and a drain. The data line is electrically connected to the source of the thin film transistor. The scan line is electrically connected to the gate of the thin film transistor. The conductive pattern is electrically connected to the drain of the thin film transistor. The gate insulating layer is disposed on the conductive pattern. The pixel electrode is electrically connected to the conductive pattern and disposed between the gate insulating layer and the substrate. The common electrode is disposed on the gate insulating layer. The touch trace is electrically connected to the common electrode and crosses the conductive pattern of the pixel.

Description

Pixel array substrate

The invention relates to a semiconductor substrate, and in particular to a pixel array substrate.

The application of the display is becoming more and more widespread, such as home audio-visual entertainment, public information display boards, e-sports displays and portable electronic products are all visible. For ease of use, the display has touch functions. Electronic devices with touch and display functions are called touch display devices. In general, touch display devices can be divided into out-cell (on cell), on-cell (on cell), and in-cell (In-cell). The in-cell touch display device has the advantage of being easy to be thin, and therefore, it has gradually become the mainstream of touch display devices in recent years.

The in-cell touch display device includes a pixel array substrate with pixels, data lines and scan lines, and touch traces integrated in the pixel array substrate. In order to integrate the touch traces into the touch traces in the pixel array substrate, most of them use another process to make the touch traces, resulting in a variety of processes for the pixel array substrate. In addition, the touch traces are mostly arranged above the data lines, and the coupling capacitance between the touch traces and the data lines is large, which affects the touch function.

The present invention provides a pixel array substrate with few manufacturing processes and good performance.

The pixel array substrate of the present invention includes a substrate, at least one pixel and touch traces. At least one pixel is disposed on the substrate. Each of the at least one pixel includes thin film transistors, data lines, scanning lines, conductive patterns, pixel electrodes, and common electrodes. The thin film transistor has a gate electrode, a semiconductor pattern, a gate insulating layer provided between the gate electrode and the semiconductor pattern, a source electrode, and a drain electrode. The data line is electrically connected to the source of the thin film transistor. The scanning line is electrically connected to the gate electrode of the thin film transistor. The conductive pattern is electrically connected to the drain electrode of the thin film transistor, and the gate insulating layer is disposed on the conductive pattern. The pixel electrode is electrically connected to the conductive pattern, and is disposed between the gate insulating layer and the substrate. The common electrode is arranged on the gate insulating layer. The touch trace is electrically connected to the common electrode. In particular, the touch trace crosses the pixel's conductive pattern.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100, 100A: pixel array substrate

110: base

121: Gate

122: conductive pattern

123: shared line

130: pixel electrode

140: gate insulation

140a, 140b, 140c, 140d, 170b, 170d: contact window

150: semiconductor pattern

161: Source

162: Jiji

163: Touch trace

170: dielectric layer

180: common electrode

180a: slit

181: Main Department

182: Extension

190: driver chip

d1, d2: direction

DL: data cable

PX, PX1, PX2: pixels

R: local

SP: Touch sensing pad

SL: Scan line

T: thin film transistor

I-I’, Π-Π’: section line

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

2 is an enlarged schematic view of a part R of the pixel array substrate 100 according to the first embodiment of the invention.

3 is a schematic cross-sectional view of the pixel array substrate 100 according to the first embodiment of the invention.

4 is a partial R of the pixel array substrate 100A of the second embodiment of the invention Enlarge the schematic.

5 is a schematic cross-sectional view of a pixel array substrate 100A according to a second embodiment of the invention.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “connected to” another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, the "electrically connected" or "coupled" system may be that there are other elements between the two elements.

As used herein, "about", "approximately", or "substantially" includes the stated value and the average value within an acceptable deviation range for a particular value determined by one of ordinary skill in the art, taking into account the measurements and A certain amount of measurement-related errors (ie, measurement system limitations). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about", "approximately", or "substantially" can be based on optical properties, etching properties, or other properties to select a more acceptable range of deviation or standard deviation, and not one standard deviation can be applied to all properties .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that such as those defined in commonly used dictionaries Terms should be interpreted as having a meaning consistent with their meaning in the context of the related art and the present invention, and will not be interpreted as an idealized or excessively formal meaning unless explicitly defined as such herein.

FIG. 1 is a schematic top view of a pixel array substrate according to an embodiment of the invention.

2 is an enlarged schematic view of a part R of the pixel array substrate 100 according to the first embodiment of the invention. FIG. 2 corresponds to a part R of the pixel array substrate 100 of FIG. 1.

3 is a schematic cross-sectional view of the pixel array substrate 100 according to the first embodiment of the invention. Fig. 3 corresponds to section line I-I' and section line Π-Π' of Fig. 2.

1 shows the base 110 of the pixel array substrate 100, the touch sensing pad SP, the touch traces 163, and the driving chip 190, and omits other components of the pixel array substrate 100; the pixel array substrate omitted by FIG. 1 The other components of 100 are depicted in FIGS. 2 and 3. In addition, FIG. 2 omits the plurality of contact windows 140a, 140b, 170b, 140c, 140d, and 170d of FIG.

Referring to FIGS. 1, 2 and 3, the pixel array substrate 100 includes a base 110 and a plurality of pixels PX disposed on the base 110. The substrate 110 is mainly used to carry the elements of the pixel array substrate 100. For example, in this embodiment, the material of the substrate 110 may be glass, quartz, organic polymer, or opaque/reflective materials (eg, wafers, ceramics, or other applicable materials), or Other applicable materials.

Each pixel PX includes a thin film transistor T, a data line DL, and a scan line SL. The thin film transistor T has a gate 121, a semiconductor pattern 150, a gate insulating layer 140 disposed between the gate 121 and the semiconductor pattern 150, a source 161, and a drain 162. The scan line SL is electrically connected to the gate 121 of the thin film transistor T. Data line DL electrical Connected to the source electrode 161 of the thin film transistor T. The source electrode 161 and the drain electrode 162 are respectively electrically connected to two different regions of the semiconductor pattern 150.

In this embodiment, the gate electrode 121 may be located under the semiconductor pattern 150, and the thin film transistor T may be a bottom gate transistor. However, the present invention is not limited to this, and according to other embodiments, the thin film transistor T may also be other types of transistors. For example, in another embodiment, the gate 121 may also be located above the semiconductor pattern 150, and the thin film transistor T may also be a top gate transistor.

The pixel PX further includes a conductive pattern 122. The gate insulating layer 140 is disposed on the conductive pattern 122. The conductive pattern 122 is disposed between the gate insulating layer 140 and the substrate 110. The drain electrode 162 of the thin film transistor T is electrically connected to the conductive pattern 122. Specifically, in this embodiment, the gate insulating layer 140 has a contact window 140a, and the drain electrode 162 of the thin film transistor T is electrically connected to the conductive pattern 122 through the contact window 140a.

The pixel PX further includes a pixel electrode 130 electrically connected to the conductive pattern 122. The pixel electrode 130 is electrically connected to the drain electrode 162 of the thin film transistor T through the conductive pattern 122. In particular, the pixel electrode 130 is disposed between the gate insulating layer 140 and the substrate 110.

For example, in this embodiment, the conductive pattern 122, the pixel electrode 130, and the gate insulating layer 140 can be selectively formed in sequence. Part of the pixel electrode 130 may be directly disposed on the conductive pattern 122, so that the pixel electrode 130 and the conductive pattern 122 are electrically connected. In this embodiment, part of the pixel electrodes 130 can be selectively disposed between the gate insulating layer 140 and the conductive pattern 122, but the invention is not limited thereto.

In this embodiment, the conductive pattern 122, the gate 121, and the scan line SL may be formed on the same first conductive layer. In other words, the material and gate of the conductive pattern 122 The material of 121 and the material of the scanning line SL may be the same. In addition, in this embodiment, the source electrode 161, the drain electrode 162 and the data line DL may be formed on the same second conductive layer. In other words, the material of the source electrode 161, the material of the drain electrode 162, and the material of the data line DL may be the same. Based on conductivity considerations, the first conductive layer and the second conductive layer are generally metals. However, the present invention is not limited to this. According to other embodiments, the first conductive layer and the second conductive layer may also use other conductive materials, such as: alloy, nitride of metal material, oxide of metal material, metal Nitrogen oxide of the material, or a stack of metal materials and other conductive materials.

In this embodiment, the pixel electrode 130 is, for example, a transparent conductive layer, which includes metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, Other suitable oxides, or stacked layers of at least two of the above, but the invention is not limited thereto.

In this embodiment, the pixel PX further includes a common electrode 180, which is disposed on the gate insulating layer 140. Specifically, in this embodiment, the pixel array substrate 100 further includes a dielectric layer 170 disposed on the source electrode 161, the drain electrode 162, and part of the gate insulating layer 140, and the common electrode 180 may be disposed on the dielectric layer 170 on.

In this embodiment, the common electrode 180 has a plurality of slits 180a, and the slit 180a of the common electrode 180 overlaps the pixel electrode 130. The pixel array substrate 100, a counter substrate (not shown), and a display medium (eg, liquid crystal; not shown) disposed between the pixel array substrate 100 and the counter substrate can constitute a display panel, and the common electrode 180 and The potential difference between the pixel electrodes 130 is used to drive the display medium, so that the display panel can display images.

In this embodiment, in addition to the common electrode 180 for display, the multiple common electrodes 180 of adjacent pixels PX can also be electrically connected to each other to form a touch sensing pad SP (labeled in FIG. 1 ). The touch sensing pad SP can be electrically connected to a driving chip 190 through the touch trace 163. In other words, in addition to being used to form a display panel, the pixel array substrate 100 of the present embodiment also has a built-in touch function.

The following specifically describes how the plurality of common electrodes 180 of the plurality of pixels PX in this embodiment are electrically connected to each other to form the touch sensing pad SP, and how the plurality of common electrodes 180 as the touch sensing pad SP are The touch trace 163 is electrically connected.

2 and 3, the pixel array substrate 100 further includes a common line 123. The gate insulating layer 140 is provided on the common line 123. In this embodiment, the common line 123 may be substantially parallel to the scan line SL. Both the common line 123 and the scan line SL may be formed on the aforementioned first conductive layer, but the invention is not limited thereto.

In this embodiment, the common electrode 180 includes a main portion 181 and an extension portion 182. The main portion 181 overlaps the pixel electrode 130. The extending portion 182 extends beyond the area of the pixel electrode 130 along the first direction d1. The common line 123 extends along the second direction d2. The first direction d1 intersects the second direction d2. The plurality of pixels PX of the pixel array substrate 100 include adjacent first pixels PX1 and second pixels PX2. The gate insulating layer 140 is disposed on the common line 123 and has a first contact window 140b and a third contact window 140d that respectively overlap two different places of the common line 123. The extension portion 182 of the common electrode 180 of the first pixel PX1 is electrically connected to the common line 123 through the first contact window 140b of the gate insulating layer 140 and the contact window 170b of the dielectric layer 170. Common electrode of the second pixel PX2 The extension portion 182 of 180 is electrically connected to the common line 123 through the third contact window 140d of the gate insulating layer 140 and the contact window 170d of the dielectric layer 170. That is to say, the plurality of common electrodes 180 of the adjacent plurality of pixels PX are electrically connected to each other by using part of the common line 123 disposed in the active area to form a touch sensing pad SP (marked at figure 1).

The pixel array substrate 100 further includes touch traces 163 electrically connected to the touch sensing pad SP. Specifically, in this embodiment, the touch traces 163 are disposed on the gate insulating layer 140 and electrically connected to the common line 123 through the second contact window 140c of the gate insulating layer 140, and the touch traces 163 pass through part of The common line 123 is connected to the touch sensing pad SP composed of a plurality of common electrodes 180.

In particular, in this embodiment, the touch trace 163 is directly disposed on the gate insulating layer 140 and is in contact with the gate insulating layer 140. The touch traces 163 disposed on the gate insulating layer 140 can cross the conductive patterns 122 of the pixels PX disposed under the gate insulating layer 140. In this embodiment, the material of the touch trace 163 and the data line DL can be the same; that is, the touch trace 163 and the data line DL can be formed in the same film layer, but the invention is not limited to this .

In this embodiment, the vertical projection of the first contact window 140b on the substrate 110 is between the vertical projection of the data line DL of the first pixel PX1 on the substrate 110 and the vertical projection of the second contact window 140c on the substrate 110 . The vertical projection of the second contact window 140c on the substrate 110 is between the vertical projection of the first contact window 140b on the substrate 110 and the vertical projection of the third contact window 140d on the substrate 110.

In this embodiment, the source 161 of the active element T of the first pixel PX1 The source 161 of the active element T of the second pixel PX2 is electrically connected to the same data line DL, and the gate 121 of the active element T of the first pixel PX1 and the active element T of the second pixel PX2 The gate 121 is electrically connected to two different scanning lines SL. That is to say, the pixel array substrate 100 of this embodiment has a half source driving (HSD) architecture.

In this embodiment, the extension 182 of the common electrode 180 of the first pixel PX1 spans the conductive pattern 122 of the second pixel PX2. In addition, the vertical projection of the touch trace 163 on the substrate 110 may be located between two vertical projections of the pixel electrode 130 of the first pixel PX1 and the pixel electrode 130 of the second pixel PX2 on the substrate 110.

It must be noted here that the following embodiments follow the element numbers and partial contents of the foregoing embodiments, wherein the same reference numbers are used to indicate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

FIG. 4 is an enlarged schematic view of a part R of the pixel array substrate 100A according to the second embodiment of the invention. FIG. 4 corresponds to a part R of the pixel array substrate 100A of FIG. 1.

5 is a schematic cross-sectional view of a pixel array substrate 100A according to a second embodiment of the invention. Fig. 5 corresponds to section line I-I' and section line Π-Π' of Fig. 4.

FIG. 1 shows the base 110 of the pixel array substrate 100A, the touch sensing pad SP, the touch traces 163, and the driving chip 190, while omitting other components of the pixel array substrate 100A; the pixel array substrate omitted by FIG. 1 Other components of 100A are depicted in FIGS. 4 and 5. In addition, FIG. 4 omits the plurality of contact windows 140a, 140b, 170b, 140c, 140d, and 170d of FIG.

The pixel array substrate 100A of the second embodiment is similar to the pixel array substrate 100 of the first embodiment, and the differences between the two are as follows. Referring to FIGS. 4 and 5, in this embodiment, the pixel electrode 130, the conductive pattern 122 and the gate insulating layer 140 are formed in sequence, and part of the conductive pattern 122 is disposed between the gate insulating layer 140 and the pixel electrode 130 between.

In summary, the pixel array substrate of an embodiment of the present invention includes a substrate, at least one pixel, and touch traces. Each of each pixel includes a thin film transistor, a data line, a scanning line, a conductive pattern, a pixel electrode, and a common electrode. The thin film transistor has a gate electrode, a semiconductor pattern, a gate insulating layer provided between the gate electrode and the semiconductor pattern, a source electrode, and a drain electrode. The conductive pattern is electrically connected to the drain electrode of the thin film transistor, and the gate insulating layer is disposed on the conductive pattern. The pixel electrode is electrically connected to the conductive pattern, and is disposed between the gate insulating layer and the substrate. The common electrode is arranged on the gate insulating layer. The touch trace is electrically connected to the common electrode. In particular, the touch trace crosses the pixel's conductive pattern. In this way, the touch trace does not need to overlap with the data line, the coupling capacitance between the touch trace and the data line is small, and the setting of the touch trace does not excessively affect the aperture ratio of the pixel array substrate, and can be achieved Pixel array substrate with excellent touch function and aperture ratio.

In addition, in one embodiment, the pixel electrode is disposed between the gate insulating layer and the substrate, the pixel electrode is electrically connected to the drain of the thin film transistor through the conductive pattern disposed under the gate insulating layer, and the touch trace is provided On the gate insulating layer, the touch trace and the data line can be formed on the same film layer. Therefore, the manufacturing process of the pixel array substrate is small.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the art will not deviate from the present invention. Within the spirit and scope, some changes and modifications can be made, so the scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100: pixel array substrate

121: Gate

122: conductive pattern

123: shared line

130: pixel electrode

150: semiconductor pattern

161: Source

162: Jiji

163: Touch trace

180: common electrode

180a: slit

181: Main Department

182: Extension

d1, d2: direction

DL: data cable

PX, PX1, PX2: pixels

R: local

SL: Scan line

T: thin film transistor

I-I’, Π-Π’: section line

Claims (8)

A pixel array substrate, including: a substrate; at least one pixel, disposed on the substrate, wherein each of the at least one pixel includes: a thin film transistor, having a gate, a semiconductor pattern, disposed on A gate insulating layer, a source electrode and a drain electrode between the gate electrode and the semiconductor pattern; a data line electrically connected to the source electrode of the thin film transistor; a scan line electrically connected to the thin film The gate electrode of the transistor; a conductive pattern electrically connected to the drain electrode of the thin film transistor, wherein the gate insulating layer is disposed on the conductive pattern; a pixel electrode is electrically connected to the conductive pattern, and Disposed between the gate insulating layer and the substrate; and a common electrode disposed on the gate insulating layer; and a touch trace electrically connected to the common electrode, wherein the touch trace crosses the conductive pattern . The pixel array substrate as described in item 1 of the patent scope, wherein the material of the conductive pattern is the same as the material of the gate electrode. The pixel array substrate as described in item 1 of the patent application range, wherein the material of the touch trace is the same as the material of the data line. The pixel array substrate as described in item 1 of the patent application range, wherein the touch trace is in contact with the gate insulating layer. The pixel array substrate as described in item 1 of the patent application scope, wherein part of the pixel electrode is disposed between the gate insulating layer and the conductive pattern. The pixel array substrate according to item 1 of the patent application scope, wherein part of the conductive pattern is disposed between the gate insulating layer and the pixel electrode. The pixel array substrate of claim 1, wherein the common electrode of each of the at least one pixel includes: a main portion overlapping the pixel electrode; and an extension portion along a The first direction extends beyond the area of the pixel electrode; the pixel array substrate further includes: a common line extending along a second direction, wherein the gate insulating layer is disposed on the common line and has overlaps with the common line, respectively A first contact window and a second contact window at two different locations, the at least one pixel includes a first pixel, and the extension of the common electrode of the first pixel is electrically through the first contact window Connected to the common line, the touch trace is disposed on the gate insulating layer and is electrically connected to the common line through the second contact window of the gate insulating layer. The pixel array substrate as described in item 7 of the patent application range, wherein the at least one pixel further includes a second pixel, and the gate insulating layer further has a third contact window overlapping another part of the common line , The extension of the common electrode of the second pixel is electrically connected to the common line through the third contact window, and the vertical projection of the second contact window on the substrate is located on the first contact window on the substrate Between the vertical projection on the top and the vertical projection of the third contact window on the substrate.

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