TWI587036B - In-cell touch panel - Google Patents

In-cell touch panel Download PDF

Info

Publication number
TWI587036B
TWI587036B TW104135845A TW104135845A TWI587036B TW I587036 B TWI587036 B TW I587036B TW 104135845 A TW104135845 A TW 104135845A TW 104135845 A TW104135845 A TW 104135845A TW I587036 B TWI587036 B TW I587036B
Authority
TW
Taiwan
Prior art keywords
touch panel
common voltage
conductive layer
voltage electrode
touch
Prior art date
Application number
TW104135845A
Other languages
Chinese (zh)
Other versions
TW201640188A (en
Inventor
江昶慶
林依縈
李昆倍
Original Assignee
瑞鼎科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/882,880 external-priority patent/US20160109741A1/en
Application filed by 瑞鼎科技股份有限公司 filed Critical 瑞鼎科技股份有限公司
Publication of TW201640188A publication Critical patent/TW201640188A/en
Application granted granted Critical
Publication of TWI587036B publication Critical patent/TWI587036B/en

Links

Description

內嵌式觸控面板 In-line touch panel

本發明係與觸控面板(Touch panel)有關,特別是關於一種能夠具有良好電性(RC loading)之內嵌式(In-cell)觸控面板。 The present invention relates to a touch panel, and more particularly to an in-cell touch panel capable of having good electrical properties (RC loading).

一般而言,電容式觸控面板大致可依照其疊層結構之不同而分為數種不同型式,例如:內嵌式(In-cell)的電容式觸控面板及On-cell的電容式觸控面板。 In general, a capacitive touch panel can be roughly divided into several different types according to the laminated structure, for example, an in-cell capacitive touch panel and an On-cell capacitive touch. panel.

請參照圖1及圖2,圖1及圖2係分別繪示內嵌式的電容式觸控面板及On-Cell的電容式觸控面板的疊層結構示意圖。如圖1所示,On-Cell的電容式觸控面板之疊層結構1由下至上依序是:基板10、薄膜電晶體(TFT)元件層11、液晶層12、彩色濾光層13、玻璃層14、觸控感應層15、偏光片16、黏合劑17及上覆透鏡18。如圖2所示,內嵌式的電容式觸控面板之疊層結構2由下至上依序是:基板20、薄膜電晶體(TFT)元件層21、觸控感應層22、液晶層23、彩色濾光層24、玻璃層25、偏光片26、黏合劑27及上覆透鏡28。 Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are schematic diagrams showing the laminated structure of the in-cell capacitive touch panel and the On-Cell capacitive touch panel. As shown in FIG. 1 , the stacked structure 1 of the On-Cell capacitive touch panel is sequentially from bottom to top: a substrate 10, a thin film transistor (TFT) device layer 11, a liquid crystal layer 12, a color filter layer 13, The glass layer 14, the touch sensing layer 15, the polarizer 16, the adhesive 17, and the overlying lens 18. As shown in FIG. 2, the laminated structure 2 of the in-cell capacitive touch panel is sequentially from bottom to top: a substrate 20, a thin film transistor (TFT) device layer 21, a touch sensing layer 22, a liquid crystal layer 23, The color filter layer 24, the glass layer 25, the polarizer 26, the adhesive 27, and the overlying lens 28.

比較圖1及圖2可知:內嵌式的電容式觸控面板係 將觸控感應層22設置於液晶層23的下方,亦即設置於液晶顯示模組之內;On-Cell的電容式觸控面板則是將觸控感應層15設置於玻璃層14的上方,亦即設置於液晶顯示模組之外。相較於傳統的單片式玻璃觸控面板(One Glass Solution,OGS)及On-Cell的電容式觸控面板,內嵌式的電容式觸控面板可達成最薄化的觸控面板設計,並可廣泛應用於手機、平板電腦及筆記型電腦等可攜式電子產品上。 Comparing Figure 1 with Figure 2, it can be seen that the embedded capacitive touch panel is The touch sensing layer 22 is disposed under the liquid crystal layer 23, that is, disposed in the liquid crystal display module; the On-Cell capacitive touch panel is disposed above the glass layer 14 by the touch sensing layer 15 That is, it is disposed outside the liquid crystal display module. Compared with the traditional one-piece glass touch panel (OGS) and On-Cell capacitive touch panel, the in-line capacitive touch panel can achieve the thinnest touch panel design. It can be widely used in portable electronic products such as mobile phones, tablet computers and notebook computers.

因此,本發明提出一種內嵌式觸控面板,希望能透過其創新的佈局方式降低阻值及寄生電容之影響,以提升內嵌式觸控面板之整體效能。 Therefore, the present invention provides an in-cell touch panel, and it is desired to reduce the influence of resistance and parasitic capacitance through its innovative layout to enhance the overall performance of the in-cell touch panel.

根據本發明之一較佳具體實施例為一種內嵌式觸控面板。於此實施例中,內嵌式觸控面板包含複數個像素。每個像素之疊層結構包含基板、薄膜電晶體元件層、液晶層、彩色濾光層及玻璃層。薄膜電晶體元件層設置於基板上。薄膜電晶體元件層內設置有第一導電層及共同電壓電極。第一導電層係以網格狀排列。液晶層設置於薄膜電晶體元件層上方。彩色濾光層設置於液晶層上方。玻璃層設置於彩色濾光層上方。 A preferred embodiment of the present invention is an in-cell touch panel. In this embodiment, the in-cell touch panel includes a plurality of pixels. The stacked structure of each pixel includes a substrate, a thin film transistor element layer, a liquid crystal layer, a color filter layer, and a glass layer. The thin film transistor element layer is disposed on the substrate. A first conductive layer and a common voltage electrode are disposed in the thin film transistor element layer. The first conductive layers are arranged in a grid shape. The liquid crystal layer is disposed above the thin film transistor element layer. The color filter layer is disposed above the liquid crystal layer. The glass layer is disposed above the color filter layer.

於一實施例中,內嵌式觸控面板係為一內嵌式自電容(self-capacitive)觸控面板,內嵌式自電容觸控面板之複數個觸控感測電極係由網格狀排列的第一導電層所形成。 In one embodiment, the in-cell touch panel is an in-cell self-capacitive touch panel, and the plurality of touch sensing electrodes of the in-cell self-capacitive touch panel are mesh-shaped. An array of first conductive layers is formed.

於一實施例中,第一導電層與共同電壓電極之間係透過一絕緣層彼此分隔。 In an embodiment, the first conductive layer and the common voltage electrode are separated from each other by an insulating layer.

於一實施例中,該複數個觸控感測電極之間不相連且間隔一特定距離。 In one embodiment, the plurality of touch sensing electrodes are disconnected and spaced apart by a specific distance.

於一實施例中,特定距離係為以像素(Pixel)或子像素(Sub-pixel)為單位。 In one embodiment, the specific distance is in units of pixels (Pixel) or sub-pixels (Sub-pixel).

於一實施例中,不作為觸控感測電極之部分的第一導電層係透過通孔(Via)與共同電壓電極電性連接。 In one embodiment, the first conductive layer that is not part of the touch sensing electrode is electrically connected to the common voltage electrode through the via (Via).

於一實施例中,第一導電層係形成於共同電壓電極之後。 In an embodiment, the first conductive layer is formed after the common voltage electrode.

於一實施例中,第一導電層係形成於共同電壓電極之前。 In one embodiment, the first conductive layer is formed before the common voltage electrode.

於一實施例中,彩色濾光層包含彩色濾光片(Color Filter)及黑色矩陣光阻(Black Matrix Resist),黑色矩陣光阻具有良好的光遮蔽性,第一導電層係位於黑色矩陣光阻之下方。 In one embodiment, the color filter layer comprises a color filter and a black matrix resist. The black matrix photoresist has good light shielding properties, and the first conductive layer is located in the black matrix light. Below the resistance.

於一實施例中,第一導電層係與薄膜電晶體元件層內之源極線(Source line)重疊。 In one embodiment, the first conductive layer overlaps the source line within the thin film transistor element layer.

於一實施例中,內嵌式觸控面板之觸控模式與顯示模式係分時驅動,並且內嵌式觸控面板係利用顯示週期之空白區間(Blanking interval)運作於觸控模式。 In one embodiment, the touch mode and the display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel operates in the touch mode by using a blanking interval of the display period.

於一實施例中,當內嵌式觸控面板運作於顯示模 式時,共同電壓電極係維持於直流(DC)電壓、交流(AC)電壓且該複數個觸控感測電極係維持於直流電壓、交流電壓、與共同電壓電極相關之電壓或呈現浮接(Floating)狀態。 In an embodiment, when the in-cell touch panel operates on the display mode In the formula, the common voltage electrode is maintained at a direct current (DC) voltage, an alternating current (AC) voltage, and the plurality of touch sensing electrodes are maintained at a direct current voltage, an alternating voltage, a voltage associated with the common voltage electrode, or exhibit a floating connection ( Floating) status.

於一實施例中,該共同電壓電極具有單一個共同電壓電極區域同時與該複數個觸控感測電極均重疊,當內嵌式觸控面板運作於觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且共同電壓電極係施加與觸控感測訊號同頻、同幅或同相之觸控相關訊號。 In one embodiment, the common voltage electrode has a single common voltage electrode region and overlaps with the plurality of touch sensing electrodes. When the embedded touch panel operates in the touch mode, the plurality of touch senses The measuring electrode applies a touch sensing signal and the common voltage electrode applies a touch-related signal of the same frequency, same-sense or in-phase as the touch sensing signal.

於一實施例中,共同電壓電極具有單一個共同電壓電極區域同時與該複數個觸控感測電極均重疊,當內嵌式觸控面板運作於觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且共同電壓電極係與訊號源斷路或呈現浮接(Floating)狀態。 In one embodiment, the common voltage electrode has a single common voltage electrode region and overlaps with the plurality of touch sensing electrodes. When the embedded touch panel operates in the touch mode, the plurality of touch sensing The electrode system applies a touch sensing signal and the common voltage electrode is disconnected from the signal source or assumes a floating state.

於一實施例中,共同電壓電極具有複數個共同電壓電極區域分別與該複數個觸控感測電極重疊,當內嵌式觸控面板運作於觸控模式時,該複數個觸控感測電極係依序施加複數個觸控感測訊號且該複數個共同電壓電極係相對應地依序施加與該複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號,或該複數個共同電壓電極係相對應地依序與訊號源斷路或呈現浮接(Floating)狀態。 In one embodiment, the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping the plurality of touch sensing electrodes. When the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes Applying a plurality of touch sensing signals sequentially, and the plurality of common voltage electrodes sequentially apply a plurality of touch-related signals in the same frequency, same-sense, or in-phase as the plurality of touch sensing signals, or The plurality of common voltage electrodes are sequentially disconnected from the signal source or in a floating state.

於一實施例中,共同電壓電極具有單一個共同電壓電極區域同時與該複數個觸控感測電極均重疊,當內嵌式 觸控面板運作於觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且薄膜電晶體元件層內之源極線(Source line)或閘極線(Gate line)係施加與觸控感測訊號同頻、同幅或同相之觸控相關訊號。 In an embodiment, the common voltage electrode has a single common voltage electrode region and overlaps with the plurality of touch sensing electrodes, and is embedded. When the touch panel operates in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and the source line or the gate line in the thin film transistor layer Apply touch-sensitive signals of the same frequency, same-sense or in-phase as the touch sensing signals.

於一實施例中,共同電壓電極具有複數個共同電壓電極區域分別與該複數個觸控感測電極重疊,當內嵌式觸控面板運作於觸控模式時,該複數個觸控感測電極係依序施加複數個觸控感測訊號,且薄膜電晶體元件層內之源極線(Source line)或閘極線(Gate line)係相對應地依序施加與該複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號。 In one embodiment, the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping the plurality of touch sensing electrodes. When the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes A plurality of touch sensing signals are sequentially applied, and a source line or a gate line in the layer of the thin film transistor component is sequentially applied and the plurality of touch sensing signals are sequentially applied. A plurality of touch-related signals of the same frequency, same-width or in-phase.

於一實施例中,薄膜電晶體元件層內還設置有一第二導電層,且第二導電層係與第一導電層電性連接。 In one embodiment, a second conductive layer is further disposed in the thin film transistor element layer, and the second conductive layer is electrically connected to the first conductive layer.

於一實施例中,第二導電層係與薄膜電晶體元件層中之源極線及汲極線同時形成。 In one embodiment, the second conductive layer is formed simultaneously with the source line and the drain line in the thin film transistor element layer.

於一實施例中,第二導電層與第一導電層係彼此重疊且並聯。 In an embodiment, the second conductive layer and the first conductive layer are overlapped and connected to each other.

於一實施例中,第二導電層係透過一通孔形成跨橋結構來跨過該第一導電層。 In one embodiment, the second conductive layer forms a cross-bridge structure through a via to cross the first conductive layer.

於一實施例中,當疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,疊層結構會額外多空出一源極線之空間,並且與第一導電層電性連接之第二導電層係利用額外多空出的源極線之空間作為觸控電極之走線。 In an embodiment, when the stacked structure has a Half Source Driving (HSD) architecture, the stacked structure additionally has a space of a source line and is electrically connected to the first conductive layer. The second conductive layer uses the space of the extra vacant source line as the trace of the touch electrode.

於一實施例中,不作為觸控走線或訊號線之第二導電層與不作為觸控感測電極使用之第一導電層之間透過通孔(Via)電性連接,再經由通孔與共同電壓電極電性連接,以進一步增加共同電壓電極之導電性。 In one embodiment, the second conductive layer that is not used as the touch trace or the signal line is electrically connected to the first conductive layer that is not used as the touch sensing electrode, and is electrically connected through the via hole. The voltage electrodes are electrically connected to further increase the conductivity of the common voltage electrode.

於一實施例中,內嵌式觸控面板之觸控模式與顯示模式的驅動時間至少有部分重疊。 In an embodiment, the touch mode of the in-cell touch panel and the driving mode of the display mode at least partially overlap.

於一實施例中,當內嵌式觸控面板運作於觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號,共同電壓電極或源極線可於一部份時間呈現浮接(Floating)狀態並於另一部份時間施加與觸控感測訊號同頻、同幅或同相之一觸控相關訊號。 In one embodiment, when the in-cell touch panel operates in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal, and the common voltage electrode or source line can be used for a part of the time. The floating state is presented and the touch-sensitive signal of the same frequency, the same or the same phase as the touch sensing signal is applied for another part of the time.

相較於先前技術,根據本發明之內嵌式觸控面板及其佈局具有下列優點: Compared with the prior art, the in-cell touch panel and its layout according to the present invention have the following advantages:

(1)其疊層結構簡單,容易生產並降低成本。 (1) The laminated structure is simple, easy to produce and reduce cost.

(2)其觸控電極、共同電壓電極及其走線之設計簡單。 (2) The design of the touch electrode, the common voltage electrode and the trace thereof is simple.

(3)透過新的佈局方式有效降低對液晶觸控面板光學上的影響。 (3) Effectively reduce the optical impact on the LCD touch panel through a new layout.

(4)有效降低共同電壓電極本身的電阻電容負載(RC Loading)。 (4) Effectively reduce the resistance and capacitance load of the common voltage electrode itself (RC Loading).

(5)觸控作動時同時控制共同電壓電極以大幅降低觸控面板的整體電阻電容負載。 (5) Simultaneously controlling the common voltage electrode during touch actuation to greatly reduce the overall resistance and capacitance load of the touch panel.

關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

1、2、3A~3D、7A‧‧‧疊層結構 1, 2, 3A ~ 3D, 7A‧‧‧ laminated structure

10、20、30、70‧‧‧基板 10, 20, 30, 70‧‧‧ substrates

11、21、31、71‧‧‧薄膜電晶體元件層 11, 21, 31, 71‧‧ ‧ thin film transistor component layer

12、23、32、72‧‧‧液晶層 12, 23, 32, 72‧‧‧ liquid crystal layer

13、24、33、73‧‧‧彩色濾光層 13, 24, 33, 73‧‧‧ color filter layer

14、25、34、74‧‧‧玻璃層 14, 25, 34, 74‧‧ ‧ glass layer

15、22‧‧‧觸控感應層 15, 22‧‧‧ touch sensing layer

16、26‧‧‧偏光片 16, 26‧‧‧ polarizers

17、27‧‧‧黏合劑 17, 27‧‧‧Binders

18、28‧‧‧上覆透鏡 18, 28‧‧‧Overlying lens

CF‧‧‧彩色濾光片 CF‧‧‧ color filters

BM‧‧‧黑色矩陣光阻 BM‧‧‧ Black Matrix Resistor

M2、M3‧‧‧導電層 M2, M3‧‧‧ conductive layer

CITO‧‧‧共同電壓電極 CITO‧‧‧Common voltage electrode

PITO‧‧‧像素(Pixel)氧化銦錫 PITO‧‧‧Pixel Indium Tin Oxide

VIA‧‧‧通孔 VIA‧‧‧through hole

LC‧‧‧液晶單元 LC‧‧‧Liquid Crystal Unit

ISO‧‧‧絕緣層 ISO‧‧‧Insulation

S、S1~S3‧‧‧源極線 S, S1~S3‧‧‧ source line

D‧‧‧汲極線 D‧‧‧汲极线

G、G1~G3‧‧‧閘極線 G, G1~G3‧‧‧ gate line

TP1、TP2、TP‧‧‧內嵌式自電容觸控面板 TP1, TP2, TP‧‧‧ embedded self-capacitive touch panel

TE、TE1~TE3‧‧‧觸控感測電極 TE, TE1~TE3‧‧‧ touch sensing electrodes

VCOM、VCOM1~VCOM3‧‧‧共同電壓電極區域 VCOM, VCOM1~VCOM3‧‧‧ common voltage electrode area

TS1~TS3‧‧‧觸控感測訊號 TS1~TS3‧‧‧ touch sensing signal

圖1及圖2係分別繪示內嵌式電容式觸控面板及On-Cell電容式觸控面板的疊層結構示意圖。 1 and 2 are schematic diagrams showing a laminated structure of an in-cell capacitive touch panel and an On-Cell capacitive touch panel, respectively.

圖3A至圖3D係分別繪示根據本發明之不同具體實施例之內嵌式自電容觸控面板之疊層結構示意圖。 3A to 3D are schematic diagrams showing a laminated structure of an in-cell self-capacitive touch panel according to different embodiments of the present invention.

圖4A係繪示內嵌式自電容觸控面板之觸控感測電極及其走線的示意圖。 4A is a schematic diagram showing a touch sensing electrode of an in-cell self-capacitive touch panel and a trace thereof.

圖4B係繪示不作為觸控感測電極之部分的第一導電層透過通孔與共同電壓電極電性連接的示意圖。 FIG. 4B is a schematic diagram showing the first conductive layer that is not part of the touch sensing electrode electrically connected to the common voltage electrode through the through hole.

圖5A係繪示共同電壓電極具有單一個共同電壓電極區域同時與第一觸控感測電極~第三觸控感測電極均重疊之示意圖。 FIG. 5A is a schematic diagram showing a common voltage electrode having a single common voltage electrode region and overlapping with both the first touch sensing electrode and the third touch sensing electrode.

圖5B至圖5D係分別繪示不同實施例中之內嵌式自電容觸控面板之各訊號於顯示模式與觸控模式下之時序圖。 5B to FIG. 5D are timing diagrams of respective signals of the in-cell self-capacitive touch panel in the display mode and the touch mode in different embodiments.

圖6A係繪示共同電壓電極具有第一共同電壓電極區域~第三共同電壓電極區域分別與第一觸控感測電極~第三觸控感測電極重疊之示意圖。 6A is a schematic diagram showing that the common voltage electrode has a first common voltage electrode region to a third common voltage electrode region overlapping with the first touch sensing electrode to the third touch sensing electrode, respectively.

圖6B係繪示圖6A中之內嵌式自電容觸控面板之各訊號於顯示模式與觸控模式下之時序圖。 FIG. 6B is a timing diagram of the signals of the in-cell self-capacitive touch panel of FIG. 6A in the display mode and the touch mode.

圖7A係繪示於內嵌式自電容觸控面板之疊層結構中的第二導電層透過通孔與第一導電層電性連接之示意圖。 FIG. 7A is a schematic diagram showing the second conductive layer electrically connected to the first conductive layer through the through hole in the stacked structure of the in-cell self-capacitive touch panel.

圖7B係繪示於內嵌式自電容觸控面板之疊層結構中的第二導電層與第一導電層之間透過通孔電性連接,再經由通孔與共同電壓電極電性連接之示意圖。 7B is a schematic diagram of the second conductive layer and the first conductive layer in the laminated structure of the in-cell self-capacitive touch panel electrically connected through the through hole, and then electrically connected to the common voltage electrode via the through hole. schematic diagram.

圖7C係繪示內嵌式自電容觸控面板之畫素設計之一實施例。 FIG. 7C illustrates an embodiment of a pixel design of an in-cell self-capacitance touch panel.

圖8係繪示內嵌式自電容觸控面板中之第二導電層所形成的觸控走線與訊號線彼此間隔排列且不同的感測電極之間透過觸控走線經由通孔形成跨橋連接之示意圖。 FIG. 8 illustrates that the touch traces and the signal lines formed by the second conductive layer in the in-cell self-capacitance touch panel are spaced apart from each other, and different sensing electrodes are formed across the through-holes through the touch traces. Schematic diagram of the bridge connection.

圖9A至圖9C係分別繪示由網格狀排列的第一導電層所形成具有不同形狀的觸控感測電極之示意圖。 9A to 9C are schematic views respectively showing touch sensing electrodes having different shapes formed by grid-shaped first conductive layers.

根據本發明之一較佳具體實施例為一種內嵌式的電容式觸控面板。實際上,由於內嵌式的電容式觸控面板可達成最薄化的觸控面板設計,可廣泛應用於智慧型手機、平板電腦及筆記型電腦等各種可攜式消費性電子產品上。 According to a preferred embodiment of the present invention, an in-cell capacitive touch panel is provided. In fact, because the in-cell capacitive touch panel can achieve the thinnest touch panel design, it can be widely used in various portable consumer electronic products such as smart phones, tablets and notebook computers.

於此實施例中,內嵌式的電容式觸控面板所適用的顯示器可以是採用橫向電場效應顯示技術(In-Plane-Switching Liquid Crystal,IPS)或由其延伸的邊界電場切換廣視角技術(Fringe Field Switching,FFS)或高階超廣視角技術(Advanced Hyper-Viewing Angle,AHVA)之顯示器, 但不以此為限。 In this embodiment, the display of the in-cell capacitive touch panel may be an In-Plane-Switching Liquid Crystal (IPS) or a boundary electric field extending therefrom to switch the wide viewing angle technology ( Fringe Field Switching (FFS) or Advanced Hyper-Viewing Angle (AHVA) display, But not limited to this.

一般而言,目前市場上的主流電容式觸控感測技術應為投射式電容觸控感測技術,可分為互電容(Mutual capacitance)及自電容(Self capacitance)兩種。互電容觸控感測技術就是當觸碰發生時,會在鄰近兩層電極間產生電容耦合的現象,並由電容量變化來確定觸碰動作的發生;自電容觸控感測技術就是觸控物與電極間產生電容耦合,並量測電極的電容量變化,以確定觸碰動作的發生。 In general, the mainstream capacitive touch sensing technology currently on the market should be a projected capacitive touch sensing technology, which can be divided into Mutual capacitance and Self capacitance. Mutual-capacitive touch sensing technology is a phenomenon in which capacitive coupling occurs between two adjacent electrodes when a touch occurs, and the occurrence of a touch action is determined by a change in capacitance; a self-capacitive touch sensing technology is a touch A capacitive coupling is generated between the object and the electrode, and the capacitance change of the electrode is measured to determine the occurrence of a touch action.

需說明的是,此實施例中之內嵌式的電容式觸控面板可採用採用自電容觸控感測技術,其複數個觸控感測電極係由網格狀排列的第一導電層所形成,並藉由佈局方式降低內嵌式觸控元件對LCD在電性及光學上的影響。 It should be noted that the in-cell capacitive touch panel in this embodiment may adopt a self-capacitive touch sensing technology, and the plurality of touch sensing electrodes are arranged by a first conductive layer arranged in a grid shape. Forming and reducing the influence of the in-cell touch elements on the electrical and optical effects of the LCD by layout.

接下來,將就此實施例之內嵌式的自電容觸控面板的疊層結構進行詳細之說明。 Next, the laminated structure of the in-cell self-capacitive touch panel of this embodiment will be described in detail.

如圖3A所示,於一實施例中,內嵌式的自電容觸控面板之每個像素的疊層結構3A由下至上可依序包含:基板30、薄膜電晶體元件層31、液晶層32、彩色濾光層33及玻璃層34。 As shown in FIG. 3A, in an embodiment, the stacked structure 3A of each pixel of the in-cell self-capacitive touch panel may be sequentially included from bottom to top: a substrate 30, a thin film transistor element layer 31, and a liquid crystal layer. 32. A color filter layer 33 and a glass layer 34.

薄膜電晶體元件層31設置於基板30上。薄膜電晶體元件層31內設置有第一導電層M3及共同電壓電極CITO。第一導電層31係以網格狀排列。液晶層32包含複數個液晶單元LC且係設置於薄膜電晶體元件層31上方。彩色濾光層33設置 於液晶層32上方。玻璃層34設置於彩色濾光層33上方。 The thin film transistor element layer 31 is disposed on the substrate 30. A first conductive layer M3 and a common voltage electrode CITO are disposed in the thin film transistor element layer 31. The first conductive layers 31 are arranged in a grid shape. The liquid crystal layer 32 includes a plurality of liquid crystal cells LC and is disposed above the thin film transistor element layer 31. Color filter layer 33 setting Above the liquid crystal layer 32. The glass layer 34 is disposed above the color filter layer 33.

實際上,第一導電層M3可由金屬或其他任意的導電材料構成,共同電壓電極CITO可由氧化銦錫層構成,並無特定之限制。 Actually, the first conductive layer M3 may be composed of metal or any other conductive material, and the common voltage electrode CITO may be composed of an indium tin oxide layer, and is not particularly limited.

彩色濾光層33包含彩色濾光片(Color Filter)CF及黑色矩陣光阻(Black Matrix Resist)BM兩部分,其中黑色矩陣光阻BM具有良好的光遮蔽性,可應用於彩色濾光層33中,作為區隔紅(R)、綠(G)、藍(B)三種顏色的彩色濾光片之材料。於此實施例中,網格狀排列的第一導電層M3係位於黑色矩陣光阻BM之下方並受到黑色矩陣光阻BM之遮蔽。 The color filter layer 33 includes a color filter CF and a black matrix photoresist (Black Matrix Resist) BM. The black matrix photoresist BM has good light shielding properties and can be applied to the color filter layer 33. Medium is used as a material for color filters of three colors of red (R), green (G), and blue (B). In this embodiment, the grid-shaped first conductive layer M3 is located below the black matrix photoresist BM and is shielded by the black matrix photoresist BM.

需說明的是,於圖3A所繪示的疊層結構3A中,第一導電層M3係形成於共同電壓電極CITO之後,並且第一導電層M3與共同電壓電極CITO之間透過絕緣層ISO彼此分隔,使得第一導電層M3不會與位於其下方的共同電壓電極CITO電性相連。 It should be noted that, in the stacked structure 3A illustrated in FIG. 3A, the first conductive layer M3 is formed after the common voltage electrode CITO, and the first conductive layer M3 and the common voltage electrode CITO are transmitted through the insulating layer ISO. The separation is such that the first conductive layer M3 is not electrically connected to the common voltage electrode CITO located under it.

於另一實施例中,於圖3B所繪示的疊層結構3B中,第一導電層M3亦形成於共同電壓電極CITO之後,並且第一導電層M3與共同電壓電極CITO之間透過絕緣層ISO彼此分隔,但第一導電層M3可透過一通孔VIA與位於其下方的共同電壓電極CITO電性相連。 In another embodiment, in the stacked structure 3B illustrated in FIG. 3B, the first conductive layer M3 is also formed after the common voltage electrode CITO, and the first conductive layer M3 and the common voltage electrode CITO are transmitted through the insulating layer. The ISOs are separated from each other, but the first conductive layer M3 is electrically connected to the common voltage electrode CITO located underneath through a via VIA.

此外,於圖3C所繪示的疊層結構3C中,第一導電層M3係形成於共同電壓電極CITO之前,並且第一導電層M3 與共同電壓電極CITO之間透過絕緣層ISO彼此分隔,使得共同電壓電極CITO不會與位於其下方的第一導電層M3電性相連。 In addition, in the stacked structure 3C illustrated in FIG. 3C, the first conductive layer M3 is formed before the common voltage electrode CITO, and the first conductive layer M3 The common voltage electrode CITO is separated from each other by the insulating layer ISO so that the common voltage electrode CITO is not electrically connected to the first conductive layer M3 located under it.

於另一實施例中,於圖3D所繪示的疊層結構3D中,第一導電層M3亦形成於共同電壓電極CITO之前,並且第一導電層M3與共同電壓電極CITO之間透過絕緣層ISO彼此分隔,但共同電壓電極CITO可透過一通孔VIA與位於其下方的第一導電層M3電性相連。 In another embodiment, in the stacked structure 3D illustrated in FIG. 3D, the first conductive layer M3 is also formed before the common voltage electrode CITO, and the first conductive layer M3 and the common voltage electrode CITO are transmitted through the insulating layer. The ISOs are separated from each other, but the common voltage electrode CITO is electrically connected to the first conductive layer M3 located underneath through a via VIA.

接著,如圖4A所示,內嵌式的自電容觸控面板TP1上之複數個觸控感測電極TE係由網格狀排列的第一導電層M3所形成,該複數個觸控感測電極TE之間不相連且間隔一特定距離。該複數個觸控感測電極TE與共同電壓電極CITO並不相連。實際上,上述的特定距離可以像素(Pixel)或子像素(Sub-pixel)為單位,但不以此為限。 Then, as shown in FIG. 4A, a plurality of touch sensing electrodes TE on the in-cell self-capacitive touch panel TP1 are formed by a grid-shaped first conductive layer M3, and the plurality of touch sensing electrodes are formed. The electrodes TE are not connected and are separated by a certain distance. The plurality of touch sensing electrodes TE are not connected to the common voltage electrode CITO. In fact, the above specific distance may be in units of pixels (Pixel) or sub-pixels, but is not limited thereto.

此外,如圖4B所示,於內嵌式的自電容觸控面板TP2中,不作為觸控感測電極TE之部分的第一導電層M3可透過通孔VIA與共同電壓電極CITO電性連接,以作為共同電壓電極CITO之走線。需說明的是,雖然圖4B中之作為觸控感測電極TE亦由第一導電層M3形成,但作為觸控感測電極TE及其走線的第一導電層M3不與共同電壓電極CITO電性連接,而不作為觸控感測電極TE之部分的第一導電層M3則透過通孔VIA與共同電壓電極CITO電性連接,以作為共同電壓電極CITO之走線。 In addition, as shown in FIG. 4B, in the in-cell self-capacitive touch panel TP2, the first conductive layer M3, which is not part of the touch sensing electrode TE, can be electrically connected to the common voltage electrode CITO through the via VIA. Take the trace of the common voltage electrode CITO. It should be noted that although the touch sensing electrode TE is also formed by the first conductive layer M3 in FIG. 4B, the first conductive layer M3 as the touch sensing electrode TE and its trace does not share the common voltage electrode CITO. The first conductive layer M3, which is not electrically connected to the touch sensing electrode TE, is electrically connected to the common voltage electrode CITO through the via VIA as a trace of the common voltage electrode CITO.

接著,請參照圖5A,於內嵌式的自電容觸控面板TP中,網格狀排列的第一導電層M3分別形成第一觸控感測電極TE1~第三觸控感測電極TE3且共同電壓電極CITP具有單一個共同電壓電極區域VCOM同時與第一觸控感測電極TE1~第三觸控感測電極TE3均重疊,但第一觸控感測電極TE1~第三觸控感測電極TE3不與共同電壓電極CITO電性連接。不作為觸控感測電極之部分的第一導電層M3則可透過通孔VIA與共同電壓電極CITO電性連接,以作為共同電壓電極CITO之走線並分別位於第一觸控感測電極TE1~第三觸控感測電極TE3之間。 Then, referring to FIG. 5A, in the in-cell self-capacitive touch panel TP, the first conductive layer M3 arranged in a grid shape forms the first touch sensing electrode TE1 to the third touch sensing electrode TE3, respectively. The common voltage electrode CITP has a single common voltage electrode region VCOM and overlaps both the first touch sensing electrode TE1 and the third touch sensing electrode TE3, but the first touch sensing electrode TE1 to the third touch sensing The electrode TE3 is not electrically connected to the common voltage electrode CITO. The first conductive layer M3, which is not part of the touch sensing electrode, can be electrically connected to the common voltage electrode CITO through the via VIA as a common voltage electrode CITO trace and respectively located at the first touch sensing electrode TE1~ The third touch sensing electrode TE3 is between.

需說明的是,本發明之內嵌式的自電容觸控面板TP之觸控模式與顯示模式可採用分時驅動之模式且係利用顯示週期之空白區間(Blanking interval)運作於觸控模式下,但不以此為限。於實際應用中,本發明之內嵌式的自電容觸控面板TP之觸控模式與顯示模式的驅動時間亦可有至少部分重疊的情況。 It should be noted that the touch mode and the display mode of the embedded self-capacitive touch panel TP of the present invention can adopt the time-division driving mode and operate in the touch mode by using the blanking interval of the display period. , but not limited to this. In practical applications, the touch mode of the embedded self-capacitive touch panel TP of the present invention and the driving time of the display mode may also overlap at least partially.

於一實施例中,如圖5B所示,當內嵌式的自電容觸控面板TP運作於顯示模式時,單一個共同電壓電極區域VCOM可維持於直流(DC)電壓或交流(AC)電壓,而第一觸控感測電極TE1~第三觸控感測電極TE3則可維持於直流電壓、交流電壓、與單一個共同電壓電極區域VCOM相關之電壓或呈現浮接(Floating)狀態。當內嵌式的自電容觸控面板TP運作於觸控模式時,第一觸控感測電極TE1~第三觸控感測電極TE3係分別 施加觸控感測訊號TS1~TS3且單一個共同電壓電極區域VCOM係施加與觸控感測訊號TS1~TS3同頻、同幅或同相之觸控相關訊號。 In one embodiment, as shown in FIG. 5B, when the in-cell self-capacitive touch panel TP operates in the display mode, a single common voltage electrode region VCOM can be maintained at a direct current (DC) voltage or an alternating current (AC) voltage. The first touch sensing electrode TE1 to the third touch sensing electrode TE3 can be maintained at a DC voltage, an AC voltage, a voltage associated with a single common voltage electrode region VCOM, or assume a floating state. When the embedded self-capacitive touch panel TP is in the touch mode, the first touch sensing electrode TE1 to the third touch sensing electrode TE3 are respectively The touch sensing signals TS1~TS3 are applied and a single common voltage electrode region VCOM is applied with touch-sensitive signals of the same frequency, same-sense or in-phase as the touch sensing signals TS1~TS3.

於另一實施例中,如圖5C所示,當內嵌式的自電容觸控面板TP運作於觸控模式時,第一觸控感測電極TE1~第三觸控感測電極TE3係分別施加觸控感測訊號TS1~TS3,但單一個共同電壓電極區域VCOM係與訊號源斷路或呈現浮接(Floating)狀態。 In another embodiment, as shown in FIG. 5C, when the in-cell self-capacitive touch panel TP is in the touch mode, the first touch sensing electrode TE1 to the third touch sensing electrode TE3 are respectively The touch sensing signals TS1~TS3 are applied, but the single common voltage electrode region VCOM is disconnected from the signal source or assumes a floating state.

於另一實施例中,如圖5D所示,當內嵌式的自電容觸控面板TP運作於觸控模式時,第一觸控感測電極TE1~第三觸控感測電極TE3係分別施加觸控感測訊號TS1~TS3,但薄膜電晶體元件層內之源極線S1~S3或閘極線G1~G3係施加與觸控感測訊號TS1~TS3同頻、同幅或同相之觸控相關訊號。 In another embodiment, as shown in FIG. 5D, when the in-cell self-capacitance touch panel TP is in the touch mode, the first touch sensing electrode TE1 to the third touch sensing electrode TE3 are respectively The touch sensing signals TS1~TS3 are applied, but the source lines S1~S3 or the gate lines G1~G3 in the thin film transistor layer are applied in the same frequency, same plane or in phase with the touch sensing signals TS1~TS3. Touch related signals.

除了上述實施例之外,共同電壓電極CITO亦可能具有複數個共同電壓電極區域分別與不同的觸控感測電極重疊。 In addition to the above embodiments, the common voltage electrode CITO may have a plurality of common voltage electrode regions respectively overlapping with different touch sensing electrodes.

請參照圖6A,共同電壓電極CITO具有第一共同電壓電極區域VCOM1~第三共同電壓電極區域VCOM3,並且第一共同電壓電極區域VCOM1~第三共同電壓電極區域VCOM3分別與第一觸控感測電極TE1~第三觸控感測電極TE3重疊。 Referring to FIG. 6A, the common voltage electrode CITO has a first common voltage electrode region VCOM1 to a third common voltage electrode region VCOM3, and the first common voltage electrode region VCOM1 to the third common voltage electrode region VCOM3 are respectively coupled to the first touch sensing. The electrodes TE1 to the third touch sensing electrodes TE3 overlap.

當內嵌式自電容觸控面板TP運作於觸控模式時,第一觸控感測電極TE1~第三觸控感測電極TE3係依序施加 第一觸控感測訊號TX1~第三觸控感測訊號TX3且第一共同電壓電極區域VCOM1~第三共同電壓電極區域VCOM3可相對應地依序施加與第一觸控感測訊號TX1~第三觸控感測訊號TX3同頻、同幅或同相之複數個觸控相關訊號。於另一實施例中,第一共同電壓電極區域VCOM1~第三共同電壓電極區域VCOM3亦可相對應地依序與訊號源斷路或呈現浮接(Floating)狀態。 When the embedded self-capacitive touch panel TP is in the touch mode, the first touch sensing electrodes TE1 to the third touch sensing electrodes TE3 are sequentially applied. The first touch sensing signal TX1 to the third touch sensing signal TX3 and the first common voltage electrode region VCOM1 to the third common voltage electrode region VCOM3 are sequentially applied to the first touch sensing signal TX1~ The third touch sensing signal TX3 has a plurality of touch-related signals of the same frequency, same-width or in-phase. In another embodiment, the first common voltage electrode region VCOM1 to the third common voltage electrode region VCOM3 may also be sequentially disconnected from the signal source or assume a floating state.

需說明的是,於實際應用中,當內嵌式自電容觸控面板TP運作於觸控模式時,單一個共同電壓電極區域VCOM、第一共同電壓電極區域VCOM1~第三共同電壓電極區域VCOM3或源極線均可於一部份時間呈現浮接(Floating)狀態並於另一部份時間施加與觸控感測訊號同頻、同幅或同相之一觸控相關訊號,並無特定之限制。 It should be noted that, in practical applications, when the embedded self-capacitive touch panel TP operates in the touch mode, a single common voltage electrode region VCOM, a first common voltage electrode region VCOM1 to a third common voltage electrode region VCOM3 Or the source line can display a floating state for a part of the time and a touch-sensitive signal of the same frequency, the same or the same phase as the touch sensing signal for another part of the time, and there is no specific limit.

如圖7A所示,於另一實施例中,於內嵌式的自電容觸控面板之疊層結構7A中,薄膜電晶體元件層71內還設置有第二導電層M2,並且第二導電層M2可透過通孔VIA與第一導電層M3電性連接。實際上,第二導電層M2可以與薄膜電晶體元件層71中之源極線S及汲極線D同時形成,並且第一導電層M3可與薄膜電晶體元件層71內之源極線S重疊,但不以此為限。圖7C則係繪示內嵌式自電容觸控面板之畫素設計之一實施例,但不以此為限。 As shown in FIG. 7A, in another embodiment, in the laminated structure 7A of the in-cell self-capacitive touch panel, the second conductive layer M2 is further disposed in the thin film transistor element layer 71, and the second conductive layer is disposed. The layer M2 is electrically connected to the first conductive layer M3 through the via VIA. In fact, the second conductive layer M2 may be formed simultaneously with the source line S and the drain line D in the thin film transistor element layer 71, and the first conductive layer M3 may be connected to the source line S in the thin film transistor element layer 71. Overlap, but not limited to this. FIG. 7C illustrates an embodiment of a pixel design of an in-cell self-capacitance touch panel, but is not limited thereto.

於實際應用中,第二導電層M2與第一導電層M3 可彼此重疊且並聯,並且第二導電層M2可透過通孔VIA形成跨橋結構來跨過第一導電層M3,但不以此為限。 In practical applications, the second conductive layer M2 and the first conductive layer M3 The second conductive layer M2 may be formed across the first conductive layer M3 through the via hole VIA, but is not limited thereto.

於實際應用中,若內嵌式的自電容觸控面板之疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,疊層結構會額外多空出一源極線之空間,並且與第一導電層M3電性連接之第二導電層M2可利用額外多空出的源極線S之空間作為觸控電極TE之走線,但不以此為限。 In practical applications, if the laminated structure of the embedded self-capacitive touch panel has a Half Source Driving (HSD) architecture, the laminated structure will additionally have a space of a source line, and The second conductive layer M2 electrically connected to the first conductive layer M3 can use the space of the additional source line S as the trace of the touch electrode TE, but is not limited thereto.

於此實施例中,如圖8所示,第二導電層M2所形成的觸控走線M2(Touch)與訊號線M2(Data)彼此間隔排列,所以第二導電層M2的數目減少為原來的一半。由於第二導電層M2與第一導電層M3可完全重疊,並且不同的感測電極TE之間可透過觸控走線M2(Touch)經由通孔VIA形成跨橋連接,因此,由網格狀排列的第一導電層M3所形成的觸控感測電極TE所涵蓋的面積會變大,因而縮減了觸控感測之盲區(Dead zone)的面積,使得內嵌式的自電容觸控面板TP的有效觸控感測區域的面積亦隨之變大。 In this embodiment, as shown in FIG. 8 , the touch trace M2 (Touch) formed by the second conductive layer M2 and the signal line M2 (Data) are spaced apart from each other, so the number of the second conductive layer M2 is reduced to the original. Half of it. The second conductive layer M2 and the first conductive layer M3 can be completely overlapped, and the different sensing electrodes TE can be connected to each other through the through-hole VIA through the touch-line M2 (Touch). The area covered by the touch sensing electrodes TE formed by the arranged first conductive layer M3 is increased, thereby reducing the area of the dead zone of the touch sensing, so that the embedded self-capacitive touch panel The area of the effective touch sensing area of the TP also increases.

需說明的是,此實施例進行觸控感測時之共同電壓電極CITO與源極線S及閘極線G之訊號控制可與前述任一實施例相同,並無特定之限制。此外,不作為觸控感測電極使用的第一導電層M3亦可如前述實施例一樣透過通孔VIA與共同電壓電極CITO電性連接,以增加共同電壓電極CITO之導電性。另外,如圖7B所示,不作為觸控走線或訊號線之第二導 電層M2亦可與不作為觸控感測電極使用的第一導電層M3經由VIA電性連接,再經由通孔VIA與共同電壓電極CITO電性連接,進一步增加共同電壓電極CITO之導電性。 It should be noted that the signal control of the common voltage electrode CITO and the source line S and the gate line G in the touch sensing of this embodiment may be the same as any of the foregoing embodiments, and is not particularly limited. In addition, the first conductive layer M3, which is not used as the touch sensing electrode, can be electrically connected to the common voltage electrode CITO through the via VIA as in the previous embodiment to increase the conductivity of the common voltage electrode CITO. In addition, as shown in FIG. 7B, it is not used as the second guide of the touch trace or the signal line. The electrical layer M2 can also be electrically connected to the first conductive layer M3, which is not used as the touch sensing electrode, via VIA, and electrically connected to the common voltage electrode CITO via the via VIA, thereby further increasing the conductivity of the common voltage electrode CITO.

請參照圖9A至圖9C,由網格狀排列的第一導電層M3所形成的觸控感測電極TE之形狀並不以傳統的矩形或四方形為限,於實際應用中,觸控感測電極TE之形狀亦可以是三角形(如圖9A所示)、六角形(如圖9B所示)、圓形(如圖9C所示)或其他任意的幾何形狀,並無特定之限制。 Referring to FIG. 9A to FIG. 9C , the shape of the touch sensing electrode TE formed by the first conductive layer M3 arranged in a grid shape is not limited to a conventional rectangular shape or a square shape. In practical applications, the touch feeling is limited. The shape of the measuring electrode TE may also be a triangle (as shown in FIG. 9A), a hexagon (as shown in FIG. 9B), a circular shape (as shown in FIG. 9C), or any other geometric shape, and is not particularly limited.

相較於先前技術,根據本發明之內嵌式觸控面板及其佈局具有下列優點: Compared with the prior art, the in-cell touch panel and its layout according to the present invention have the following advantages:

(1)其疊層結構簡單,容易生產並降低成本。 (1) The laminated structure is simple, easy to produce and reduce cost.

(2)其觸控電極、共同電壓電極及其走線之設計簡單。 (2) The design of the touch electrode, the common voltage electrode and the trace thereof is simple.

(3)透過新的佈局方式有效降低對液晶觸控面板光學上的影響。 (3) Effectively reduce the optical impact on the LCD touch panel through a new layout.

(4)有效降低共同電壓電極本身的電阻電容負載(RC Loading)。 (4) Effectively reduce the resistance and capacitance load of the common voltage electrode itself (RC Loading).

(5)觸控作動時同時控制共同電壓電極以大幅降低觸控面板的整體電阻電容負載。 (5) Simultaneously controlling the common voltage electrode during touch actuation to greatly reduce the overall resistance and capacitance load of the touch panel.

藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是 希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. Instead, its purpose is It is intended that the various modifications and equivalents may be included within the scope of the invention as claimed.

7A‧‧‧疊層結構 7A‧‧‧Laminated structure

70‧‧‧基板 70‧‧‧Substrate

71‧‧‧薄膜電晶體元件層 71‧‧‧Thin-film transistor component layer

72‧‧‧液晶層 72‧‧‧Liquid layer

73‧‧‧彩色濾光層 73‧‧‧Color filter layer

74‧‧‧玻璃層 74‧‧‧ glass layer

M3‧‧‧第一導電層 M3‧‧‧first conductive layer

M2‧‧‧第二導電層 M2‧‧‧Second conductive layer

CITO‧‧‧共同電壓電極 CITO‧‧‧Common voltage electrode

LC‧‧‧液晶單元 LC‧‧‧Liquid Crystal Unit

VIA‧‧‧通孔 VIA‧‧‧through hole

G‧‧‧閘極線 G‧‧‧ gate line

S‧‧‧源極線 S‧‧‧ source line

D‧‧‧汲極線 D‧‧‧汲极线

Claims (24)

一種內嵌式觸控面板,係為一內嵌式自電容(self-capacitive)觸控面板,該內嵌式觸控面板包含:複數個像素(Pixel),每個像素之一疊層結構包含:一基板;一薄膜電晶體元件層,設置於該基板上,該薄膜電晶體元件層內係設置有一第一導電層(M3)及一共同電壓電極(Common Electrode),其中該第一導電層係以網格狀(Mesh type)排列;一液晶層,設置於該薄膜電晶體元件層上方;一彩色濾光層,設置於該液晶層上方;以及一玻璃層,設置於該彩色濾光層上方;其中,該薄膜電晶體元件層內還設置有一第二導電層(M2),且該第二導電層係與該第一導電層電性連接。 An in-cell touch panel is an in-cell self-capacitive touch panel, the in-cell touch panel includes: a plurality of pixels (Pixel), and one of the stacked structures of each pixel includes a substrate; a thin film transistor element layer disposed on the substrate, the first layer of the transistor layer is provided with a first conductive layer (M3) and a common voltage electrode (Common Electrode), wherein the first conductive layer Aligning in a mesh type; a liquid crystal layer disposed above the thin film transistor element layer; a color filter layer disposed over the liquid crystal layer; and a glass layer disposed on the color filter layer The second conductive layer (M2) is further disposed in the thin film transistor element layer, and the second conductive layer is electrically connected to the first conductive layer. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該內嵌式觸控面板之複數個觸控感測電極係由網格狀排列的該第一導電層所形成。 The in-cell touch panel of claim 1, wherein the plurality of touch sensing electrodes of the in-cell touch panel are formed by the first conductive layer arranged in a grid pattern. 如申請專利範圍第2項所述之內嵌式觸控面板,其中該第一導電層與該共同電壓電極之間係透過一絕緣層彼此分隔。 The in-cell touch panel of claim 2, wherein the first conductive layer and the common voltage electrode are separated from each other by an insulating layer. 如申請專利範圍第2項所述之內嵌式觸控面板,其中該複數個觸控感測電極之間不相連且間隔一特定距離。 The in-cell touch panel of claim 2, wherein the plurality of touch sensing electrodes are not connected and spaced apart by a specific distance. 如申請專利範圍第4項所述之內嵌式觸控面板,其中該特定距離係為以像素(Pixel)或子像素(Sub-pixel)為單位。 The in-cell touch panel of claim 4, wherein the specific distance is in units of pixels or sub-pixels. 如申請專利範圍第2項所述之內嵌式觸控面板,其中不作 為觸控感測電極之部分的該第一導電層係透過一通孔(Via)與該共同電壓電極電性連接。 The in-cell touch panel as described in claim 2 of the patent application, wherein The first conductive layer that is part of the touch sensing electrode is electrically connected to the common voltage electrode through a via (Via). 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第一導電層係形成於該共同電壓電極之後。 The in-cell touch panel of claim 1, wherein the first conductive layer is formed after the common voltage electrode. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第一導電層係形成於該共同電壓電極之前。 The in-cell touch panel of claim 1, wherein the first conductive layer is formed before the common voltage electrode. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該彩色濾光層包含一彩色濾光片(Color Filter)及一黑色矩陣光阻(Black Matrix Resist),該黑色矩陣光阻具有良好的光遮蔽性,該第一導電層係位於該黑色矩陣光阻之下方。 The in-cell touch panel of claim 1, wherein the color filter layer comprises a color filter and a black matrix resist (Black Matrix Resist), the black matrix resist With good light shielding, the first conductive layer is located below the black matrix photoresist. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第一導電層係與該薄膜電晶體元件層內之一源極線(Source line)重疊。 The in-cell touch panel of claim 1, wherein the first conductive layer overlaps with a source line in the thin film transistor element layer. 如申請專利範圍第2項所述之內嵌式觸控面板,其中該內嵌式觸控面板之一觸控模式與一顯示模式係分時驅動,並且該內嵌式觸控面板係利用顯示週期之一空白區間(Blanking interval)運作於該觸控模式。 The in-cell touch panel of claim 2, wherein one touch mode and one display mode of the in-cell touch panel are time-divisionally driven, and the in-cell touch panel utilizes display One of the cycles, the blanking interval, operates in the touch mode. 如申請專利範圍第11項所述之內嵌式觸控面板,其中當該內嵌式觸控面板運作於該顯示模式時,該共同電壓電極係維持於直流(DC)電壓、交流(AC)電壓且該複數個觸控感測電極係維持於直流電壓、交流電壓、與該共同電壓電極相關之電壓或呈現浮接(Floating)狀態。 The in-cell touch panel of claim 11, wherein when the in-cell touch panel operates in the display mode, the common voltage electrode is maintained at a direct current (DC) voltage, alternating current (AC) The voltage and the plurality of touch sensing electrodes are maintained at a DC voltage, an AC voltage, a voltage associated with the common voltage electrode, or in a floating state. 如申請專利範圍第11項所述之內嵌式觸控面板,其中該共同電壓電極具有單一個共同電壓電極區域同時與該複 數個觸控感測電極均重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且該共同電壓電極係施加與該觸控感測訊號同頻、同幅或同相之一觸控相關訊號。 The in-cell touch panel of claim 11, wherein the common voltage electrode has a single common voltage electrode region and the complex The plurality of touch sensing electrodes are overlapped. When the in-cell touch panel is operated in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and the common voltage electrode is applied The touch sensing signal is related to one of the same frequency, the same or the same phase. 如申請專利範圍第11項所述之內嵌式觸控面板,其中該共同電壓電極具有單一個共同電壓電極區域同時與該複數個觸控感測電極均重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且該共同電壓電極係與訊號源斷路或呈現浮接(Floating)狀態。 The in-cell touch panel of claim 11, wherein the common voltage electrode has a single common voltage electrode region and overlaps the plurality of touch sensing electrodes, and the in-cell touch panel When operating in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and the common voltage electrode is disconnected from the signal source or assumes a floating state. 如申請專利範圍第11項所述之內嵌式觸控面板,其中該共同電壓電極具有複數個共同電壓電極區域分別與該複數個觸控感測電極重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係依序施加複數個觸控感測訊號且該複數個共同電壓電極係相對應地依序施加與該複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號,或該複數個共同電壓電極係相對應地依序與訊號源斷路或呈現浮接(Floating)狀態。 The in-cell touch panel of claim 11, wherein the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping the plurality of touch sensing electrodes, and the in-cell touch panel operates In the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals, and the plurality of common voltage electrodes are sequentially applied in the same manner as the plurality of touch sensing signals. The plurality of touch-related signals of the frequency, the same or the same phase, or the plurality of common voltage electrodes are sequentially disconnected from the signal source or in a floating state. 如申請專利範圍第11項所述之內嵌式觸控面板,其中該共同電壓電極具有單一個共同電壓電極區域同時與該複數個觸控感測電極均重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號且該薄膜電晶體元件層內之一源極線(Source line)或一閘極線(Gate line)係施加與該觸控感測訊號同頻、同幅或同相之一觸控相關訊號。 The in-cell touch panel of claim 11, wherein the common voltage electrode has a single common voltage electrode region and overlaps the plurality of touch sensing electrodes, and the in-cell touch panel When operating in the touch mode, the plurality of touch sensing electrodes apply a touch sensing signal and a source line or a gate line in the thin film transistor layer. A touch-sensitive signal is applied to one of the same frequency, the same or the same phase as the touch sensing signal. 如申請專利範圍第11項所述之內嵌式觸控面板,其中該共同電壓電極具有複數個共同電壓電極區域分別與該複數個觸控感測電極重疊,當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係依序施加複數個觸控感測訊號,且該薄膜電晶體元件層內之一源極線(Source line)或一閘極線(Gate line)係相對應地依序施加與該複數個觸控感測訊號同頻、同幅或同相之複數個觸控相關訊號。 The in-cell touch panel of claim 11, wherein the common voltage electrode has a plurality of common voltage electrode regions respectively overlapping the plurality of touch sensing electrodes, and the in-cell touch panel operates In the touch mode, the plurality of touch sensing electrodes sequentially apply a plurality of touch sensing signals, and one source line or one gate line in the thin film transistor layer ( The gate line is sequentially applied with a plurality of touch-related signals of the same frequency, same-width or in-phase as the plurality of touch sensing signals. 如申請專利範圍第11項所述之內嵌式觸控面板,其中當該內嵌式觸控面板運作於該觸控模式時,該複數個觸控感測電極係施加一觸控感測訊號,該共同電壓電極或源極線可於一部份時間呈現浮接(Floating)狀態並於另一部份時間施加與該觸控感測訊號同頻、同幅或同相之一觸控相關訊號。 The in-cell touch panel of claim 11, wherein the plurality of touch sensing electrodes apply a touch sensing signal when the in-cell touch panel operates in the touch mode The common voltage electrode or the source line can be in a floating state for a part of the time and a touch-sensitive signal of the same frequency, the same or the same phase as the touch sensing signal is applied at another part of the time. . 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係與該薄膜電晶體元件層中之一源極線及一汲極線同時形成。 The in-cell touch panel of claim 1, wherein the second conductive layer is formed simultaneously with one source line and one drain line of the thin film transistor element layer. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層與該第一導電層係彼此重疊且並聯。 The in-cell touch panel of claim 1, wherein the second conductive layer and the first conductive layer are overlapped and connected to each other. 如申請專利範圍第1項所述之內嵌式觸控面板,其中該第二導電層係透過一通孔形成跨橋結構來跨過該第一導電層。 The in-cell touch panel of claim 1, wherein the second conductive layer forms a bridge structure across the first conductive layer through a through hole. 如申請專利範圍第1項所述之內嵌式觸控面板,其中當該疊層結構具有半源極驅動(Half Source Driving,HSD)架構時,該疊層結構會額外多空出一源極線之空間,並且與 該第一導電層電性連接之該第二導電層係利用額外多空出的該源極線之空間作為該觸控電極之走線。 The in-cell touch panel of claim 1, wherein when the laminated structure has a half source driving (HSD) architecture, the laminated structure additionally has a source Line space, and with The second conductive layer electrically connected to the first conductive layer utilizes an extra space of the source line that is vacated as a trace of the touch electrode. 如申請專利範圍第1項所述之內嵌式觸控面板,其中不作為觸控走線或訊號線之該第二導電層與不作為觸控感測電極使用之該第一導電層之間透過通孔電性連接,再經由通孔與該共同電壓電極電性連接,以進一步增加該共同電壓電極之導電性。 The in-cell touch panel of claim 1, wherein the second conductive layer that is not used as the touch trace or the signal line passes through the first conductive layer that is not used as the touch sensing electrode. The hole is electrically connected, and is electrically connected to the common voltage electrode via the through hole to further increase the conductivity of the common voltage electrode. 如申請專利範圍第2項所述之內嵌式觸控面板,其中該內嵌式觸控面板之一觸控模式與一顯示模式的驅動時間至少有部分重疊。 The in-cell touch panel of claim 2, wherein the touch mode of one of the in-cell touch panels overlaps at least partially with the driving time of a display mode.
TW104135845A 2015-05-07 2015-10-30 In-cell touch panel TWI587036B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201562158322P 2015-05-07 2015-05-07
US201562162238P 2015-05-15 2015-05-15
US14/882,880 US20160109741A1 (en) 2014-10-17 2015-10-14 In-cell touch display system, in-cell touch panel and trace layout thereof

Publications (2)

Publication Number Publication Date
TW201640188A TW201640188A (en) 2016-11-16
TWI587036B true TWI587036B (en) 2017-06-11

Family

ID=57471569

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104135845A TWI587036B (en) 2015-05-07 2015-10-30 In-cell touch panel

Country Status (2)

Country Link
CN (1) CN106125996A (en)
TW (1) TWI587036B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690917B (en) * 2019-03-13 2020-04-11 友達光電股份有限公司 Pixel array substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201243688A (en) * 2011-04-27 2012-11-01 Lg Display Co Ltd In-cell type touch panel
US20130176251A1 (en) * 2012-01-09 2013-07-11 Nvidia Corporation Touch-screen input/output device touch sensing techniques
TWM518787U (en) * 2014-10-17 2016-03-11 瑞鼎科技股份有限公司 In-cell touch panel

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013246289A (en) * 2012-05-25 2013-12-09 Panasonic Liquid Crystal Display Co Ltd Liquid crystal display device
KR102024779B1 (en) * 2012-12-13 2019-09-24 엘지디스플레이 주식회사 Touch sensor integrated type display device
TWM459453U (en) * 2013-01-10 2013-08-11 Inv Element Inc In-cell touch display panel structure with metal sensing layer on lower substrate
TWM474964U (en) * 2013-10-23 2014-03-21 Superc Touch Corp Embedded touch display panel structure
TWM472204U (en) * 2013-08-07 2014-02-11 Superc Touch Corp Embedded display touch structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201243688A (en) * 2011-04-27 2012-11-01 Lg Display Co Ltd In-cell type touch panel
US20130176251A1 (en) * 2012-01-09 2013-07-11 Nvidia Corporation Touch-screen input/output device touch sensing techniques
TWM518787U (en) * 2014-10-17 2016-03-11 瑞鼎科技股份有限公司 In-cell touch panel
TW201627834A (en) * 2014-10-17 2016-08-01 瑞鼎科技股份有限公司 In-cell touch panel and trace layout thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI690917B (en) * 2019-03-13 2020-04-11 友達光電股份有限公司 Pixel array substrate

Also Published As

Publication number Publication date
CN106125996A (en) 2016-11-16
TW201640188A (en) 2016-11-16

Similar Documents

Publication Publication Date Title
TWI569182B (en) In-cell touch panel and trace layout thereof
TWI594156B (en) In-cell touch panel and trace layout thereof
TWI579754B (en) In-cell mutual-capacitive touch panel and trace layout thereof
US9619066B2 (en) Touch sensor integrated type display device
US10198130B2 (en) In-cell touch panel and display device
TWI545481B (en) In-cell touch display system, in-cell touch panel and trace layout thereof
US9626027B2 (en) Touch sensor integrated type display device
US9529482B2 (en) Capacitive in-cell touch screen and display device
TWI467298B (en) Liquid crystal display device
US9891745B2 (en) In-cell mutual-capacitive touch panel and trace layout thereof
US9665196B2 (en) Touch sensor-integrated type display device
WO2015135289A1 (en) Imbedded touchscreen and display device
TWI626579B (en) Display panel
TW201545017A (en) Touch sensor-integrated display device
KR101673206B1 (en) Self capacitor type in-cell touch liquid crystal display device
US20160328061A1 (en) In-cell touch panel
TWI610205B (en) In-cell touch panel
WO2016084728A1 (en) Position input device and display device fitted with position input function
TWI611323B (en) In-cell mutual-capacitive touch panel
TWI587036B (en) In-cell touch panel
WO2020010756A1 (en) Touch control display panel
KR102040654B1 (en) Touch sensor integrated type display device and method of fabricating the same
KR20160082810A (en) In Cell Touch Liquid Crystal Display Device
TWI611322B (en) In-cell touch panel

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees