TWI804326B - Pixel array substrate - Google Patents
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- TWI804326B TWI804326B TW111119045A TW111119045A TWI804326B TW I804326 B TWI804326 B TW I804326B TW 111119045 A TW111119045 A TW 111119045A TW 111119045 A TW111119045 A TW 111119045A TW I804326 B TWI804326 B TW I804326B
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本發明是有關於一種畫素陣列基板。The invention relates to a pixel array substrate.
顯示器的應用日益廣泛,舉凡家用的視聽娛樂、公共場合的訊息顯示看板、電競用的顯示器及可攜式電子產品都可見其蹤跡。近幾年來,顯示器大多兼具有觸控功能。顯示器的觸控種類大致上可分為外掛(out-cell)式、晶胞上(on-cell)式及內嵌式(In-cell touch)。內嵌式觸控(In-cell touch)技術具有易薄型化的優勢,因此在近幾年逐漸成為觸控顯示器的主流。然而,整合於顯示器中的資料線及/或閘極線和用以供間隙物站立的導電圖案易產生耦合效應,進而造成漏光問題。The applications of monitors are becoming more and more widespread, such as home audio-visual entertainment, information display boards in public places, monitors for e-sports and portable electronic products. In recent years, most of the displays also have a touch function. The touch types of displays can be roughly divided into out-cell touch, on-cell touch and in-cell touch. In-cell touch (In-cell touch) technology has the advantage of easy thinning, so it has gradually become the mainstream of touch displays in recent years. However, the data lines and/or gate lines integrated in the display and the conductive patterns for the spacers to stand are prone to coupling effects, thereby causing light leakage problems.
本發明提供一種畫素陣列基板,性能佳。The invention provides a pixel array substrate with good performance.
本發明一實施例的畫素陣列基板包括閘極線、資料線、主動元件、畫素電極、共用電極、觸控訊號線及導電圖案。資料線與閘極線交錯設置。主動元件具有第一端、第二端及控制端。主動元件的第一端電性連接至資料線,且主動元件的控制端電性連接至閘極線。畫素電極電性連接至主動元件的第二端。共用電極重疊於畫素電極。觸控訊號線電性連接於共用電極。導電圖案設置於觸控訊號線旁,電性隔離於觸控訊號線,且用以與間隙物重疊。資料線具有曲線段。在畫素陣列基板的俯視圖中,資料線的曲線段繞過導電圖案且與導電圖案隔開。A pixel array substrate according to an embodiment of the present invention includes gate lines, data lines, active components, pixel electrodes, common electrodes, touch signal lines and conductive patterns. The data lines and the gate lines are arranged alternately. The active element has a first terminal, a second terminal and a control terminal. The first end of the active element is electrically connected to the data line, and the control end of the active element is electrically connected to the gate line. The pixel electrode is electrically connected to the second terminal of the active device. The common electrode overlaps the pixel electrode. The touch signal line is electrically connected to the common electrode. The conductive pattern is disposed beside the touch signal line, electrically isolated from the touch signal line, and used to overlap with the spacer. The data lines have curved segments. In the top view of the pixel array substrate, the curved segment of the data line bypasses the conductive pattern and is separated from the conductive pattern.
本發明一實施例的畫素陣列基板包括閘極線、資料線、主動元件、畫素電極、共用電極、觸控訊號線及導電圖案。資料線與閘極線交錯設置。主動元件具有第一端、第二端及控制端。主動元件的第一端電性連接至資料線,且主動元件的控制端電性連接至閘極線。畫素電極電性連接至主動元件的第二端。共用電極重疊於畫素電極。觸控訊號線電性連接於共用電極。導電圖案設置於觸控訊號線旁,電性隔離於觸控訊號線,且用以與間隙物重疊。閘極線具有曲線段。在畫素陣列基板的俯視圖中,閘極線的曲線段繞過導電圖案且與導電圖案隔開。A pixel array substrate according to an embodiment of the present invention includes gate lines, data lines, active components, pixel electrodes, common electrodes, touch signal lines and conductive patterns. The data lines and the gate lines are arranged alternately. The active element has a first terminal, a second terminal and a control terminal. The first end of the active element is electrically connected to the data line, and the control end of the active element is electrically connected to the gate line. The pixel electrode is electrically connected to the second terminal of the active device. The common electrode overlaps the pixel electrode. The touch signal line is electrically connected to the common electrode. The conductive pattern is disposed beside the touch signal line, electrically isolated from the touch signal line, and used to overlap with the spacer. The gate lines have curved segments. In the top view of the pixel array substrate, the curved section of the gate line bypasses the conductive pattern and is separated from the conductive pattern.
本發明一實施例的畫素陣列基板包括閘極線、資料線、主動元件、畫素電極、共用電極、觸控訊號線及導電圖案。資料線與閘極線交錯設置。主動元件具有第一端、第二端及控制端。主動元件的第一端電性連接至資料線,且主動元件的控制端電性連接至閘極線。畫素電極電性連接至主動元件的第二端。共用電極重疊於畫素電極。觸控訊號線電性連接於共用電極。導電圖案設置於觸控訊號線旁,電性隔離於觸控訊號線,且用以與間隙物重疊。導電圖案具有多個主要部。在畫素陣列基板的俯視圖中,多個主要部位資料線與閘極線之至少一者的不同側。A pixel array substrate according to an embodiment of the present invention includes gate lines, data lines, active components, pixel electrodes, common electrodes, touch signal lines and conductive patterns. The data lines and the gate lines are arranged alternately. The active element has a first terminal, a second terminal and a control terminal. The first end of the active element is electrically connected to the data line, and the control end of the active element is electrically connected to the gate line. The pixel electrode is electrically connected to the second terminal of the active device. The common electrode overlaps the pixel electrode. The touch signal line is electrically connected to the common electrode. The conductive pattern is disposed beside the touch signal line, electrically isolated from the touch signal line, and used to overlap with the spacer. The conductive pattern has a plurality of main parts. In the plan view of the pixel array substrate, different sides of at least one of the data line and the gate line of the plurality of main parts.
本發明一實施例的畫素陣列基板包括閘極線、資料線、主動元件、畫素電極、共用電極、觸控訊號線及導電圖案。資料線與閘極線交錯設置。主動元件具有第一端、第二端及控制端。主動元件的第一端電性連接至資料線,且主動元件的控制端電性連接至閘極線。畫素電極電性連接至主動元件的第二端。共用電極重疊於畫素電極。觸控訊號線電性連接於共用電極。導電圖案設置於觸控訊號線旁,電性隔離於觸控訊號線,且用以與間隙物重疊。導電圖案電性連接至畫素電極。A pixel array substrate according to an embodiment of the present invention includes gate lines, data lines, active components, pixel electrodes, common electrodes, touch signal lines and conductive patterns. The data lines and the gate lines are arranged alternately. The active element has a first terminal, a second terminal and a control terminal. The first end of the active element is electrically connected to the data line, and the control end of the active element is electrically connected to the gate line. The pixel electrode is electrically connected to the second terminal of the active device. The common electrode overlaps the pixel electrode. The touch signal line is electrically connected to the common electrode. The conductive pattern is disposed beside the touch signal line, electrically isolated from the touch signal line, and used to overlap with the spacer. The conductive pattern is electrically connected to the pixel electrode.
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於附圖中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.
應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件“上”或“連接到”另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為“直接在另一元件上”或“直接連接到”另一元件時,不存在中間元件。如本文所使用的,“連接”可以指物理及/或電性連接。再者,“電性連接”或“耦合”可以是二元件間存在其它元件。It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that other elements exist between two elements.
本文使用的“約”、“近似”、或“實質上”包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,“約”可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的“約”、“近似”或“實質上”可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。As used herein, "about," "approximately," or "substantially" includes stated values and averages within acceptable deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the relative A specific amount of measurement-related error (ie, the limit of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, "about", "approximately" or "substantially" used herein can select a more acceptable deviation range or standard deviation according to optical properties, etching properties or other properties, and it is not necessary to use one standard deviation to apply to all properties .
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意義,除非本文中明確地這樣定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.
圖1為本發明一實施例之畫素陣列基板100的俯視示意圖。FIG. 1 is a schematic top view of a
圖2為本發明一實施例之顯示面板10的剖面示意圖。圖2對應圖1的剖線I-I’。圖1省略圖2的基底110。FIG. 2 is a schematic cross-sectional view of a
請參照圖1及圖2,畫素陣列基板100包括基底110。基底110用以承載畫素陣列基板100的其它元件。舉例而言,在本實施例中,基底110的材質可為玻璃、石英、有機聚合物、或是不透光/反射材料(例如:晶圓、陶瓷、或其它可適用的材料)、或是其它可適用的材料。Referring to FIG. 1 and FIG. 2 , the
畫素陣列基板100還包括閘極線122,設置於基底110上。畫素陣列基板100還包括資料線142,與閘極線122交錯設置。舉例而言,在本實施例中,閘極線122及資料線142可分別屬於不同的第一金屬層120及第二金屬層140,其中第一金屬層120與第二金屬層140之間設有第一絕緣層130,但本發明不以此為限。The
畫素陣列基板100還包括主動元件T,具有第一端Ta、第二端Tb及控制端Tc,其中主動元件T的第一端Ta電性連接至資料線142,且主動元件T的控制端Tc電性連接至閘極線122。舉例而言,在本實施例中,主動元件T可包括薄膜電晶體,第一端Ta、第二端Tb及控制端Tc可分別為薄膜電晶體的源極、汲極與閘極,薄膜電晶體還包括通道(未繪示),其中源極與汲極分別與通道的不同兩區電性連接。在本實施例中,薄膜電晶體的閘極例如是屬於第一金屬層120,薄膜電晶體的源極與汲極例如是屬於第二金屬層140,而第一絕緣層130例如是設置於通道與閘極之間的閘絕緣層,但本發明不以此為限。The
畫素陣列基板100還包括畫素電極192及共用電極172。畫素電極192電性連接至主動元件T的第二端Tb。共用電極172與畫素電極192相重疊。舉例而言,在本實施例中,畫素電極192具有多個狹縫192a,重疊於共用電極172。於顯示時間區間,共用電極172與畫素電極192之間的電位差可形成邊緣電場,以驅動顯示介質300(例如但不限於:液晶),進而顯示畫面。畫素陣列基板100還包括觸控訊號線162,電性連接於共用電極172。於觸控時間區間,共用電極172是做為觸控感測墊使用。The
在本實施例中,畫素陣列基板100還包括設置於第二金屬層140上的第二絕緣層150,第三金屬層160設置於第二絕緣層150上,而觸控訊號線162例如是屬於第三金屬層160;畫素陣列基板100還包括設置於第三金屬層160上的第三絕緣層182;畫素陣列基板100還包括設置於第三絕緣層182上的第一透明導電層170,而共用電極172例如是屬於第一透明導電層170;畫素陣列基板100還包括設置於第一透明導電層170上的第四絕緣層184;畫素陣列基板100還包括設置於第四絕緣層184上的第二透明導電層190,而畫素電極192例如是屬於第二透明導電層190;但本發明不以此為限。In this embodiment, the
舉例而言,在本實施例中,第一透明導電層170及第二透明導電層190的材質例如是銦錫氧化物、銦鋅氧化物、鋁錫氧化物、鋁鋅氧化物、銦鍺鋅氧化物、其它合適的氧化物、或者是上述至少二者的堆疊層,但本發明不以此為限。For example, in this embodiment, the materials of the first transparent
畫素陣列基板100還包括導電圖案164,設置於觸控訊號線162旁,電性隔離於觸控訊號線162,且用以與間隙物PS重疊。具體而言,在本實施例中,顯示面板10包括畫素陣列基板100、對向基板200及設置於畫素陣列基板100與對向基板200之間的顯示介質300;間隙物PS設置於對向基板200與畫素陣列基板100之間,以維持顯示面板10的晶胞間隙(cell gap),而導電圖案164是用以做為供間隙物PS站立的平台。The
舉例而言,在本實施例中,導電圖案164與觸控訊號線162同屬第三金屬層160,且導電圖案164與觸控訊號線162於結構上分離。此外,在本實施例中,導電圖案164例如是浮置的(floating),但本發明不以此為限。For example, in this embodiment, the
請參照圖1,值得注意的是,資料線142具有曲線段142a。在畫素陣列基板100的俯視圖中,資料線142的曲線段142a繞過導電圖案164且與導電圖案164隔開。舉例而言,在本實施例中,資料線142的曲線段142a可為一圓弧段,但本發明不以此為限。Referring to FIG. 1 , it is worth noting that the
在本實施例中,觸控訊號線162具有曲線段162a。在畫素陣列基板100的俯視圖中,觸控訊號線162的曲線段162a及資料線142的曲線段142a分別經由導電圖案164的相對兩側繞過導電圖案164。舉例而言,在本實施例中,觸控訊號線162的曲線段162a可為一圓弧段,但本發明不以此為限。In this embodiment, the
在本實施例中,資料線142還具有折線段142b,位於畫素電極192旁且與曲線段142a連接。觸控訊號線162還具有折線段162b,與曲線段162a連接。在畫素陣列基板100的俯視圖中,資料線142的折線段142b與觸控訊號線162的折線段162b可相重疊,但本發明不以此為限。In this embodiment, the
值得一提的,由於資料線142利用曲線段142a繞過供間隙物PS站立的導電圖案164,因此,導電圖案164與資料線142的耦合效應可降低。如此一來,因導電圖案164受資料線142影響造成顯示介質300(例如:液晶)轉動而產生的漏光問題可獲得改善。It is worth mentioning that since the
在此必須說明的是,下述實施例沿用前述實施例的元件標號與部分內容,其中採用相同的標號來表示相同或近似的元件,並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例,下述實施例不再重述。It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the aforementioned embodiments, and the following embodiments will not be repeated.
圖3為本發明另一實施例之畫素陣列基板100A的俯視示意圖。FIG. 3 is a schematic top view of a
圖3的畫素陣列基板100A與圖1的畫素陣列基板100類似,兩者的差異在於:兩者的閘極線122、122A不同。請參照圖3,具體而言,在本實施例中,閘極線122A具有曲線段122a。在畫素陣列基板100的俯視圖中,閘極線122A的曲線段122a繞過導電圖案164且與導電圖案164隔開。舉例而言,在本實施例中,閘極線122A的曲線段122a可為一圓弧段,但本發明不以此為限。The
由於閘極線122A利用曲線段122a繞過供間隙物PS站立的導電圖案164,因此,導電圖案164與閘極線122A的耦合效應可降低。如此一來,因導電圖案164受到閘極線122A影響而造成顯示介質300(可參考圖2)轉動而產生的漏光問題可獲得改善。Since the
在本實施例中,於畫素陣列基板100A的俯視圖中,閘極線122A的曲線段122a與資料線142的曲線段142a可選擇性地部分地重疊,但本發明不以此為限。在本實施例中,於畫素陣列基板100A的俯視圖中,閘極線122A的曲線段122a可選擇性地與觸控訊號線162的曲線段162a部分地重疊,但本發明不以此為限。In this embodiment, in the top view of the
圖4為本發明又一實施例之畫素陣列基板100B的俯視示意圖。圖4的畫素陣列基板100B與圖1的畫素陣列基板100類似,兩者的差異在於:兩者的資料線142、142B不同,且兩者的導電圖案164、164B不同。FIG. 4 is a schematic top view of a
請參照圖4,具體而言,在本實施例中,資料線142B可不具有曲線段142a。導電圖案164B可具有多個主要部164B-1、164B-2。在畫素陣列基板100B的俯視圖中,多個主要部164B-1、164B-2位資料線142B與閘極線122之至少一者的不同側。舉例而言,在本實施例中,導電圖案164B的多個主要部164B-1、164B-2包括第一主要部164B-1及第二主要部164B-2;在畫素陣列基板100B的俯視圖中,第一主要部164B-1及第二主要部164B-2分別位資料線142B的相對兩側。Please refer to FIG. 4 , specifically, in this embodiment, the
值得一提是,在本實施例中,透過將導電圖案164B分為位於資料線142B相對兩側的多個主要部164B-1、164B-2,可降低導電圖案164B與資料線142B的重疊面積及其耦合效應。如此一來,因導電圖案164B受資料線142B影響造成顯示介質300(可參考圖2)轉動而產生的漏光問題可獲得改善。It is worth mentioning that, in this embodiment, by dividing the
圖5為本發明再一實施例之畫素陣列基板100C的俯視示意圖。圖5的畫素陣列基板100C與圖1的畫素陣列基板100類似,兩者的差異在於:兩者的資料線142、142C不同,且兩者的導電圖案164、164C不同。FIG. 5 is a schematic top view of a
請參照圖5,具體而言,在本實施例中,資料線142C可不具有曲線段142a。導電圖案164C可具有多個主要部164C-1、164C-2、164C-3、164C-4。在畫素陣列基板100C的俯視圖中,多個主要部164C-1、164C-2、164C-3、164C-4位資料線142C與閘極線122之至少一者的不同側。Please refer to FIG. 5 , specifically, in this embodiment, the
舉例而言,在本實施例中,導電圖案164C的多個主要部164C-1、164C-2、164C-3、164C-4包括第一主要部164C-1、第二主要部164C-2、第三主要部164C-3及第四主要部164C-4;在畫素陣列基板100C的俯視圖中,第一主要部164C-1及第二主要部164C-2位資料線142C的相對兩側,且位於閘極線122的一側(例如:上側);在畫素陣列基板100C的俯視圖中,導電圖案164C的第一主要部164C-1及第三主要部164C-3位於資料線142C的一側(例如:右側)和閘極線122的相對兩側(例如:上下側);在畫素陣列基板100C的俯視圖中,第三主要部164C-3及第四主要部164C-4位資料線142C的相對兩側,且位於閘極線122的另一側(例如:下側)。For example, in this embodiment, the plurality of
圖6為本發明一實施例之畫素陣列基板100D的俯視示意圖。FIG. 6 is a schematic top view of a
圖6的畫素陣列基板100D與圖1的畫素陣列基板100類似,兩者的差異在於:兩者的資料線142、142D不同,且兩者的導電圖案164、164D不同。The
請參照圖6,具體而言,在本實施例中,資料線142D可不具有曲線段142a。導電圖案164D可電性連接至畫素電極192而非浮置。Please refer to FIG. 6 , specifically, in this embodiment, the
值得一提的是,在本實施例中,透過將導電圖案164D電性連接至畫素電極192,即使導電圖案164D與資料線142D/閘極線122耦合,導電圖案164D仍具有與畫素電極192相同的電位。藉此,可避免導電圖案164D對顯示介質300(可參考圖2)造成不良影響,進而改善漏光問題。It is worth mentioning that, in this embodiment, by electrically connecting the
圖7為本發明另一實施例之畫素陣列基板100E的俯視示意圖。圖7的畫素陣列基板100E與圖3的畫素陣列基板100A類似,兩者的差異在於:在圖7的實施例中,導電圖案164E電性連接至畫素電極192。FIG. 7 is a schematic top view of a
圖8為本發明又一實施例之畫素陣列基板100F的俯視示意圖。圖8的畫素陣列基板100F與圖5的畫素陣列基板100C類似,兩者的差異在於:在圖8的實施例中,導電圖案164F電性連接至畫素電極192。FIG. 8 is a schematic top view of a
10:顯示面板
100、100A、100B、100C、100D、100E、100F:畫素陣列基板
110:基底
120:第一金屬層
122、122A:閘極線
122a、142a、162a:曲線段
130:第一絕緣層
140:第二金屬層
142、142B、142C、142D:資料線
142b、162b:折線段
150:第二絕緣層
160:第三金屬層
162:觸控訊號線
164、164B、164D、164E、164F:導電圖案
164B-1、164B-2、164C-1、164C-2、164C-3、164C-4:主要部
170:第一透明導電層
172:共用電極
182:第三絕緣層
184:第四絕緣層
190:第二透明導電層
192:畫素電極
192a:狹縫
200:對向基板
300:顯示介質
T:主動元件
Ta:第一端
Tb:第二端
Tc:控制端
PS:間隙物
I-I’:剖線
10:
圖1為本發明一實施例之畫素陣列基板100的俯視示意圖。
圖2為本發明一實施例之顯示面板10的剖面示意圖。
圖3為本發明另一實施例之畫素陣列基板100A的俯視示意圖。
圖4為本發明又一實施例之畫素陣列基板100B的俯視示意圖。
圖5為本發明再一實施例之畫素陣列基板100C的俯視示意圖。
圖6為本發明一實施例之畫素陣列基板100D的俯視示意圖。
圖7為本發明另一實施例之畫素陣列基板100E的俯視示意圖。
圖8為本發明又一實施例之畫素陣列基板100F的俯視示意圖。
FIG. 1 is a schematic top view of a
100:畫素陣列基板 100:Pixel array substrate
122:閘極線 122: Gate line
142:資料線 142: data line
142a、162a:曲線段 142a, 162a: curve segment
142b、162b:折線段 142b, 162b: polyline segment
162:觸控訊號線 162: Touch signal line
164:導電圖案 164: conductive pattern
170:第一透明導電層 170: the first transparent conductive layer
172:共用電極 172: common electrode
190:第二透明導電層 190: the second transparent conductive layer
192:畫素電極 192: pixel electrode
192a:狹縫 192a: Slit
T:主動元件 T: active component
Ta:第一端 Ta: the first end
Tb:第二端 Tb: the second end
Tc:控制端 Tc: control terminal
I-I’:剖線 I-I': section line
Claims (13)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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TW111119045A TWI804326B (en) | 2022-05-23 | 2022-05-23 | Pixel array substrate |
CN202211301431.2A CN115662995A (en) | 2022-05-23 | 2022-10-24 | Pixel array substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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TW111119045A TWI804326B (en) | 2022-05-23 | 2022-05-23 | Pixel array substrate |
Publications (2)
Publication Number | Publication Date |
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TWI804326B true TWI804326B (en) | 2023-06-01 |
TW202347102A TW202347102A (en) | 2023-12-01 |
Family
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TW111119045A TWI804326B (en) | 2022-05-23 | 2022-05-23 | Pixel array substrate |
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CN (1) | CN115662995A (en) |
TW (1) | TWI804326B (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201044052A (en) * | 2009-06-06 | 2010-12-16 | Au Optronics Corp | Touch panel |
US20170192279A1 (en) * | 2016-01-05 | 2017-07-06 | Japan Display Inc. | Display device |
CN109782500A (en) * | 2017-11-10 | 2019-05-21 | 中华映管股份有限公司 | Embedded touch liquid crystal display device |
-
2022
- 2022-05-23 TW TW111119045A patent/TWI804326B/en active
- 2022-10-24 CN CN202211301431.2A patent/CN115662995A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201044052A (en) * | 2009-06-06 | 2010-12-16 | Au Optronics Corp | Touch panel |
US20170192279A1 (en) * | 2016-01-05 | 2017-07-06 | Japan Display Inc. | Display device |
CN109782500A (en) * | 2017-11-10 | 2019-05-21 | 中华映管股份有限公司 | Embedded touch liquid crystal display device |
Also Published As
Publication number | Publication date |
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TW202347102A (en) | 2023-12-01 |
CN115662995A (en) | 2023-01-31 |
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