TWI724927B - Display panel and pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of active components, a plurality of pixel electrodes, at least one common electrode, and at least one touch signal line. The scan lines, the data lines, the touch signal lines, and the common electrodes are all disposed on the substrate. The data lines and the touch signal lines cross the scan lines to define a plurality of sub-pixel areas. The touch signal line is electrically connected to at least the common electrode. The active components are electrically connected to the scan lines and the data lines. The pixel electrodes overlap the common electrode. Each pixel electrode is distributed in two adjacent sub-pixel areas across one of the scan lines. Each pixel electrode is electrically connected to one of the active components.

Description

Display panel and its pixel array substrate

The present invention relates to a display, and particularly relates to a display panel and a pixel array substrate thereof.

The existing in-cell touch display panel usually has at least one touch signal line. Generally speaking, the touch signal line is arranged between two adjacent rows of pixel electrodes, so the touch signal line will be adjacent to one of the data lines. That is to say, in the same accommodating area between two adjacent rows of pixel electrodes, not only data lines will be provided, but also touch signal lines will be provided. Therefore, the touch signal line and the data line are arranged together in the same accommodating area, which causes the in-cell touch display panel to have a low transmittance (equivalent to the aperture ratio).

At least one embodiment of the present invention provides a pixel array substrate to improve the transmittance of the existing in-cell touch display panel.

Another embodiment of the present invention provides a display panel having the above-mentioned pixel array substrate.

The pixel array substrate provided by at least one embodiment of the present invention includes a substrate, multiple scan lines, multiple data lines, multiple active devices, multiple pixel electrodes, at least one common electrode, and at least one touch signal line. These scan lines, these data lines, touch signal lines and common electrodes are all arranged on the substrate. The scan line extends in the first direction, and the data line and the touch signal line extend in the second direction. The scan lines, the data lines and the touch signal lines are interlaced to define a plurality of sub-pixel areas. The touch signal line is electrically connected to at least the common electrode. These active components are electrically connected to the scan lines and the data lines. These pixel electrodes overlap the common electrode. Each pixel electrode is distributed in two adjacent sub-pixel regions across one of the scan lines along the second direction. Each pixel electrode is electrically connected to one of these active devices.

In at least one embodiment of the present invention, each pixel electrode includes a main body portion and an extension portion. The main body part is connected to the extension part, and the extension parts of two adjacent pixel electrodes are located in the same sub-pixel area.

In at least one embodiment of the present invention, the main body portions of the pixel electrodes respectively correspond to a plurality of color resists.

In at least one embodiment of the present invention, the extensions of two adjacent pixel electrodes located in the same sub-pixel area correspond to the colorless resistance area.

In at least one embodiment of the present invention, in a 3×3 matrix formed by rows of adjacent sub-pixel regions, the same scan line controls the main body portions in two of the sub-pixel regions.

In at least one embodiment of the present invention, there is an accommodating area between two adjacent rows of pixel electrodes, and each data line and each touch signal line are respectively arranged in the accommodating area, but the data line and the touch The control signal lines are not arranged in the same accommodating area.

A display panel provided by at least one other embodiment of the present invention includes the above-mentioned pixel array substrate, an opposite substrate, and a display medium. The opposite substrate is arranged on the opposite side of the pixel array substrate, and the display medium is arranged between the opposite substrate and the pixel array substrate.

In at least one embodiment of the present invention, the above-mentioned opposite substrate includes a carrier plate, a black matrix, and a plurality of color resists. The black matrix has a plurality of pixel openings and is arranged on the carrying plate. The color resists are arranged on the carrier board and are respectively arranged in some of the pixel openings, wherein the main body of the pixel electrodes respectively correspond to the color resists.

In at least one embodiment of the present invention, the extensions of two adjacent pixel electrodes located in the same sub-pixel area correspond to pixel openings that are not provided with any color resistance.

Since each pixel electrode crosses one of the scan lines along the second direction and is distributed in two adjacent sub-pixel regions, and each pixel electrode is electrically connected to one of the active devices, one active device can control more than one The sub-pixel area (for example, 1.5 sub-pixel area). In this way, the pixel array substrate can use a smaller number of data lines to control these pixel electrodes, so that the touch signal line and the data line do not need to be arranged in the same accommodating area between two adjacent rows of pixel electrodes. In turn, the penetration rate of the display panel is improved.

In order to make the features and advantages of the present invention more comprehensible, the following specific examples are cited in conjunction with the accompanying drawings, which are described in detail as follows.

In the following text, in order to clearly present the technical features of the case, the dimensions (such as length, width, thickness, and depth) of the elements (such as layers, films, substrates, and regions) in the drawings will be enlarged in unequal proportions. . Therefore, the description and explanation of the following embodiments are not limited to the size and shape presented by the elements in the drawings, but should cover the size, shape, and deviation of the two caused by actual manufacturing processes and/or tolerances. For example, the flat surface shown in the drawing may have rough and/or non-linear characteristics, and the acute angle shown in the drawing may be round. Therefore, the elements shown in the drawings of this case are mainly used for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of patent applications in this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated value and range of values, but also cover the understanding of those with ordinary knowledge in the technical field of the invention. The allowable deviation range of, wherein the deviation range can be determined by the error generated during the measurement, and this error is caused by the limitation of the measurement system or the process conditions, for example. In addition, "about" may mean within one or more standard deviations of the aforementioned value, for example within ±30%, ±20%, ±10%, or ±5%. The terms "about", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties, or other properties. The standard deviation applies to all the above optical properties, etching properties, mechanical properties, and other properties.

FIG. 1A is a schematic circuit diagram of a pixel array substrate according to at least one embodiment of the invention. Referring to FIG. 1A, the pixel array substrate 100 includes a plurality of scan lines 111, a plurality of data lines 112, and at least one touch signal line 113. FIG. 1A shows two touch signal lines 113 as an example. The scan lines 111 extend along the first direction D1, and the data lines 112 and the touch signal lines 113 extend along the second direction D2. The first direction D1 and the second direction D2 may be substantially perpendicular.

Taking FIG. 1A as an example, the first direction D1 may be a horizontal direction, and the second direction D2 may be a vertical direction. Therefore, in FIG. 1A, the scan line 111 runs horizontally, and the data line 112 is perpendicular to the touch signal line 113 Towards. In addition, in other embodiments, the first direction D1 may be a vertical direction, and the second direction D2 may be a horizontal direction. Therefore, the directions of the scan lines 111, the data lines 112, and the touch signal lines 113 are not shown in FIG. 1A. limit.

The scan lines 111, the data lines 112, and the touch signal lines 113 are interlaced to define a plurality of sub-pixel regions P10, P11, P12, and P13. The sub-pixel regions P10, P11, P12, and P13 can be arranged in a matrix. For example, the multiple sub-pixel regions P10, P11, P12, and P13 shown in FIG. 1A can be arranged in a 3×3 matrix, which can be formed by arranging two data lines 112, four scan lines 111, and two touch signal lines 113.

In other embodiments, the pixel array substrate 100 may include more than two data lines 112, one or more than two touch signal lines 113, and more than four scan lines 111, so the sub-pixel regions P10, The number of P11, P12, and P13, the number of data lines 112, the number of touch signal lines 113, and the number of scan lines 111 are for illustration only, and are not intended to limit the present invention.

The sub-pixel regions P10, P11, P12, and P13 arranged in a 3×3 matrix in FIG. 1A can be regularly and repeatedly arranged. In other words, the 3×3 matrix formed by the sub-pixel regions P10, P11, P12, and P13 in FIG. 1A can be regarded as a repeating unit. This repeating unit can be replicated in multiples, and these repeating units are arranged in a larger matrix, so that a larger number of sub-pixel regions P10, P11, P12, and P13 can be arranged in a larger matrix exceeding 3×3.

The pixel array substrate 100 further includes a plurality of pixel electrodes 120, and each pixel electrode 120 crosses one of the scan lines 111 along the second direction D2 and is distributed in the sub-pixel regions P10, P11, P12, and P13 Two of them are adjacent to each other. Taking FIG. 1A as an example, one of the pixel electrodes 120 extends from the sub-pixel area P12 above the middle along the second direction D2 to the middle sub-pixel area P10 across a scan line 111. The other pixel electrode 120 extends from the secondary pixel region P10 in the middle along the second direction D2 to the secondary pixel region P12 below the middle across the other scan line 111.

FIG. 1B is a schematic diagram of a circuit of a common electrode and a touch signal line of the pixel array substrate in FIG. 1A. Referring to FIGS. 1A and 1B, the pixel array substrate 100 further includes at least one common electrode 140. Taking FIG. 1B as an example, the pixel array substrate 100 includes a plurality of common electrodes 140 and a plurality of touch signal lines 113, wherein the common electrodes 140 may be arranged in a matrix, as shown in FIG. 1B. In addition, the numbers of the common electrode 140 and the touch signal line 113 shown in FIG. 1B are for illustration only, and do not limit the present invention.

The touch signal lines 113 are electrically connected to the common electrodes 140, respectively. The touch signal lines 113 shown in FIG. 1B may be electrically connected to the common electrodes 140 one-to-one. The size (equivalent to the area) of each common electrode 140 is much larger than the size of any one of the sub-pixel regions P10, P11, P12, and P13. A plurality of pixel electrodes 120 can overlap with at least one common electrode 140, and each common electrode 140 can overlap each other. The electrodes 140 are distributed in some of these sub-pixel regions P10, P11, P12, and P13.

For example, a single common electrode 140 can cover 900 main pixel regions PM1 arranged in a 30×30 matrix, and the touch signal line 113 is distributed in a plurality of sub pixel regions P10, P11, P12, and P13. One main pixel area PM1 may include multiple sub-pixel areas. For example, each main pixel area PM1 may include at least three of the sub-pixel areas P10, P11, P12, and P13. Therefore, a single common electrode 140 can cover at least 2700 sub-pixel regions, including the sub-pixel regions P10, P11, P12, and P13. It can be seen from this that a plurality of (for example, more than 2700) pixel electrodes 120 may be arranged to overlap one common electrode 140.

It should be noted that FIG. 1B simplifies the shape of the common electrode 140, and draws the shape of each common electrode 140 as a square. In actual situations, the common electrode 140 has at least one opening due to considerations such as reducing parasitic capacitance and avoiding a short circuit with the pixel electrode 120, so the shape of the common electrode 140 will not be a square as shown in FIG. 1B.

FIG. 1C is a schematic top view of a counter substrate suitable for combining with the pixel array substrate in FIG. 1A. 1C, the opposite substrate 200 can be combined with the pixel array substrate 100, and the opposite substrate 200 can be a color filter substrate, and the pixel array substrate 100 and the opposite substrate 200 can be used to make a display panel. In addition, the counter substrate 200 includes a black matrix 210 and a plurality of color resists 22R, 22G, and 22B.

The shape of the black matrix 210 can be a mesh shape and has a plurality of pixel openings PH0, PH1, PH2, and PH3, and these color resists 22R, 22G, and 22B are respectively disposed in the pixel openings PH1, PH2, and PH3, but Not set in the pixel opening PH0. In other words, all the color resists 22R, 22G, and 22B are respectively arranged in some of these pixel openings, that is, in the pixel openings PH1, PH2, and PH3, but no color resists are set in the other pixel openings PH0. 22R, 22G and 22B. Therefore, the pixel opening PH0 is a colorless area of the opposite substrate 200.

The color resists 22R, 22G, and 22B are all filter layers, and the material of the filter layer can be colored photoresist or resin. These color resists 22R have the same color. Similarly, the color resists 22G have the same color, and the color resists 22B have the same color, but the color resists 22R, 22G, and 22B have different colors from each other. For example, the color resists 22R can all be red filter layers, the color resists 22G can all be green filter layers, and the color resists 22B can all be blue filter layers.

In particular, in the embodiment shown in FIG. 1C, the color resists of the same color may be arranged in the same row along the second direction D2 (for example, the vertical direction). Taking FIG. 1C as an example, the color resists 22R, 22G, and 22B are respectively arranged in three rows along the second direction D2, wherein a plurality of color resists 22R are arranged in a row on the left, and a plurality of color resists 22G are arranged in a row in the middle. The multiple color resists 22B are arranged in a row on the right. However, in other embodiments, the color resists of different colors can also be arranged in the same row along the second direction D2. For example, the color resists 22R, 22G, and 22B may be arranged in the same row along the second direction D2. Therefore, the arrangement of the color resists 22R, 22G, and 22B shown in FIG. 1C is only an example and does not limit the present invention.

1A and 1C, after the pixel array substrate 100 and the counter substrate 200 are combined, the counter substrate 200 is disposed on the opposite side of the pixel array substrate 100, and the pixel electrodes 120 correspond to the color resists 22R , 22G and 22B. Specifically, each pixel electrode 120 includes a main portion 121 and an extension portion 122, wherein the main portion 121 is connected to the extension portion 122, and the extension portions 122 of two adjacent pixel electrodes 120 are located in the same sub-pixel area P10 . The extension 122 is only arranged in the sub-pixel area P10, but not in the sub-pixel areas P11, P12, and P13. On the contrary, these main body parts 121 are respectively arranged in the sub-pixel areas P11, P12, and P13, but are not arranged in the sub-pixel area P10.

The main body 121 of the pixel electrode 120 corresponds to the color resists 22R, 22G, and 22B, respectively. In other words, each main body 121 is aligned with one of these color resists 22R, 22G, and 22B. For example, the main body 121 located in the upper middle of FIG. 1A is aligned with the color resist 22G in the pixel opening PH2 located in the upper middle of FIG. 1C. Similarly, the main body 121 in the middle right in FIG. 1A will be aligned with the color resist 22B in the pixel opening PH3 in the middle right in FIG. 1C, while the main body 121 in the middle left in FIG. The color resist 22R in the pixel opening PH1 on the left in the center of the quasi-figure 1C.

The extensions 122 of the pixel electrodes 120 respectively correspond to the pixel openings PH0, and in this embodiment, the extensions 122 located in the same sub-pixel area P10 correspond to the absence of any color resists 22R, One pixel opening PH0 of 22G and 22B (that is, no color blocking area). For example, the two extensions 122 at the upper left in FIG. 1A are aligned with the pixel opening PH0 at the upper left in FIG. 1C. Similarly, the two extensions 122 in the middle of FIG. 1A are aligned with the pixel opening PH0 in the middle of FIG. 1C, and the two extensions 122 at the bottom right in FIG. 1A are aligned with the pixel openings in FIG. 1C. The pixel on the bottom right opens PH0.

In the 3×3 matrix of multiple sub-pixel regions P10, P11, P12, and P13 shown in FIG. 1A, these sub-pixel regions P10 with extensions 122 can be located in this 3×3 matrix. Diagonal position. Taking FIG. 1A as an example, these sub-pixel areas P10 can be located in the upper left, middle, and lower right positions in the 3×3 matrix. Similarly, in the black matrix 210 shown in FIG. 1C, these pixel openings PH0, PH1, PH2, and PH3 can also be arranged to form a 3×3 matrix without any color resists 22R, 22G, and 22B. The pixel opening PH0 can be located at the diagonal position of the 3×3 matrix, for example, at the top left, middle, and bottom right positions, so that the sub-pixel regions P10 can respectively correspond to the pixel openings PH0.

1A, the pixel array substrate 100 further includes a plurality of active elements 130, where the active elements 130 may be transistors, and for example, a field-effect transistor (Field-Effect Transistor, FET) as shown in FIG. 1A, so Each active device 130 may have a gate G13, a source S13, and a drain D13. The active device 130 is electrically connected to the scan lines 111, the data line 112 and the pixel electrode 120, and each pixel electrode 120 is electrically connected to one of the active devices 130.

Taking FIG. 1A as an example, in each active device 130, the gate G13 of the active device 130 is electrically connected to the scan line 111, the source electrode S13 is electrically connected to the data line 112, and the drain electrode D13 is electrically connected to the pixel electrode 120. In this way, the scan line 111 and the data line 112 can control the corresponding pixel electrode 120 through the active device 130 to promote the formation of an image.

In the embodiment shown in FIG. 1A, the active device 130 is electrically connected to the pixel electrode 120 from the main body 121, instead of being electrically connected to the pixel electrode 120 from the extension portion 122. Since each pixel electrode 120 is distributed across the scan line 111 in the sub-pixel area P10 and the adjacent sub-pixel areas P11, P12, or P13, and two adjacent extensions 122 are provided in the sub-pixel area P10, However, no main body 121 is provided.

In the top row of sub-pixel regions P10, P12, and P13 in FIG. 1A along the first direction D1, the top scan line 111 is electrically connected to those located in the sub-pixel regions P12 and P13 via the active device 130. The two main bodies 121 are not electrically connected to the extension 122 located in the upper left sub-pixel area P10, so that the uppermost scan line 111 in FIG. 1A can control the uppermost sub-pixel area P12 in FIG. 1A and The main body 121 in P13 does not control the extension 122 in the upper left sub-pixel area P10.

Similarly, the second scan line 111 from the top controls the main body 121 in the middle row of sub-pixel areas P11 and P13 in FIG. 1A, but does not control any extensions in the middle sub-pixel area P10. 122. The third scan line 111 from the top (that is, the penultimate scan line 111) controls the main body 121 in the sub-pixel regions P11 and P12 in the lower column of FIG. 1A, but does not control the sub-pictures located in the lower right. Any extension 122 in the prime area P10. It can be seen that in the 3×3 matrix of the adjacent sub-pixel regions P10, P11, P12, and P13 (as shown in FIG. 1A), the same scan line 111 can control the position in these sub-pixel regions. These main body portions 121 in two of the pixel regions P11, P12, and P13.

In the sub-pixel area P10 located at the upper left, the lower extension 122 is connected to the main body 121 in the sub-pixel area P11 located at the middle left, and the second scan line 111 from the top is electrically connected to the middle. The main body 121 in the sub-pixel area P11 on the left. Therefore, the lower extension 122 located in the upper left sub-pixel area P10 is controlled by the second scan line 111 counted from the upper side. In the sub-pixel area P10 located at the upper left, the upper extension 122 is controlled by the scan line 111 of the uppermost scan line 111 in FIG. 1A. Therefore, the two extension portions 122 in the sub-pixel area P10 located at the upper left are respectively controlled by two different scan lines 111.

Similarly, in the sub-pixel region P10 located in the middle, the upper extension 122 is electrically connected to the uppermost scan line 111 in FIG. 1A, and the lower extension 122 is electrically connected to the third scan line from the top. 111. In the sub-pixel area P10 located at the lower right, the upper extension 122 is electrically connected to the second scan line 111 counted from the top, and the lower extension 122 is electrically connected to the bottom scan line 111. It can be seen that the two extension portions 122 in each sub-pixel region P10 are controlled by two different scan lines 111 respectively.

Although the two extensions 122 in each sub-pixel area P10 are controlled by two different scan lines 111, and the two scan lines 111 directly control the other sub-pixel areas P10 (that is, the sub-pixel areas P11, P12 and P13 are two of the main body 121, but the extension 122 corresponds to the pixel opening PH0 (that is, the colorless area) without any color resists 22R, 22G, and 22B. Therefore, the sub-pixel area P10 can be used as a colorless pixel, such as a white pixel, but not as a colored pixel of the display panel, such as a red, green, or blue pixel. Therefore, these extensions 122 will not substantially damage the overall color performance of the display panel.

In the embodiment shown in FIG. 1A, there is a accommodating area R1 between the pixel electrodes 120 arranged in two adjacent rows, and the same data line 112 is arranged between the pixel electrodes 120 in two adjacent rows. The accommodating area R1 can be electrically connected to the two rows of pixel electrodes 120. Therefore, two adjacent rows of pixel electrodes 120 can be controlled by the same data line 112.

Since each pixel electrode 120 crosses one of the scan lines 111 along the second direction D2 and is distributed in the sub-pixel area P10 and the adjacent sub-pixel area P11, P12, or P13, and each pixel electrode 120 is electrically conductive One active element 130 is connected, so one active element 130 can control more than one sub-pixel area, such as 1.5 sub-pixel areas, that is, one of the sub-pixel areas P11, P12, and P13 and the adjacent half of the sub-pixel area Pixel area P10. In this way, the pixel array substrate 100 can use a smaller number of data lines 112 to control the pixel electrodes 120, thereby reducing the number of output ports of source driving elements. The source driving elements are, for example, integrated circuits. , IC).

Taking Figure 1A as an example, in the 3×3 matrix of sub-pixel regions P10, P11, P12, and P13 shown in Figure 1A, the total number of these sub-pixel regions P10, P11, P12 is 9 And P13 are controlled by 6 active components 130, and the pixel electrodes 120 in the sub-pixel regions P10, P11, P12, and P13 arranged in three adjacent rows along the second direction D2 can use two data lines 112 to control.

It can be seen that, on average, one active device 130 can control 1.5 sub-pixels, and on average one data line 112 can control 1.5 rows of pixel electrodes 120, so the number of data lines 112 is less than the number of rows of these pixel electrodes 120. However, the data lines 112 can still control the pixel electrodes 120, and all the data lines 112 do not need to be arranged in all the accommodating regions R1, that is, there is no need to provide any data lines 112 in some accommodating regions R1.

The same touch signal line 113 can also be separately arranged in the accommodating area R1 between two adjacent rows of pixel electrodes 120. In detail, since some data lines 112 are not provided in the accommodating area R1, although the data lines 112 and the touch signal lines 113 are respectively arranged in the accommodating area R1, the data lines 112 and the touch The signal line 113 is not arranged in the same accommodating area R1. Compared with the existing in-cell touch display panel, the pixel array substrate 100 can achieve a higher transmittance (aperture ratio), thereby enhancing the brightness of the display panel. In addition, in the embodiment shown in FIG. 1A, two data lines 112 may be provided between two adjacent touch signal lines 113.

2 is a schematic diagram of partial wiring of the pixel array substrate in FIG. 1A, and FIG. 3A is a schematic cross-sectional view of a display panel according to at least one embodiment of the present invention, wherein FIG. 2 shows the pixel array substrate 100 in FIG. 1A The wiring in the area A2, and the pixel array substrate 100 shown in FIG. 3A is drawn along the line 3A-3A section in FIG. 2.

2 and 3A, the display panel 10 includes a pixel array substrate 100, an opposite substrate 200, and a display medium 300. The counter substrate 200 is disposed on the opposite side of the pixel array substrate 100, and the display medium 300 is disposed between the counter substrate 200 and the pixel array substrate 100. The display medium 300 may be a liquid crystal material, and the display panel 10 may be a liquid crystal display panel, which is, for example, a Fringe Field Switching (FFS) liquid crystal display panel, but the display panel 10 is not limited to being a Fringe Field Switching type. Liquid crystal display panel.

The pixel array substrate 100 includes a substrate 150, which is a transparent substrate such as a glass plate, and these scan lines 111, data lines 112, touch signal lines 113, common electrodes 140, pixel electrodes 120, and active components 130 are all disposed on the substrate 150 on. The pixel array substrate 100 may further include insulating layers 160, 161, 162, and 163 and a channel layer C13, where the channel layer C13 may be a semiconductor layer.

The gate G13 of the active device 130 is formed on the substrate 150, and the insulating layer 160 covers the gate G13. The gate electrode G13 and the scan line 111 may be formed by etching the same film layer, and the film layer is, for example, a metal layer. Therefore, both the gate electrode G13 and the scan line 111 can be formed on the same surface of the substrate 150. The channel layer C13, the source electrode S13 and the drain electrode D13 are all located on the insulating layer 160, and the insulating layer 161 covers the channel layer C13, the source electrode S13 and the drain electrode D13.

The insulating layer 162 is formed on the insulating layer 161, and the insulating layer 163 and the common electrode 140 are formed on the insulating layer 162, and the insulating layer 163 covers the common electrode 140. The pixel electrode 120 is formed on the insulating layer 163, and the pixel electrode 120 and the common electrode 140 are overlapped. In addition, both the main body 121 and the extension 122 of the pixel electrode 120 may have a plurality of parallel slits 124, as shown in FIG. 2 and FIG. 3A.

The insulating layers 161, 162, and 163 have a plurality of contact holes V1. Each contact hole V1 can be formed through the insulating layers 161, 162, and 163. That is, the contact hole V1 can be formed from the top surface of the insulating layer 163 through the insulating layer 162. Extend to the bottom surface of the insulating layer 161. The contact holes V1 correspond to the drain electrodes D13 respectively, so that a part of the drain electrodes D13 under the contact hole V1 is not covered by the insulating layers 161, 162, and 163. In this way, the main body 121 of the pixel electrode 120 can extend from the insulating layer 163 to the drain D13 under the contact hole V1, so that the main body 121 is electrically connected to the drain D13 through the contact hole V1, so that the active device 130 can be electrically connected. The pixel electrode 120 is connected.

In addition, the insulating layers 161 and 162 have a plurality of contact holes V2. Each contact hole V2 may be formed through the insulating layers 161 and 162, that is, the contact hole V2 may extend from the top surface of the insulating layer 162 to the bottom surface of the insulating layer 161. From FIG. 3A, the depth of the contact hole V2 is significantly smaller than the depth of the contact hole V1. The contact holes V2 correspond to the touch signal lines 113 respectively, so that part of the touch signal lines 113 under the contact holes V2 are not covered by the insulating layers 161 and 162. In this way, the common electrode 140 can extend from the insulating layer 162 to the touch signal line 113 under the contact hole V2, so that the common electrode 140 can be electrically connected to the touch signal line 113 through the contact hole V2. In addition, the contact hole V2 may be filled with the insulating layer 163, as shown in FIG. 3A.

In the embodiment shown in FIG. 2, each pixel electrode 120 may further include a connecting portion 123, and in the same pixel electrode 120, the connecting portion 123 is located between the main body 121 and the extension 122 and is connected to the main body. 121 and extension 122. Therefore, the main body 121 can be connected to the extension portion 122 via the connection portion 123, wherein each extension portion 122 can be disposed above one of the scan lines 111, as shown in FIG. 2.

It should be noted that the connecting portion 123 shown in FIG. 2 is only one of various embodiments of the present invention. In other embodiments, the main body 121 may be connected to the extension portion 122 by using other connecting portions other than those in FIG. 2. Alternatively, the main body 121 can also be directly connected to the extension portion 122 without the connecting portion 123 being used. Therefore, the connection portion 123 shown in FIG. 2 is for illustration only, and does not limit the connection manner between the main body 121 and the extension portion 122.

The opposite substrate 200 includes a carrier plate 250. The black matrix 210 and the color resists 22R, 22G, and 22B are all disposed on the carrier board 250, and the color resists 22R, 22G, and 22B are respectively located in the pixel openings PH1, PH2, and PH3 of the black matrix 210, wherein the black matrix 210 The active device 130, the scan line 111, and the touch signal line 113 can be covered, and the color resists 22R, 22G, and 22B correspond to the main body 121 of the pixel electrode 120. For example, in FIG. 3A, the color resist 22B is located in the pixel opening PH3, and the main body 121 is aligned with the color resist 22B in the pixel opening PH3.

3B is another schematic cross-sectional view of the display panel 10, in which the pixel array substrate 100 shown in FIG. 3B is drawn along the line 3B-3B in FIG. 2. 2 and 3B, the black matrix 210 further covers the data lines 112, and the data lines 112 are all located on the insulating layer 160. The source electrode S13, the drain electrode D13 (see FIG. 3A) and the data line 112 can be formed by etching the same film layer, where the film layer is, for example, a metal layer.

The pixel opening PH0 without any color resists 22R, 22G, and 22B corresponds to the extension 122 of the pixel electrode 120. Taking FIG. 3B as an example, the extension 122 is aligned with the pixel opening PH0. In the embodiment shown in FIG. 3B, the pixel opening PH0 may not be filled with any film, as shown in FIG. 3B. However, in other embodiments, the pixel opening PH0 may be filled with a transparent layer, and the transparent layer may be formed of a transparent photoresist or a resin. Therefore, the pixel opening PH0 is not limited to FIG. 3B.

Referring to FIGS. 3A and 3B, the display panel 10 is an example of a boundary electric field switching type liquid crystal display panel. The common electrode 140 can output a common voltage, and the data line 112 can output the pixel voltage to the corresponding pixel electrode 120 through the active device 130. The common voltage is usually different from the pixel voltage, so the pixel electrode 120 and the common electrode 140 Can generate electric field. Since the main body 121 and the extension 122 of the pixel electrode 120 have a plurality of parallel slits 124, an electric field with a horizontal component can be generated between the pixel electrode 120 and the common electrode 140. When the display medium 300 is a liquid crystal material, the aforementioned electric field with a horizontal component can drive the liquid crystal molecules in the liquid crystal material (display medium 300) to deflect, so that the display panel 10 can display images.

In addition, the common electrode 140 may also have a touch sensing function. In detail, when the display panel 10 is operating, the data lines 112 temporarily suspend outputting pixel voltages, and the common electrodes 140 also temporarily suspend outputting common voltages, so that the common electrodes 140 can perform touch sensing. When an object (such as a finger or a stylus) touches the display surface 251 of the display panel 10, the common electrodes 140 for touch sensing can detect the position and movement of the object. In this way, the user can use objects to touch and operate the display panel 10.

Referring to FIGS. 2 and 3A, the common electrode 140 may have a plurality of openings 141 (one is shown in FIG. 2 as an example), and the opening 141 corresponds to the touch signal line 113. In detail, the opening 141 is formed directly above the touch signal line 113 and extends along the touch signal line 113, so the shape of the opening 141 is a bar shape and corresponds to the shape of the touch signal line 113. These openings 141 can reduce the overlap area between the common electrode 140 and the touch signal line 113, so as to reduce the parasitic capacitance between the common electrode 140 and the touch signal line 113, thereby improving the touch sensing function of the common electrode 140.

The common electrode 140 may further have a plurality of openings 142, and the openings 142 respectively correspond to the contact holes V1. Specifically, the contact hole V1 is located in the opening 142, wherein the sidewall of the opening 142 surrounds the contact hole V1, that is, the hole diameter of the opening 142 is larger than the hole diameter of the contact hole V1. Therefore, the common electrode 140 does not contact the main body 121 in the contact hole V1. In this way, the common electrode 140 is not directly electrically connected to the pixel electrode 120 to avoid a short circuit between the common electrode 140 and the pixel electrode 120.

In particular, in the above embodiments, the counter substrate 200 may be a color filter substrate, but in other embodiments, the counter substrate 200 may not include any color resists 22R, 22G, and 22B, and the pixel array The substrate 100 may further include a COA (Color Filter On Array). In other words, the color resists 22R, 22G, and 22B can be formed on the pixel array substrate 100, so the counter substrate 200 is not limited to being a color filter substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of invention protection shall be subject to the scope of the attached patent application.

10: Display panel 22B, 22G, 22R: color resistance 100: Pixel array substrate 111: scan line 112: data line 113: Touch signal cable 120: pixel electrode 121: main body 122: Extension 123: Connection part 124: Slit 130: active component 140: Common electrode 141, 142: Opening 150: substrate 160, 161, 162, 163: insulating layer 200: Opposite substrate 210: black matrix 250: Carrying board 251: display surface 300: display medium A2: area C13: Channel layer D1: First direction D2: second direction D13: Dip pole G13: Gate P10, P11, P12, P13: sub-pixel area PH0, PH1, PH2, PH3: pixel opening PM1: main pixel area R1: containment area S13: Source V1, V2: contact hole

FIG. 1A is a schematic circuit diagram of a pixel array substrate according to at least one embodiment of the invention. FIG. 1B is a schematic diagram of a circuit of a common electrode and a touch signal line of the pixel array substrate in FIG. 1A. FIG. 1C is a schematic top view of a counter substrate suitable for combining with the pixel array substrate in FIG. 1A. FIG. 2 is a schematic diagram of local wiring of the pixel array substrate in FIG. 1A. 3A and 3B are schematic cross-sectional views of a display panel according to at least one embodiment of the invention.

100: Pixel array substrate

111: scan line

112: data line

113: Touch signal cable

120: pixel electrode

121: main body

122: Extension

130: active component

A2: area

D1: First direction

D2: second direction

D13: Dip pole

G13: Gate

P10, P11, P12, P13: sub-pixel area

R1: containment area

S13: Source

Claims (14)

A pixel array substrate includes: A substrate; A plurality of scan lines are arranged on the substrate and extend along a first direction; A plurality of data lines and at least one touch signal line are arranged on the substrate and extend along a second direction, wherein the scan lines, the data lines and the at least one touch signal line are interlaced to define a plurality of times Pixel area At least one common electrode is disposed on the substrate, wherein the at least one touch signal line is electrically connected to the at least one common electrode; A plurality of active components are electrically connected to the scan lines and the data lines; A plurality of pixel electrodes are arranged overlapping the at least one common electrode, wherein each of the pixel electrodes is distributed in the two adjacent sub-pixel regions across one of the scan lines along the second direction, And each pixel electrode is electrically connected to one of the active devices. The pixel array substrate according to claim 1, wherein each pixel electrode includes a main body portion and an extension portion, the main body portion is connected to the extension portion, and the extension portions of the two adjacent pixel electrodes are located In the same pixel area of this time. The pixel array substrate according to claim 2, wherein the main body portions of the pixel electrodes respectively correspond to a plurality of color resists. The pixel array substrate according to claim 2, wherein the extensions of the two adjacent pixel electrodes located in the same sub-pixel area correspond to a colorless resistance area. The pixel array substrate according to claim 2, wherein in the 3×3 matrix of the sub-pixel area rows adjacent to each other, the same scan line controls two of the sub-pixel areas的 These main parts. The pixel array substrate according to claim 1, wherein there is a accommodating area between the pixel electrodes in two adjacent rows, and each of the data lines and each of the at least one touch signal line are respectively disposed in the accommodating area However, the data line and the at least one touch signal line are not arranged in the same accommodating area. A display panel including: A pixel array substrate, including: A substrate; A plurality of scan lines are arranged on the substrate and extend along a first direction; A plurality of data lines and at least one touch signal line are arranged on the substrate and extend along a second direction, wherein the scan lines, the data lines and the at least one touch signal line are interlaced to define a plurality of times Pixel area At least one common electrode is disposed on the substrate, wherein the at least one touch signal line is electrically connected to the at least one common electrode; A plurality of active components are electrically connected to the scan lines and the data lines; A plurality of pixel electrodes are arranged overlapping the at least one common electrode, wherein each of the pixel electrodes is distributed in the two adjacent sub-pixel regions across one of the scan lines along the second direction, And each pixel electrode is electrically connected to one of the active components; A pair of facing substrates arranged on the opposite side of the pixel array substrate; and A display medium is arranged between the opposite substrate and the pixel array substrate. The display panel according to claim 7, wherein each of the pixel electrodes includes a main body portion and an extension portion, the main body portion is connected to the extension portion, and the extension portions of the two adjacent pixel electrodes are located at the same In this pixel area. The display panel according to claim 8, wherein the main body portions of the pixel electrodes respectively correspond to a plurality of color resists. The display panel according to claim 8, wherein the extensions of the two adjacent pixel electrodes located in the same sub-pixel area correspond to a colorless resistance area. The display panel according to claim 8, wherein the counter substrate includes: A bearing plate; A black matrix with a plurality of pixel openings and arranged on the carrying plate; and A plurality of color resists are arranged on the carrier board and respectively arranged in part of the pixel openings, wherein the main body portions of the pixel electrodes correspond to the color resists respectively. The display panel according to claim 11, wherein the extensions of the two adjacent pixel electrodes located in the same sub-pixel area correspond to the pixel openings without any color resistance of the color. The display panel according to claim 8, wherein in the 3×3 matrix of the adjacent sub-pixel area rows, the same scan line controls the two sub-pixel areas The main body. The display panel according to claim 7, wherein there is an accommodating area between the pixel electrodes in two adjacent rows, and each of the data lines and each of the at least one touch signal line are respectively arranged in the accommodating area , But the data line and the at least one touch signal line are not arranged in the same accommodating area.

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