TW202201191A - Display panel and pixel array substrate - Google Patents
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- TW202201191A TW202201191A TW109120898A TW109120898A TW202201191A TW 202201191 A TW202201191 A TW 202201191A TW 109120898 A TW109120898 A TW 109120898A TW 109120898 A TW109120898 A TW 109120898A TW 202201191 A TW202201191 A TW 202201191A
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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Abstract
Description
本發明是有關於一種顯示器,且特別是有關於一種顯示面板及其畫素陣列基板。The present invention relates to a display, and more particularly, to a display panel and a pixel array substrate thereof.
現有內嵌式觸控顯示面板(in-cell touch display panel)通常具有至少一條觸控訊號線。一般而言,觸控訊號線設置在相鄰兩行畫素電極之間,所以觸控訊號線會與其中一條資料線相鄰。也就是說,在相鄰兩行畫素電極之間的同一個容置區域內,不僅會設置資料線,而且也會設置觸控訊號線。因此,觸控訊號線與資料線會一起設置在同一個容置區域內,從而造成內嵌式觸控顯示面板具有偏低的穿透率(等同於開口率)。Existing in-cell touch display panels usually have at least one touch signal line. Generally speaking, the touch signal line is disposed between two adjacent rows of pixel electrodes, so the touch signal line is adjacent to one of the data lines. That is to say, in the same accommodating area between two adjacent rows of pixel electrodes, not only data lines but also touch signal lines are arranged. Therefore, the touch signal lines and the data lines are disposed together in the same accommodating area, so that the in-cell touch display panel has a low transmittance (equivalent to an aperture ratio).
本發明至少一實施例提供一種畫素陣列基板,以改善現有內嵌式觸控顯示面板的穿透率。At least one embodiment of the present invention provides a pixel array substrate to improve the transmittance of an existing in-cell touch display panel.
本發明另一實施例提供一種顯示面板,其具有上述畫素陣列基板。Another embodiment of the present invention provides a display panel having the above-mentioned pixel array substrate.
本發明至少一實施例所提出的畫素陣列基板,包括基板、多條掃描線、多條資料線、多個主動元件、多個畫素電極、至少一共用電極以及至少一條觸控訊號線。這些掃描線、這些資料線、觸控訊號線與共用電極皆設置於基板上。掃描線沿第一方向延伸,而資料線與觸控訊號線沿第二方向延伸。這些掃描線、這些資料線與觸控訊號線交錯而定義多個次畫素區。觸控訊號線電性連接至少共用電極。這些主動元件電性連接這些掃描線與這些資料線。這些畫素電極與共用電極重疊設置。各個畫素電極沿著第二方向跨越這些掃描線之其中一者而分佈於相鄰兩個次畫素區中。各個畫素電極電性連接這些主動元件之其中一者。The pixel array substrate proposed in at least one embodiment of the present invention includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of active elements, a plurality of pixel electrodes, at least one common electrode and at least one touch signal line. The scan lines, the data lines, the touch signal lines and the common electrodes are all disposed on the substrate. The scan lines extend along the first direction, and the data lines and the touch signal lines extend along the second direction. The scan lines, the data lines and the touch signal lines intersect to define a plurality of sub-pixel regions. The touch signal line is electrically connected to at least the common electrode. The active elements are electrically connected to the scan lines and the data lines. These pixel electrodes are arranged to overlap with the common electrodes. Each pixel electrode is distributed in two adjacent sub-pixel regions along one of the scan lines along the second direction. Each pixel electrode is electrically connected to one of the active elements.
在本發明至少一實施例中,各個畫素電極包括主體部以及延伸部。主體部連接延伸部,而相鄰兩個畫素電極的延伸部位於同一個次畫素區中。In at least one embodiment of the present invention, each pixel electrode includes a main body portion and an extension portion. The main body part is connected to the extension part, and the extension parts of two adjacent pixel electrodes are located in the same sub-pixel region.
在本發明至少一實施例中,這些畫素電極的主體部分別對應於多個顏色色阻。In at least one embodiment of the present invention, the main body portions of the pixel electrodes correspond to a plurality of color resists, respectively.
在本發明至少一實施例中,位於同一個次畫素區中的相鄰兩個畫素電極的延伸部對應於無色阻區。In at least one embodiment of the present invention, the extension portions of two adjacent pixel electrodes located in the same sub-pixel region correspond to the colorless resist region.
在本發明至少一實施例中,在彼此相鄰的這些次畫素區排所列成的3×3矩陣中,同一條掃描線控制其中兩個次畫素區內的這些主體部。In at least one embodiment of the present invention, in a 3×3 matrix formed by the adjacent sub-pixel regions, the same scan line controls the main portions in two of the sub-pixel regions.
在本發明至少一實施例中,相鄰兩行畫素電極之間存有容置區域,而各條資料線與各條觸控訊號線各自配置於此容置區域中,但資料線與觸控訊號線不設置於同一個容置區域中。In at least one embodiment of the present invention, an accommodating area exists between two adjacent rows of pixel electrodes, and each data line and each touch signal line are respectively arranged in this accommodating area, but the data lines and touch The control signal lines are not arranged in the same accommodating area.
本發明其他至少一實施例所提出的顯示面板包括上述畫素陣列基板、對向基板與顯示介質。對向基板設置於畫素陣列基板的對面,而顯示介質設置於對向基板與畫素陣列基板之間。A display panel provided by at least one other embodiment of the present invention includes the above-mentioned pixel array substrate, an opposite substrate, and a display medium. The opposite substrate is arranged on the opposite side of the pixel array substrate, and the display medium is arranged between the opposite substrate and the pixel array substrate.
在本發明至少一實施例中,上述對向基板包括承載板、黑矩陣與多個顏色色阻。黑矩陣具有多個畫素開口,並設置於承載板上。這些顏色色阻設置於承載板上,並分別設置於部分這些畫素開口中,其中這些畫素電極的主體部分別對應於這些顏色色阻。In at least one embodiment of the present invention, the opposite substrate includes a carrier plate, a black matrix, and a plurality of color resists. The black matrix has a plurality of pixel openings and is arranged on the carrier plate. The color resists are disposed on the carrier plate and are respectively disposed in some of the pixel openings, wherein the main portions of the pixel electrodes correspond to the color resists respectively.
在本發明至少一實施例中,其中位於同一個次畫素區中的相鄰兩個畫素電極的這些延伸部對應於沒有設置任何顏色色阻的畫素開口。In at least one embodiment of the present invention, the extending portions of two adjacent pixel electrodes located in the same sub-pixel region correspond to pixel openings without any color resistance.
由於各個畫素電極沿著第二方向跨越其中一條掃描線而分佈於相鄰兩個次畫素區中,且各個畫素電極電性連接其中一個主動元件,因此一個主動元件可控制1個以上的次畫素區(例如,1.5個次畫素區)。如此,畫素陣列基板可採用較少數量的資料線控制這些畫素電極,以使觸控訊號線與資料線不用一起設置在同一個相鄰兩行畫素電極之間的容置區域內,進而提升顯示面板的穿透率。Since each pixel electrode is distributed in two adjacent sub-pixel regions across one of the scan lines along the second direction, and each pixel electrode is electrically connected to one of the active elements, one active element can control more than one active element sub-pixel area (for example, 1.5 sub-pixel area). In this way, the pixel array substrate can use a smaller number of data lines to control these pixel electrodes, so that the touch signal lines and the data lines are not arranged together in the same accommodating area between two adjacent rows of pixel electrodes. Thereby, the transmittance of the display panel is improved.
為讓本發明的特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式,作詳細說明如下。In order to make the features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given in conjunction with the accompanying drawings, and are described in detail as follows.
在以下的內文中,為了清楚呈現本案的技術特徵,圖式中的元件(例如層、膜、基板以及區域等)的尺寸(例如長度、寬度、厚度與深度)會以不等比例的方式放大。因此,下文實施例的說明與解釋不受限於圖式中的元件所呈現的尺寸與形狀,而應涵蓋如實際製程及/或公差所導致的尺寸、形狀以及兩者的偏差。例如,圖式所示的平坦表面可以具有粗糙及/或非線性的特徵,而圖式所示的銳角可以是圓的。所以,本案圖式所呈示的元件主要是用於示意,並非旨在精準地描繪出元件的實際形狀,也非用於限制本案的申請專利範圍。In the following text, the dimensions (such as length, width, thickness and depth) of elements (such as layers, films, substrates and regions, etc.) in the drawings are exaggerated in unequal proportions in order to clearly present the technical features of the present application. . Therefore, the descriptions and explanations of the following embodiments are not limited to the dimensions and shapes of the elements in the drawings, but should cover the dimensions, shapes and deviations caused by actual manufacturing processes and/or tolerances. For example, the flat surfaces shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements shown in the drawings in this application are mainly for illustration, and are not intended to accurately depict the actual shapes of the elements, nor are they intended to limit the scope of the patent application of this application.
其次,本案內容中所出現的「約」、「近似」或「實質上」等這類用字不僅涵蓋明確記載的數值與數值範圍,而且也涵蓋發明所屬技術領域中具有通常知識者所能理解的可允許偏差範圍,其中此偏差範圍可由測量時所產生的誤差來決定,而此誤差例如是起因於測量系統或製程條件兩者的限制。此外,「約」可表示在上述數值的一個或多個標準偏差內,例如±30%、±20%、±10%或±5%內。本案文中所出現的「約」、「近似」或「實質上」等這類用字可依光學性質、蝕刻性質、機械性質或其他性質來選擇可以接受的偏差範圍或標準偏差,並非單以一個標準偏差來套用以上光學性質、蝕刻性質、機械性質以及其他性質等所有性質。Secondly, words such as "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical value and numerical value range, but also cover the understanding of those with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range of , wherein the deviation range can be determined by the error generated during measurement, for example, the error is caused by the limitations of both the measurement system or the process conditions. Further, "about" can mean within one or more standard deviations of the above-mentioned numerical value, eg, within ±30%, ±20%, ±10%, or ±5%. Words such as "about", "approximately" or "substantially" appearing in this text may be used to select acceptable ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, not a single Standard deviation to apply all of the above optical, etch, mechanical and other properties.
圖1A是本發明至少一實施例的畫素陣列基板的電路示意圖。請參閱圖1A,畫素陣列基板100包括多條掃描線111、多條資料線112以及至少一條觸控訊號線113,其中圖1A繪示兩條觸控訊號線113作為舉例說明。這些掃描線111沿第一方向D1延伸,而這些資料線112與觸控訊號線113沿第二方向D2延伸,其中第一方向D1可與第二方向D2實質上垂直。FIG. 1A is a schematic circuit diagram of a pixel array substrate according to at least one embodiment of the present invention. Referring to FIG. 1A , the
以圖1A為例,第一方向D1可為水平方向,而第二方向D2可為垂直方向,所以在圖1A中,掃描線111呈水平走向,而資料線112與觸控訊號線113呈垂直走向。此外,在其他實施例中,第一方向D1可為垂直方向,而第二方向D2可為水平方向,所以這些掃描線111、資料線112與觸控訊號線113的走向並不以圖1A為限制。Taking FIG. 1A as an example, the first direction D1 can be a horizontal direction, and the second direction D2 can be a vertical direction. Therefore, in FIG. 1A , the
這些掃描線111、資料線112與觸控訊號線113交錯而定義多個次畫素區P10、P11、P12與P13,其中這些次畫素區P10、P11、P12與P13可呈矩陣排列。例如,圖1A所示的多個次畫素區P10、P11、P12與P13可排列成3×3矩陣,其可由二條資料線112、四條掃描線111以及二條觸控訊號線113排列而成。The
在其他實施例中,畫素陣列基板100可包括超過二條的資料線112、一條或超過二條的觸控訊號線113以及超過四條的掃描線111,所以圖1A所示的次畫素區P10、P11、P12與P13數量、資料線112數量、觸控訊號線113數量以及掃描線111數量僅供舉例說明,並非用以限制本發明。In other embodiments, the
圖1A中排列成3×3矩陣的這些次畫素區P10、P11、P12與P13可規則地重複排列。換句話說,圖1A中的由次畫素區P10、P11、P12與P13所排列而成的3×3矩陣可視為一個重複單元。此重複單元可複製多個,而這些重複單元排列成更大的矩陣,以使更多數量的次畫素區P10、P11、P12與P13能排列成超過3×3的大矩陣。These sub-pixel regions P10 , P11 , P12 and P13 arranged in a 3×3 matrix in FIG. 1A may be regularly repeated. In other words, the 3×3 matrix formed by the arrangement of the sub-pixel regions P10 , P11 , P12 and P13 in FIG. 1A can be regarded as a repeating unit. This repeating unit can be replicated in multiples, and these repeating units are arranged in a larger matrix, so that a greater number of sub-pixel regions P10, P11, P12 and P13 can be arranged in a large matrix exceeding 3×3.
畫素陣列基板100還包括多個畫素電極120,而各個畫素電極120沿著第二方向D2跨越這些掃描線111之其中一者而分佈於這些次畫素區P10、P11、P12與P13其中相鄰兩個中。以圖1A為例,其中一個畫素電極120沿著第二方向D2從中間上方的次畫素區P12,跨過一條掃描線111而延伸至中間的次畫素區P10。另一個畫素電極120沿著第二方向D2從中間的次畫素區P10,跨過另一條掃描線111而延伸至中間下方的次畫素區P12。The
圖1B是圖1A中的畫素陣列基板的共用電極與觸控訊號線的電路示意圖。請參閱圖1A與圖1B,畫素陣列基板100還包括至少一個共用電極140。以圖1B為例,畫素陣列基板100包括多個共用電極140與多條觸控訊號線113,其中這些共用電極140可呈矩陣排列,如圖1B所示。另外,圖1B所示的共用電極140與觸控訊號線113兩者的數量僅供舉例說明,並非限制本發明。FIG. 1B is a schematic circuit diagram of the common electrodes and touch signal lines of the pixel array substrate in FIG. 1A . Please refer to FIG. 1A and FIG. 1B , the
這些觸控訊號線113分別電性連接這些共用電極140,其中圖1B所示的這些觸控訊號線113可以是一對一地電性連接這些共用電極140。各個共用電極140的尺寸(等同於面積)遠大於次畫素區P10、P11、P12與P13任一者的尺寸,其中多個畫素電極120能與至少一個共用電極140重疊設置,而各個共用電極140分佈於部分這些次畫素區P10、P11、P12與P13中。The
舉例而言,單一個共用電極140可以涵蓋排列成30×30矩陣的900個主畫素區PM1,而觸控訊號線113分佈於多個次畫素區P10、P11、P12與P13,其中單一個主畫素區PM1可包括多個次畫素區。例如,各個主畫素區PM1可包括次畫素區P10、P11、P12與P13其中至少三個。所以,單一個共用電極140能涵蓋至少2700個次畫素區,其包括次畫素區P10、P11、P12與P13。由此可知,多個(例如2700個以上)畫素電極120可以與一個共用電極140重疊設置。For example, a single
須說明的是,圖1B簡化繪示共用電極140的形狀,並將各個共用電極140的形狀畫成正方形。在實際情況中,共用電極140會因為例如減少寄生電容以及避免與畫素電極120之間發生短路等考量而具有至少一個開口,所以共用電極140的形狀不會是如圖1B所示的正方形。It should be noted that, FIG. 1B shows the shape of the
圖1C是適於與圖1A中的畫素陣列基板結合的對向基板的俯視示意圖。請參閱圖1C,對向基板200能與畫素陣列基板100結合,而且對向基板200可以是彩色濾光基板,其中畫素陣列基板100與對向基板200可用來製作成顯示面板。此外,對向基板200包括黑矩陣210以及多個顏色色阻22R、22G與22B。FIG. 1C is a schematic top view of a counter substrate suitable for combining with the pixel array substrate of FIG. 1A . 1C, the
黑矩陣210的形狀可以是網狀,並具有多個畫素開口PH0、PH1、PH2與PH3,而這些顏色色阻22R、22G與22B分別設置於這些畫素開口PH1、PH2與PH3中,但不設置於畫素開口PH0中。換句話說,所有顏色色阻22R、22G與22B分別設置於部分這些畫素開口中,即設置於畫素開口PH1、PH2與PH3中,但是其他畫素開口PH0內不會設置任何顏色色阻22R、22G與22B。所以,畫素開口PH0為對向基板200的無色阻區。The shape of the
顏色色阻22R、22G與22B皆為濾光層,而濾光層的構成材料可以是有色光阻或樹脂。這些顏色色阻22R具有相同顏色。同樣地,這些顏色色阻22G具有相同顏色,而這些顏色色阻22B具有相同顏色,但是顏色色阻22R、22G與22B卻具有彼此不同的顏色。例如,這些顏色色阻22R可皆為紅色濾光層,這些顏色色阻22G可皆為綠色濾光層,而這些顏色色阻22B可皆為藍色濾光層。The color resists 22R, 22G and 22B are all filter layers, and the constituent materials of the filter layers can be colored resists or resins. These color resists 22R have the same color. Likewise, the color resists 22G have the same color, and the color resists 22B have the same color, but the color resists 22R, 22G, and 22B have different colors from each other. For example, the color resists 22R can all be red filter layers, the color resists 22G can all be green filter layers, and the color resists 22B can all be blue filter layers.
特別一提的是,在圖1C所示的實施例中,相同顏色的顏色色阻可以沿第二方向D2(例如垂直方向)排列在同一行中。以圖1C為例,這些顏色色阻22R、22G與22B分別沿第二方向D2排列在三行中,其中多個顏色色阻22R排列於左邊一行,多個顏色色阻22G排列於中間一行,而多個顏色色阻22B排列於右邊一行。不過,在其他實施例中,不同顏色的顏色色阻也可沿第二方向D2排列在同一行。例如,顏色色阻22R、22G與22B可沿第二方向D2排列在同一行中。因此,圖1C所示的這些顏色色阻22R、22G與22B的排列方式只是舉例說明,並非限制本發明。It is particularly mentioned that, in the embodiment shown in FIG. 1C , the color resists of the same color may be arranged in the same row along the second direction D2 (for example, the vertical direction). Taking FIG. 1C as an example, the
請參閱圖1A與圖1C,在畫素陣列基板100與對向基板200結合之後,對向基板200會設置於畫素陣列基板100的對面,而這些畫素電極120會對應這些顏色色阻22R、22G與22B。具體而言,各個畫素電極120包括主體部121以及延伸部122,其中主體部121連接延伸部122,而相鄰兩個畫素電極120的延伸部122皆位於同一個次畫素區P10中。延伸部122僅設置於次畫素區P10內,但不設置於次畫素區P11、P12與P13內。相反地,這些主體部121分別設置於次畫素區P11、P12與P13內,但不設置於次畫素區P10內。1A and FIG. 1C , after the
這些畫素電極120的主體部121分別對應於這些顏色色阻22R、22G與22B。換句話說,各個主體部121會對準這些顏色色阻22R、22G與22B其中一個。例如,圖1A中位在中間上方的主體部121會對準圖1C中位在中間上方的畫素開口PH2內的顏色色阻22G。同樣地,圖1A中位在中間右邊的主體部121會對準圖1C中位在中間右邊的畫素開口PH3內的顏色色阻22B,而圖1A中位在中間左邊的主體部121會對準圖1C中位在中間左邊的畫素開口PH1內的顏色色阻22R。The
這些畫素電極120的延伸部122分別對應於這些畫素開口PH0,而在本實施例中,位於同一個次畫素區P10中的這些延伸部122會對應於沒有設置任何顏色色阻22R、22G與22B的一個畫素開口PH0(即無色阻區)。例如,圖1A中位在左上方的兩個延伸部122對準圖1C中位在左上方的畫素開口PH0。同樣地,圖1A中位在中間的兩個延伸部122對準圖1C中位在中間的畫素開口PH0,而圖1A中位在右下方的兩個延伸部122對準圖1C中位在右下方的畫素開口PH0。The extending
在圖1A所示的由多個次畫素區P10、P11、P12與P13排列而成的3×3矩陣中,裡面設有延伸部122的這些次畫素區P10可位於此3×3矩陣的對角線位置。以圖1A為例,這些次畫素區P10可位在3×3矩陣中的左上、中間與右下三個位置。相似地,在圖1C所示的黑矩陣210中,這些畫素開口PH0、PH1、PH2與PH3也可排列而成的3×3矩陣,其中沒有設置任何顏色色阻22R、22G與22B的這些畫素開口PH0可位於此3×3矩陣的對角線位置,例如在左上、中間與右下三個位置,以使這些次畫素區P10能分別對應這些畫素開口PH0。In the 3×3 matrix formed by a plurality of sub-pixel regions P10 , P11 , P12 and P13 arranged in FIG. 1A , the sub-pixel regions P10 with the
請參閱圖1A,畫素陣列基板100還包括多個主動元件130,其中主動元件130可以是電晶體,且例如是如圖1A所示的場效電晶體(Field-Effect Transistor,FET),所以各個主動元件130可以具有閘極G13、源極S13以及汲極D13。主動元件130電性連接這些掃描線111、資料線112與畫素電極120,而各個畫素電極120電性連接這些主動元件130之其中一者。Referring to FIG. 1A , the
以圖1A為例,在每一個主動元件130中,主動元件130的閘極G13電性連接掃描線111,源極S13電性連接資料線112,而汲極D13電性連接畫素電極120。如此,掃描線111與資料線112能經由主動元件130來控制對應的畫素電極120,以促使影像的形成。Taking FIG. 1A as an example, in each
在圖1A所示的實施例中,主動元件130是從主體部121電性連接畫素電極120,而非從延伸部122電性連接畫素電極120。由於各個畫素電極120是跨越掃描線111而分佈於次畫素區P10以及與其相鄰的次畫素區P11、P12或P13,而且次畫素區P10內設置相鄰兩個延伸部122,但不設置任何主體部121。In the embodiment shown in FIG. 1A , the
在沿著第一方向D1排列於圖1A中最上面的一列次畫素區P10、P12與P13中,最上面的掃描線111經由主動元件130電性連接位於次畫素區P12與P13內的兩個主體部121,但卻沒有電性連接位於左上方次畫素區P10內的延伸部122,以至於圖1A中最上面的掃描線111能控制圖1A中最上面次畫素區P12與P13內的主體部121,但不控制位於左上方次畫素區P10內的延伸部122。In the uppermost column of sub-pixel regions P10 , P12 and P13 arranged along the first direction D1 in FIG. 1A , the
同理,從上面數來第二條的掃描線111控制圖1A中位於中間一列次畫素區P11與P13內的主體部121,但不控制位於中間的次畫素區P10內的任何延伸部122。從上面數來第三條的掃描線111(即倒數第二條掃描線111)控制圖1A中位於下面一列的次畫素區P11與P12內的主體部121,但不控制位於右下方次畫素區P10內的任何延伸部122。由此可知,在彼此相鄰的這些次畫素區P10、P11、P12與P13排所列成的3×3矩陣中(如圖1A所示),同一條掃描線111能控制位在這些次畫素區P11、P12與P13其中兩個內的這些主體部121。Similarly, the
在位於左上方的次畫素區P10中,下面的延伸部122連接位於中間左邊的次畫素區P11中的主體部121,而從上面數來第二條的掃描線111電性連接位於中間左邊的次畫素區P11中的主體部121。因此,位於左上方次畫素區P10內的下面延伸部122是由從上面數來第二條掃描線111控制。在位於左上方的次畫素區P10中,上面的延伸部122是由圖1A中最上面掃描線111的前一級掃描線111所控制。因此,位於左上方的次畫素區P10內的這兩個延伸部122分別由兩條不同的掃描線111所控制。In the sub-pixel region P10 located at the upper left, the
同理,在位於中間的次畫素區P10中,上面的延伸部122電性連接圖1A中最上面的掃描線111,而下面的延伸部122電性連接從上面數來第三條掃描線111。在位於右下方的次畫素區P10中,上面的延伸部122電性連接從上面數來第二條掃描線111,而下面的延伸部122電性連接最下面的掃描線111。由此可知,各個次畫素區P10內的兩個延伸部122分別由兩條不同的掃描線111控制。Similarly, in the sub-pixel region P10 located in the middle, the
雖然各個次畫素區P10內的兩個延伸部122分別由兩條不同的掃描線111控制,且這兩條掃描線111皆直接控制其他次畫素區P10以外(即次畫素區P11、P12與P13其中兩者)的主體部121,但延伸部122對應沒有設置任何顏色色阻22R、22G與22B的畫素開口PH0(即無色阻區)。因此,次畫素區P10可作為無色畫素,例如白色畫素,而不會作為顯示面板的有色畫素,例如紅色、綠色或藍色畫素。所以,這些延伸部122實質上不會破壞顯示面板在色彩方面的整體表現。Although the two extending
在圖1A所示的實施例中,排列於相鄰兩行的這些畫素電極120之間存有容置區域R1,而同一條資料線112配置於相鄰兩行畫素電極120之間的容置區域R1,並且可以電性連接這兩行畫素電極120。因此,相鄰兩行畫素電極120可由同一條資料線112來控制。In the embodiment shown in FIG. 1A , there is an accommodation region R1 between the
由於各個畫素電極120沿著第二方向D2跨越其中一條掃描線111而分佈於次畫素區P10以及與其相鄰的次畫素區P11、P12或P13中,且各個畫素電極120電性連接一個主動元件130,因此一個主動元件130能控制1個以上的次畫素區,例如1.5個次畫素區,即次畫素區P11、P12與P13其中一個以及與其相鄰的半個次畫素區P10。如此,畫素陣列基板100能用較少數量的資料線112控制這些畫素電極120,進而減少源極驅動元件的輸出端(port)數量,其中源極驅動元件例如是積體電路(Integrated Circuit,IC)。Since each
以圖1A為例,在圖1A所示的由次畫素區P10、P11、P12與P13排列而成的3×3矩陣中,總數量為9個的這些次畫素區P10、P11、P12與P13是由6個主動元件130來控制,而沿著第二方向D2排列成相鄰三行的這些次畫素區P10、P11、P12與P13內的畫素電極120可以用兩條資料線112來控制。Taking FIG. 1A as an example, in the 3×3 matrix formed by the sub-pixel regions P10 , P11 , P12 and P13 arranged in FIG. 1A , the total number of these sub-pixel regions P10 , P11 , P12 is 9 and P13 are controlled by six
由此可知,平均一個主動元件130能控制1.5個次畫素,而平均一條資料線112可控制1.5行的畫素電極120,所以資料線112的數量少於這些畫素電極120的行數。然而,這些資料線112仍可以控制這些畫素電極120,而所有資料線112可不用設置於所有容置區域R1內,即有的容置區域R1內可以不用設置任何資料線112。It can be seen that, on average, one
同一條觸控訊號線113也可以單獨配置於相鄰兩行畫素電極120之間的容置區域R1。詳細而言,由於有的容置區域R1內不用設置任何資料線112,因此儘管各條資料線112與各條觸控訊號線113各自配置於容置區域R1中,但資料線112與觸控訊號線113不會設置於同一個容置區域R1中。相較於現有內嵌式觸控顯示面板,畫素陣列基板100可達到較高的穿透率(開口率),從而提升顯示面板的亮度。此外,在圖1A所示的實施例中,相鄰兩條觸控訊號線113之間可以設置兩條資料線112。The same
圖2是圖1A中的畫素陣列基板的局部佈線示意圖,而圖3A是本發明至少一實施例的顯示面板的剖面示意圖,其中圖2所繪示的是圖1A中的畫素陣列基板100在區域A2內的佈線,而圖3A所示的畫素陣列基板100是沿著圖2中的線3A-3A剖面而繪製。2 is a schematic diagram of partial wiring of the pixel array substrate in FIG. 1A , and FIG. 3A is a schematic cross-sectional view of a display panel according to at least one embodiment of the present invention, wherein FIG. 2 shows the
請參閱圖2與圖3A,顯示面板10包括畫素陣列基板100、對向基板200以及顯示介質300。對向基板200設置於畫素陣列基板100的對面,而顯示介質300設置於對向基板200與畫素陣列基板100之間。顯示介質300可以是液晶材料,而顯示面板10可以是液晶顯示面板,其例如是邊界電場切換型(Fringe Field Switching,FFS)液晶顯示面板,但顯示面板10並不限制只能是邊界電場切換型液晶顯示面板。Please refer to FIG. 2 and FIG. 3A , the
畫素陣列基板100包括基板150,其例如是玻璃板等透明基板,而這些掃描線111、資料線112、觸控訊號線113、共用電極140、畫素電極120以及主動元件130皆設置於基板150上。畫素陣列基板100可以還包括絕緣層160、161、162與163以及通道層C13,其中通道層C13可以是半導體層。The
主動元件130的閘極G13形成於基板150上,而絕緣層160覆蓋閘極G13。閘極G13與掃描線111可以是由同一層膜層經蝕刻後而形成,而此膜層例如是金屬層。因此,閘極G13與掃描線111皆可以形成在基板150的同一表面上。通道層C13、源極S13以及汲極D13皆位於絕緣層160上,而絕緣層161覆蓋通道層C13、源極S13與汲極D13。The gate electrode G13 of the
絕緣層162形成於絕緣層161上,而絕緣層163與共用電極140形成於絕緣層162上,其中絕緣層163覆蓋共用電極140。畫素電極120形成於絕緣層163上,其中畫素電極120會與共用電極140重疊設置。此外,畫素電極120的主體部121與延伸部122皆可以具有多條並列的狹縫124,如圖2與圖3A所示。The insulating
絕緣層161、162與163內具有多個接觸孔V1,其中各個接觸孔V1可以是貫穿絕緣層161、162與163而形成,即接觸孔V1可從絕緣層163頂面,經由絕緣層162而延伸至絕緣層161底面。這些接觸孔V1分別對應這些汲極D13,以使位於接觸孔V1底下的部分汲極D13不被絕緣層161、162與163覆蓋。如此,畫素電極120的主體部121可從絕緣層163延伸至接觸孔V1底下的汲極D13,以使主體部121經由接觸孔V1而電性連接汲極D13,讓主動元件130能電性連接畫素電極120。The insulating
另外,絕緣層161與162內具有多個接觸孔V2。各個接觸孔V2可以是貫穿絕緣層161與162而形成,即接觸孔V2可從絕緣層162頂面而延伸至絕緣層161底面。從圖3A來看,接觸孔V2的深度明顯小於接觸孔V1的深度。這些接觸孔V2分別對應這些觸控訊號線113,以使位於接觸孔V2底下的部分觸控訊號線113不被絕緣層161與162覆蓋。如此,共用電極140可從絕緣層162延伸至接觸孔V2底下的觸控訊號線113,以使共用電極140能經由接觸孔V2而電性連接觸控訊號線113。此外,接觸孔V2可被絕緣層163所填滿,如圖3A所示。In addition, the insulating
在圖2所示的實施例中,各個畫素電極120可以還包括連接部123,而在同一個畫素電極120中,連接部123位於主體部121與延伸部122之間,並連接主體部121與延伸部122。因此,主體部121可經由連接部123而連接延伸部122,其中各個延伸部122可設置在其中一條掃描線111上方,如圖2所示。In the embodiment shown in FIG. 2 , each
須說明的是,圖2所示的連接部123只是本發明多種實施例的其中一種。在其他實施例中,主體部121可利用圖2以外的其他連接部來連接延伸部122。或者,主體部121也可以直接連接延伸部122,無需採用連接部123。因此,圖2所示的連接部123僅供舉例說明,並非限制主體部121與延伸部122之間的連接方式。It should be noted that the connecting
對向基板200包括承載板250。黑矩陣210與這些顏色色阻22R、22G與22B皆設置於承載板250上,而顏色色阻22R、22G與22B分別位於黑矩陣210的畫素開口PH1、PH2與PH3內,其中黑矩陣210可遮蓋主動元件130、掃描線111與觸控訊號線113,而顏色色阻22R、22G與22B會對應這些畫素電極120的主體部121。例如,在圖3A中,顏色色阻22B位於畫素開口PH3中,而主體部121對準畫素開口PH3內的顏色色阻22B。The
圖3B是顯示面板10的另一個剖面示意圖,其中圖3B所示的畫素陣列基板100是沿著圖2中的線3B-3B剖面而繪製。請參閱圖2與圖3B,黑矩陣210更遮蓋這些資料線112,而這些資料線112皆位於絕緣層160上。源極S13、汲極D13(請參閱圖3A)與資料線112可由同一層膜層經蝕刻後而形成,其中膜層例如是金屬層。FIG. 3B is another schematic cross-sectional view of the
沒有設置任何顏色色阻22R、22G與22B的畫素開口PH0對應畫素電極120的延伸部122。以圖3B為例,延伸部122會對準畫素開口PH0。在圖3B所示的實施例中,畫素開口PH0可以不被任何膜層填滿,如圖3B所示。不過,在其他實施例中,畫素開口PH0可以被透明層填滿,其中此透明層可由透明光阻或樹脂來形成。因此,畫素開口PH0不以圖3B為限制。The pixel openings PH0 without any color resists 22R, 22G, and 22B correspond to the extending
請參閱圖3A與圖3B,顯示面板10是以邊界電場切換型液晶顯示面板作為舉例說明。共用電極140能輸出共用電壓,而資料線112能經由主動元件130輸出畫素電壓至對應的畫素電極120,其中共用電壓通常不同於畫素電壓,因此畫素電極120與共用電極140之間能產生電場。由於畫素電極120的主體部121與延伸部122具有多條並列的狹縫124,因此畫素電極120與共用電極140之間可產生具水平分量的電場。當顯示介質300為液晶材料時,上述具水平分量的電場能驅動液晶材料(顯示介質300)內的液晶分子偏轉,以使顯示面板10得以顯示影像。Please refer to FIG. 3A and FIG. 3B , the
另外,共用電極140還可具有觸控感測的功能。詳細而言,當顯示面板10運作時,這些資料線112短暫地暫停輸出畫素電壓,而共用電極140也短暫地暫停輸出共用電壓,以使共用電極140能進行觸控感測。當有物件(例如手指或觸控筆)接觸顯示面板10的顯示面251時,進行觸控感測的這些共用電極140能偵測物件的位置與移動。如此,使用者能利用物件來觸控並操作顯示面板10。In addition, the
請參閱圖2與圖3A,共用電極140可以具有多個開口141(圖2繪示一個為例),其中開口141對應觸控訊號線113。詳細而言,開口141形成於觸控訊號線113的正上方,並沿著觸控訊號線113而延伸,所以開口141的形狀為條狀,並且對應觸控訊號線113的形狀。這些開口141能減少共用電極140與觸控訊號線113之間的重疊區域,以減少共用電極140與觸控訊號線113之間的寄生電容,從而提升共用電極140的觸控感測功能。Referring to FIGS. 2 and 3A , the
共用電極140可還具有多個開口142,其中這些而開口142分別對應這些接觸孔V1。具體而言,接觸孔V1位於開口142內,其中開口142的側壁圍繞接觸孔V1,即開口142的孔徑大於接觸孔V1的孔徑。因此,共用電極140不會接觸接觸孔V1內的主體部121。如此,共用電極140不會直接電性連接畫素電極120,以避免共用電極140與畫素電極120之間發生短路。The
特別說明的是,在以上實施例中,對向基板200可以是彩色濾光基板,但在其他實施例中,對向基板200可以不包括任何顏色色阻22R、22G與22B,而畫素陣列基板100可更包括陣列上彩色濾光層(Color Filter On Array,COA)。也就是說,顏色色阻22R、22G與22B可以形成在畫素陣列基板100上,因此對向基板200並不限制只能是彩色濾光基板。Specifically, in the above embodiments, the
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不脫離本發明精神和範圍內,當可作些許更動與潤飾,因此本發明保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the appended patent application.
10:顯示面板
22B、22G、22R:顏色色阻
100:畫素陣列基板
111:掃描線
112:資料線
113:觸控訊號線
120:畫素電極
121:主體部
122:延伸部
123:連接部
124:狹縫
130:主動元件
140:共用電極
141、142:開口
150:基板
160、161、162、163:絕緣層
200:對向基板
210:黑矩陣
250:承載板
251:顯示面
300:顯示介質
A2:區域
C13:通道層
D1:第一方向
D2:第二方向
D13:汲極
G13:閘極
P10、P11、P12、P13:次畫素區
PH0、PH1、PH2、PH3:畫素開口
PM1:主畫素區
R1:容置區域
S13:源極
V1、V2:接觸孔10:
圖1A是本發明至少一實施例的畫素陣列基板的電路示意圖。 圖1B是圖1A中的畫素陣列基板的共用電極與觸控訊號線的電路示意圖。 圖1C是適於與圖1A中的畫素陣列基板結合的對向基板的俯視示意圖。 圖2是圖1A中的畫素陣列基板的局部佈線示意圖。 圖3A與圖3B是本發明至少一實施例的顯示面板的剖面示意圖。FIG. 1A is a schematic circuit diagram of a pixel array substrate according to at least one embodiment of the present invention. FIG. 1B is a schematic circuit diagram of the common electrodes and touch signal lines of the pixel array substrate in FIG. 1A . FIG. 1C is a schematic top view of a counter substrate suitable for combining with the pixel array substrate of FIG. 1A . FIG. 2 is a schematic diagram of partial wiring of the pixel array substrate in FIG. 1A . 3A and 3B are schematic cross-sectional views of a display panel according to at least one embodiment of the present invention.
100:畫素陣列基板100: pixel array substrate
111:掃描線111: scan line
112:資料線112: data line
113:觸控訊號線113: touch signal line
120:畫素電極120: pixel electrode
121:主體部121: main body
122:延伸部122: Extensions
130:主動元件130: Active Components
A2:區域A2: Area
D1:第一方向D1: first direction
D2:第二方向D2: Second direction
D13:汲極D13: Drain
G13:閘極G13: Gate
P10、P11、P12、P13:次畫素區P10, P11, P12, P13: Sub-pixel area
R1:容置區域R1: accommodating area
S13:源極S13: Source
Claims (14)
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JP3992920B2 (en) * | 2000-11-21 | 2007-10-17 | シャープ株式会社 | Active matrix substrate |
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CN102156371B (en) * | 2010-01-15 | 2013-09-25 | 友达光电股份有限公司 | Pixel array |
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