201128277 2009-I-P-D-030TW 33328twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種基板，且特別是有關於一種晝素 陣列基板。 ' 【先前技術】 般的液晶顯示器主要是由一主動元件陣列基板、一 對向基板以及一夾於前述二基板之間的液晶層所構成。主 動元件陣列基板主要包括多條掃描線、多條資料線，排列 於掃描線與資料線間之主動元件以及與每一主動元件對應 配置之一晝素電極(Pixel Electr〇de)。而上述之主動元件通 常為薄膜電晶體，其包括閘極、半導體層、源極與汲極， 其用來作為液晶顯示單元的開關元件。 圖1為習知之一種晝素陣列基板的示意圖。請參照圖 1，此晝素陣列基板1〇〇中，多個晝素130a、13〇b排列成 夕歹各列晝素位於兩條婦描線11 〇a、n 之間，且兩條 掃描線ll〇a、ll〇b位於相鄰兩列晝素之間。其中，晝素 13〇a與晝素130b位於資料線120的兩側，晝素130a、130b 之主動元件14〇、150的閘極142、152分別與掃描線n〇a、 ii〇b電性連接，以及晝素13〇a、13〇b中之主動元件14〇、 UO的源極144、154與同—條資料線12〇電性連接。 —般來說，在製作具有此畫素陣列基板1〇〇的主動元 件陣列基板的製程中，主動元件14〇、15〇的閘極142、152 與掃描線110a、ll〇b由第一導體層（Metal 1)形成，而主 201128277 2009-I-P-D-030TW 33328twf.doc/n 動元件140、150的源極144、154、汲極146、156與資料 線120由第一導體層（Metal 2)形成，且第一導體層與第 二導體層是以不同的光罩製程進行製作的。因此，當機台 的精密度不足或是製程上的對位誤差時，主動元件14〇、 150的閘極142、152與源極144、154、沒極146、156之 間會產生相對位移而使主動元件14〇、15〇的特性偏離原有 的設計值。201128277 2009-I-P-D-030TW 33328twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a substrate, and more particularly to a halogen array substrate. [Prior Art] A liquid crystal display is mainly composed of an active device array substrate, a counter substrate, and a liquid crystal layer sandwiched between the two substrates. The active device array substrate mainly comprises a plurality of scan lines, a plurality of data lines, an active component arranged between the scan lines and the data lines, and a pixel electrode (Pixel Electr〇de) corresponding to each active element. The above active element is usually a thin film transistor comprising a gate, a semiconductor layer, a source and a drain, which are used as switching elements of the liquid crystal display unit. 1 is a schematic view of a conventional halogen matrix substrate. Referring to FIG. 1 , in the pixel array substrate 1 , a plurality of halogen elements 130 a and 13 〇 b are arranged such that each of the pixels is located between two lines 11 〇 a and n, and two scanning lines are arranged. Ll〇a, ll〇b are located between two adjacent columns of pixels. Wherein, the halogen 13〇a and the halogen 130b are located on both sides of the data line 120, and the gates 142 and 152 of the active elements 14〇 and 150 of the halogen elements 130a and 130b are electrically connected to the scanning lines n〇a and ii〇b, respectively. The connection, and the active elements 14〇 and U0 of the elements 13〇a, 13〇b are electrically connected to the same data line 12〇. Generally, in the process of fabricating the active device array substrate having the pixel array substrate, the gates 142, 152 of the active devices 14, 15 and the scan lines 110a, 110b are made of the first conductor. The layer (Metal 1) is formed, and the source 144, 154, the drain 146, 156 of the main element 201128277 2009-IPD-030TW 33328 twf.doc/n, and the data line 120 are composed of the first conductor layer (Metal 2). Formed, and the first conductor layer and the second conductor layer are fabricated in different mask processes. Therefore, when the precision of the machine is insufficient or the alignment error on the process, the relative displacement between the gates 142, 152 of the active elements 14 150 150 and the sources 144, 154 and the poles 146, 156 is generated. The characteristics of the active elements 14 〇, 15 偏离 are deviated from the original design values.
詳言之，掃描線110a、. ii〇b的訊號傳輸品質除了與掃 描線110a、110b本身的阻抗有關之外’尚與掃描線n〇a、 ll〇b上的寄生電容有關，也就是一般所說的電阻-電容效 應(R-Ceffect)。此外，掃描線11〇a、11〇b上的寄生電容大 約正比於掃描線ll〇a、110b與汲極146、156的重疊面積。 一但製程土發生對位誤差，同一條掃描線11〇&或11%上 的寄生電容將會因而改變。也就是說，製程的對位誤差將 會影響掃描線ll〇a、l10b的訊號傳輸品質。 【發明内容】 本發明提供-種晝素_基板，有效改善因為製 的對位誤差造成閘極·源極寄生電容產生變化的問題。 本發明提出-種晝素陣列基板，包括基板、 掃t田線、多條第二掃描線、多個畫素、多個第—補^ 第二:償結構。第一掃描線與第二掃描線成‘設 _二板上。育料線與第一掃描線及第二掃描線垂直相 交又設置。多個晝素包括多個第-晝素與多個第二晝素， 201128277 2009-I-P-D-030TW 33328twf.doc/n 且位於成對的一第一掃描線、一第二掃描線以及資料線之 間。第一晝素與第一掃描線及資料線的第一側相連，第二 晝素與第二掃描線及資料線的第二側相連。第一補償結構 位於所對應之資料線的第二側，第一補償結構包括第一導 體圖案、第一半導體圖案以及第一源極補償圖案，第—導 體圖案與第一掃描線連接，第一半導體圖案位於第一導體 圖案上方，第一源極補償圖案至少部分位於第一半導體圖 案上且與資料線電性連接。第二補償結構位於所對應之資 =線的第一側，第二補償結構包括第二導體圖案、第二半 導體圖案以及第二源極補償圖案，第二導體圖案與第二掃 描線連接，第二半導體圖案位於第二導體圖案上方，第二 源極補償圖案至少部分位々第二半導體圖案上且 : 線電性連接。 〃貧枓 在本發明之一實施例中，上述之第一晝素包括— 雜、-第—半導體層、—第—祕以及 -掃描線綱接，第一半導體層位以 ，上方，第-源極與第-汲極至少部分位於第 且第一源極與資料線電性連接。 一 在本發明之-實施例中，上述之第—源極 體處具有一第-寬度’第一源極補償圖案與第-導 界切齊處具有-第二寬度，第-寬度實質ί等： 晝素包括一第二 二汲極以及一第二源極，第 在本發明之一實施例中，上述之第 閘極、一第二半導體層、一第 201128277 2009-I-P-D-030TW 33328twf.doc/n 二閑極與弟二城線電性連接，第二半導體層位於第 極上方’第—源極與第二汲極至少部分位於第 上且第二源極與資料線電性連接。 隨增 在本發明之-實施例中，上述之第二源 邊界切齊處射—第三寬度，第二源_償圖案 體圖案邊界切背處具有-第四寬度，第 第四寬度。 雜 在本發明之-實施例中，上述之第—導體圖案 掃描線一體成形。 在本發明之-實施例中，上述之第二導 掃描線一體成形。 干一乐一 在本I月之戸'知例中，上述之第二源極 資料線一體成形。 貝u木〃 =本發明之—實施例中，上述之第—畫素的第—祕 ^括檢1部與連接部。梳型部環繞第一源極， :少=支’分支中至少-者延伸至第-閉極4:;; 之外的至少一凸出部。連接部由梳型部延 巧極外，且凸出部與連接部分別位於第— 相對兩側’其中凸出部與第1極邊界域處具有第五Ϊ 度，連接部與第—閑極邊界切齊處具有第六寬度，第五♦ 度實質上等於第六寬度。 & #五見 在本發明之一實施例中，上述之梳型部的分支中—者 201128277 2009-I-P-D-030TW 33328twf.doc/n 延伸至第-閘極之外，而另—者完全地位於第—閘極 區域中以使至少一凸出部的數量為一。 在本發明之-實施例中，上述之第二晝素的第 包括梳型部與連接部。梳型部環繞第二源極，梳 ^ 至少兩分支’分支中至少-者延伸至第二間極之外以^ 外的至少一凸出部。連接部由梳型部延 伸至第一閘極外’且凸出部與連接部分別位於第 相對兩側，其中凸出部與第二·邊界切齊處具有第^ 度，連接部與第二閘極邊界切齊處具有第 度實質上等於第八寬度。 兄又弟七見 延伸:發^施例十，上述之梳型部的分支中—者 L伸至第—閘極之外，者完全地位於第 區域中以使至少一凸出部的數量為一。 在本發明之一實施例中’上 於第一導體圖案。 L ^體圖案凸出 在本發明之一實施例中，上 第二 於第二導體圖案。 L ^版圖案凸出 以及述:本發明在資料線的一側配置閘極及源極， 導體條資料線的另—侧配置與閘極及源極相對應的 t;案;:極補償圖案。因此，在製作晝素結構的過： 極與源極:=3::體層之間的相對偏移並不影響間 的重疊面積的總合:亦即及Id :案之間 容可以補償mm Γ ®案韻圖案寄生電 甲1極-源極寄生電容的變化，使閘極-源極寄生 201128277 2009-I-P-D-030TW 33328twf.doc/n 電容與導體圖案-源極補償圖案寄生電容的總合為恒定 的。因此’本發明的晝素陣列基板不因製程上的對位誤差 而對顯不效果產生負面影響。換言之，本發明的晝素陣列 基板具有良好的品質以及產品良率。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 φ 【實施方式】 圖2A為本發明之第一實施例之一種晝素陣列基板的 不意圖，圖2B為圖2A之第一晝素230a與第二晝素230b 的不意圖，以及圖2C與圖2D分別為沿圖2B之A-A，線與 B-B’線的剖面示意圖。為了說明方便，圖2A中僅繪示兩 個晝素列Cn、（:㈣作為代表，且在圖2B中以位於資料線 DL(m)之兩側的第一晝素23〇a與第二畫素23〇b來進行說 明。請參照圖2A，在本實施例中，晝素陣列基板2〇〇包括 φ 基板20卜多條第一掃描線SL1⑻、SLl(n+l)、SLl(n+2) 與多條第二掃描線SL2(n-l)、SL2(n)、SL2(n+l)、多條資 ，線 DL(m-l)、DL(m)、DL(m+l)、多個晝素 230a、230b、 多/固第一補償結構260以及多個第二補償結構27〇。其中， 第掃描線SLl(n)、SLl(n+l)、SLl(n+2)與第二掃描線 SL2(n 1)' SL2(n)、SL2(n+l)在列方向上延伸，且第一掃插 ，SLl(n)與第二掃描線SL2⑻成對設置在基板2〇1上， 第一掃描線SLl(n+l)與第二掃描線SL2(n+1)成對設置在 基板2〇1上，依此類推。資料線DL(m-l)、DL(m)、DL(m+l) 201128277 2009-I-P-D-030TW 33328twf.doc/n 在行方向上延伸，且第一掃描線SLl(n)、SLl(n+l)、SLl(n+2) 及第二掃描線SL2(n-l)、SL2⑻、SL2(n+l)與資料線 DL(m-l)、DL(m)、DL(m+l)垂直相互交叉绝缘設置。 如圖2 A所示，晝素列C n位於成對的第一掃描線s L1 (η) 與第二掃描線SL2(n)之間’晝素列cn+1位於成對的第一掃 描線SLl(n+l)與第二掃描線SL2(n+l)之間，依此類推。多 個晝素230a、230b包括交替排列的多個第一晝素230a與 多個第二晝素230b，且位於成對的第一掃描線SL1(n)、 SLl(n+l)、SLl(n+2)及第二掃描線心㈣）、SL2⑻、 籲 SL2(n+l)以及資料線 DL(m-l)、DL(m)、DL(m+l)之間。詳 言之，以圖2B、圖2C以及圖2D所示的第一晝素230a與 第二晝素230b來進行說明，第一晝素23〇a與第一掃描線 SLl(n)及資料線DL(m)的第一側221a相連，第二晝素230b 與第二掃描線SL2(n)及資料線DLCm)的第二側221b相 連。在本實施例中，第一晝素230a包括第一主動元件240 與第一畫素電極249，第一主動元件24〇包括第一閘極 242、第一半導體層244、第一源極246以及第一汲極MS。 φ 其中，第一閘極242與第一掃描線su(n)電性連接，第一 半導體層244位於第一閘極242上方，第一源極246與第 一汲極248至少部分位於第—半導體層244上且第一源極 246與資料線DL(m)電性連接。第一晝素電極2的則電性 連接至第-没極248以藉由第—主動元件的開啟或是 關閉來接收資料線DL(m)上所傳輸的訊號。 第二晝素230b包括第二主動元件25〇,第二主動元件 10 201128277 2009-I-P-D-030TW 33328twf.doc/n 250包括第一閘極252、弟二半導體層254、第二源極256、 第一及極258以及弟一晝素電極259。其中，第二閘極252 與第二掃描線SL2(n)電性連接，第二半導體層254位於第 一閘極252上方，第二源極256與第二汲極258至少部分 位於第二半導體層254上且第二源極256與資料線DL(m) 電性連接。 在本實施例中，第一閘極242、第二閘極252、第一 • 掃描線SL1(n)以及第二掃描線SL2(n)例如是由第一金屬層 圖案化而成的元件，而第一源極246、第二源極256、第一 汲極248、第二汲極258以及資料線DL(m)例如是由第二 金屬層圖案化而成的元件。一旦第一金屬層與第二金屬層 的圖案化製程中，對位的精準度產生了誤差，將使兩層金 屬層圖案化後的元件在相對位置上發生偏移。如此一來， 閘極242、252與源極246、256之間的重疊面積可能產生 變化而使畫素230a、230b的元件特性受到影響。換言之， 先前技術中所k到的閘極-源極寄生電容不同使晝素陣列 基板在顯示過程中易產生顯示亮度不均勻的問題。 因此，為了避免顯示亮度不均勻的問題發生，本實施 例在晝素陣列基板200中分別為第一晝素23〇a與第二晝素 230b設計第一補償結構260與第二補償結構27〇，其設計 概念如下所述。弟一補償結構260位於所對應之資料線 DL(m)的第二側221b，換言之，第一補償結構26〇與第一 主動元件240位於所對應之資料線DL(m)的相對兩側。第 一補彳員結構260包括弟一導體圖案262、第一半導體圖案 201128277 2009-I-P-D-030TW 33328twf.doc/n 264以及第一源極補償圖案266。第一導體圖案262與第一 掃描線SLl(n)連接，第—半導體圖案264位於第一導體圖 案262上方，以及第一源極補償圖案266至少部分位於第 半導體圖案262上且與資料線DL(m)電性連接。在本實 施例t ’第-導體圖案262例如是與第-掃描線SL1⑻一 體成形，第一源極補償圖案266例如是與資料線1)1^11) 一 體成形。具體而言’第—導體圖案262例如是由上述之第 -，屬層圖案化而成的元件，而第一源極補償圖案施例 ^疋由上述之第一金屬層圖案化而成的元件。再者，在本 實施例中，是以第—半導體圖案264超出第-導體圖案262 的區域範圍為例’但在其他實施例中，第一半導體圖案撕 也了以位於第一導體圖案262的區域範圍内。In detail, the signal transmission quality of the scan lines 110a, ii 〇b is related to the parasitic capacitance on the scan lines n〇a, ll〇b, in addition to the impedance of the scan lines 110a, 110b themselves, that is, Said resistance-capacitance effect (R-Ceffect). Further, the parasitic capacitance on the scanning lines 11a, 11b is approximately proportional to the overlapping area of the scanning lines 11a, 110b and the drains 146, 156. Once the alignment error occurs in the process soil, the parasitic capacitance on the same scan line 11〇& or 11% will change accordingly. That is to say, the alignment error of the process will affect the signal transmission quality of the scan lines 11a, l10b. SUMMARY OF THE INVENTION The present invention provides a seed crystal substrate which effectively improves the variation of the gate/source parasitic capacitance caused by the alignment error of the system. The invention provides a seed crystal array substrate, which comprises a substrate, a sweeping t-line, a plurality of second scan lines, a plurality of pixels, and a plurality of first-second compensation structures. The first scan line and the second scan line are formed on the second board. The feed line is perpendicularly intersected with the first scan line and the second scan line. The plurality of elements include a plurality of singular elements and a plurality of second elements, 201128277 2009-IPD-030TW 33328 twf.doc/n and located in a pair of first scan lines, a second scan line, and data lines between. The first pixel is connected to the first side of the first scan line and the data line, and the second element is connected to the second side of the second scan line and the data line. The first compensation structure is located on the second side of the corresponding data line, the first compensation structure includes a first conductor pattern, a first semiconductor pattern, and a first source compensation pattern, and the first conductor pattern is connected to the first scan line, first The semiconductor pattern is located above the first conductor pattern, and the first source compensation pattern is at least partially located on the first semiconductor pattern and electrically connected to the data line. The second compensation structure is located on the first side of the corresponding credit=line, and the second compensation structure includes a second conductor pattern, a second semiconductor pattern, and a second source compensation pattern, and the second conductor pattern is connected to the second scan line. The two semiconductor patterns are located above the second conductor pattern, and the second source compensation pattern is at least partially located on the second semiconductor pattern and: the wires are electrically connected. In one embodiment of the invention, the first element includes: a hetero-, a --semiconductor layer, a ---- and a scan line, the first semiconductor layer is above, the first - The source and the first drain are at least partially located at the first and the first source is electrically connected to the data line. In an embodiment of the invention, the first source-source body has a first-width 'first source compensation pattern and the first-contour has a second width, a first width, and the like. The halogen includes a second dipole and a second source. In an embodiment of the invention, the first gate, the second semiconductor layer, and a second semiconductor layer, a 201128277 2009-IPD-030TW 33328twf.doc /n The second idler is electrically connected to the second bust, and the second semiconductor layer is located above the first pole. The first source and the second drain are at least partially located on the upper side and the second source is electrically connected to the data line. In the embodiment of the invention, the second source boundary is aligned to the third width, and the second source _ pattern pattern has a fourth width and a fourth width at the boundary cut. In the embodiment of the invention, the above-described first conductor pattern scanning line is integrally formed. In an embodiment of the invention, the second scan line is integrally formed. Dry one music one In the case of this I month, the above-mentioned second source data line is integrally formed. In the embodiment of the present invention, the first component of the first pixel described above includes a portion and a connecting portion. The comb portion surrounds the first source, and at least one of the less-branch branches extends to at least one of the protrusions other than the first-closed pole 4; The connecting portion is extended by the comb portion, and the protruding portion and the connecting portion are respectively located on the first opposite sides, wherein the convex portion and the first pole boundary region have a fifth degree, the connecting portion and the first idler The boundary is flushed to have a sixth width, and the fifth ♦ degree is substantially equal to the sixth width. &#五见 In one embodiment of the present invention, the branch of the comb portion described above - 201128277 2009-IPD-030TW 33328twf.doc/n extends beyond the first gate, and the other is completely Located in the first gate region such that the number of at least one protrusion is one. In an embodiment of the invention, the second unit of the second element includes a comb portion and a connecting portion. The comb portion surrounds the second source, and at least one of the at least two branch ' branches extends to at least one of the protrusions outside the second interpole. The connecting portion extends from the comb portion to the first gate outer portion and the protruding portion and the connecting portion are respectively located on opposite sides, wherein the protruding portion has a second degree at the same time as the second boundary, and the connecting portion and the second portion The gate boundary is tangent to have a degree substantially equal to the eighth width. The brother and the younger brother see the extension: in the case of the tenth embodiment, the branch of the above-mentioned comb-shaped portion extends beyond the first gate, and is completely located in the first region so that the number of at least one projection is One. In one embodiment of the invention, 'on the first conductor pattern. L^ Body Pattern Projection In one embodiment of the invention, the upper second is in the second conductor pattern. The L ^ plate pattern is protruded and described: the gate and the source are arranged on one side of the data line, and the other side of the conductor strip data line is corresponding to the gate and the source; . Therefore, in the production of the structure of the halogen element: the relative offset between the pole and the source: =3:: body layer does not affect the sum of the overlapping areas: that is, and Id: the capacity between the cases can compensate for mm Γ ® case pattern parasitic armor 1 pole - source parasitic capacitance change, making gate-source parasitic 201128277 2009-IPD-030TW 33328twf.doc/n Capacitance and conductor pattern - source compensation pattern parasitic capacitance stable. Therefore, the halogen matrix substrate of the present invention does not adversely affect the display effect due to the alignment error on the process. In other words, the halogen matrix substrate of the present invention has good quality and product yield. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 2A is a schematic view of a pixel array substrate according to a first embodiment of the present invention, and FIG. 2B is a schematic view of the first pixel 230a and the second pixel 230b of FIG. 2A, and FIG. 2C and FIG. 2D is a schematic cross-sectional view taken along line AA, line BB' of FIG. 2B, respectively. For convenience of description, only two halogen columns Cn, (: (4) are represented in FIG. 2A, and in FIG. 2B, the first element 23〇a and the second on both sides of the data line DL(m) are shown. Referring to FIG. 2A, in the present embodiment, the pixel array substrate 2 includes a φ substrate 20 and a plurality of first scanning lines SL1 (8), SL1 (n+l), and SL1 (n). +2) with a plurality of second scan lines SL2(nl), SL2(n), SL2(n+l), multiple pieces of resources, lines DL(ml), DL(m), DL(m+l), and more a plurality of pixels 230a, 230b, a multi/solid first compensation structure 260, and a plurality of second compensation structures 27A, wherein the scan lines SL1(n), SL1(n+l), SLl(n+2) and The two scan lines SL2(n 1)' SL2(n), SL2(n+1) extend in the column direction, and the first scan, SL1(n) and the second scan line SL2(8) are disposed in pairs on the substrate 2〇1 The first scan line SL1(n+1) and the second scan line SL2(n+1) are disposed in pairs on the substrate 2〇1, and so on. The data lines DL(ml), DL(m), DL (m+l) 201128277 2009-IPD-030TW 33328twf.doc/n extending in the row direction, and the first scan lines SL1(n), SL1(n+l), SLl(n+2), and the second scan line SL2 (nl), SL2 (8) SL2(n+l) is vertically insulated from the data lines DL(ml), DL(m), and DL(m+l). As shown in Figure 2A, the pixel column C n is located in the first pair of scans. Between the line s L1 (η) and the second scan line SL2(n), the 'cell' column cn+1 is located between the pair of first scan lines SL1(n+1) and the second scan line SL2(n+l) And the plurality of halogen elements 230a, 230b include a plurality of first halogen elements 230a and a plurality of second halogen elements 230b arranged alternately, and are located in the pair of first scan lines SL1(n), SL1(n +l), SLl(n+2) and second scan line center (4)), SL2(8), call SL2(n+l), and data lines DL(ml), DL(m), DL(m+l). In detail, the first pixel 230a and the second pixel 230b shown in FIG. 2B, FIG. 2C, and FIG. 2D are used to describe the first pixel 23a and the first scan line SL1(n) and the data line. The first side 221a of the DL (m) is connected, and the second element 230b is connected to the second side 221b of the second scan line SL2(n) and the data line DLCm). In this embodiment, the first pixel 230a includes a first active device 240 and a first pixel electrode 249, and the first active device 24 includes a first gate 242, a first semiconductor layer 244, a first source 246, and The first bungee MS. The first gate 242 is electrically connected to the first scan line su(n), the first semiconductor layer 244 is located above the first gate 242, and the first source 246 and the first drain 248 are at least partially located at the first The first source 246 is electrically connected to the data line DL(m). The first halogen electrode 2 is electrically connected to the first-pole 248 to receive the signal transmitted on the data line DL(m) by turning on or off the first active element. The second element 230b includes a second active element 25〇, and the second active element 10 201128277 2009-IPD-030TW 33328twf.doc/n 250 includes a first gate 252, a second semiconductor layer 254, a second source 256, and a second One pole 258 and the other one electrode 259. The second gate 252 is electrically connected to the second scan line SL2(n), the second semiconductor layer 254 is located above the first gate 252, and the second source 256 and the second drain 258 are at least partially located in the second semiconductor. The layer 254 and the second source 256 are electrically connected to the data line DL(m). In this embodiment, the first gate 242, the second gate 252, the first scan line SL1(n), and the second scan line SL2(n) are, for example, elements patterned by the first metal layer. The first source 246, the second source 256, the first drain 248, the second drain 258, and the data line DL(m) are, for example, elements patterned by the second metal layer. Once the patterning process of the first metal layer and the second metal layer occurs, the accuracy of the alignment is inaccurate, and the elements patterned by the two metal layers are shifted in relative positions. As a result, the overlapping area between the gates 242, 252 and the sources 246, 256 may vary to affect the element characteristics of the pixels 230a, 230b. In other words, the different gate-source parasitic capacitances of the prior art make the pixel array substrate susceptible to display brightness unevenness during display. Therefore, in order to avoid the problem of uneven display brightness, the present embodiment designs the first compensation structure 260 and the second compensation structure 27 for the first halogen 23a and the second halogen 230b in the pixel array substrate 200, respectively. The design concept is as follows. The first compensation structure 260 is located on the second side 221b of the corresponding data line DL(m). In other words, the first compensation structure 26A and the first active element 240 are located on opposite sides of the corresponding data line DL(m). The first patch structure 260 includes a conductor pattern 262, a first semiconductor pattern 201128277 2009-I-P-D-030TW 33328twf.doc/n 264, and a first source compensation pattern 266. The first conductor pattern 262 is connected to the first scan line SL1(n), the first semiconductor pattern 264 is located above the first conductor pattern 262, and the first source compensation pattern 266 is at least partially located on the second semiconductor pattern 262 and is connected to the data line DL. (m) Electrical connection. In the present embodiment, the first conductor pattern 262 is integrally formed, for example, with the first scanning line SL1 (8), and the first source compensation pattern 266 is integrally formed, for example, with the data lines 1) 1^11). Specifically, the 'first conductor pattern 262 is, for example, an element patterned by the above-described first and genus layers, and the first source compensation pattern is applied to an element patterned by the first metal layer described above. . Furthermore, in the present embodiment, the range of the region in which the first semiconductor pattern 264 is beyond the first conductor pattern 262 is taken as an example. However, in other embodiments, the first semiconductor pattern is also torn to be located in the first conductor pattern 262. Within the scope of the area.
第一補侦結構270位於所對應之資料線DL(m)的第 側22U ’換言之，第二補償結構27〇與第二主動元件^ 對應之資料線DL (m)的相對兩側。第二補償結構1 ，、、厂導體81案272、第二半導體圖案274以及第二j f】7、Γ第二導體圖案272與第二掃描線su(] V »错_ 一半一體圖案274位於第二導體圖案272上方 二—源·極補償圖案276至少部分位於第二導體圖^ 導抑t與資料線沉⑽電性連接。在本實施例中，第: 源極例如是與第二掃描線SL2⑻一體成形，第: 而丄^圖案276例如是與資料線DL(m)一體成形。星旁 的:件=體==如是由第一金屬層圖案化^ 第原極補伯圖案276例如是由第二金屬層g 12 201128277 2009-I-P-D-030TW 33328twf.doc/n 案化而成的元件。再者，在本實施例中’是以第二半導體 圖案274超出第二導體圖案272的區域範圍為例，但在其 他實施例中，第二半導體圖案274也可以位於第二導體圖 案272的區域範圍内。由圖2C與圖2D可知，晝素陣列基 板200更包括閘介電層210與保護層220，閘介電層210 形成於基板201上’其覆蓋閘極242、252、掃描線SL1 (η)、 SLl(n+l)、SLl(n+2)、SL2(n-l)、SL2⑻、SL2(n+l)以及導 體圖案262、272。保護層220形成於基板201上，覆蓋住 掃描線 SLl(n)、SLl(n+l)、SU(n+2)、SL2(n-l)、SL2⑻、 SL2(n+l)、資料線 DL(m-l)、DL(m)、DL(m+l)、主動元件 240、250、閘介電層210以及補償結構260、270。此外， 晝素電極249、259藉由保護層220中的接觸窗222、223 與汲極248、258電性連接。 假設晝素陣列基板200中各元件的相對位置應為圖 2B中貝線部伤所繪不的樣貌。不過，在圖案化的對位步驟 中發生了對位誤差而使第二金屬層在方向D上產生了偏 移’於是資料線DL(m)與源極246、256相對於閘極242、 252的位置關係以及源極補償圖案266、276相對於導體圖 案262、272實際上如虛線所繪示。也就是說，資料線 DL⑽、源極246、256、汲極248、258整體地相對間極 242、252朝向圖面的左侧，也就是方向d，平移。第一源 極246重疊於第一閘極242的面積因而增大而第—源極補 償圖案266重疊於第一導體圖案262的面積則隨之縮小。 第二源極256重疊於第二閘極252的面積因而縮小而第二 13 201128277 2009-I-P-D-030TW 33328twf.doc/n 源極補償圖案276重疊於第二導體圖案272的面積則隨之 增加。 在本實施例中’第一源極246例如具有一第一寬度 W1 ’即第一源極246與第一閘极242邊界切齊處的寬度為 W1，第一源極補償圖案266例如具有一第二寬度W2，即 第一源極補償圖案266與第一導體圖案262邊界切齊處的 寬度為W2。為了閘極-源極寄生電容與導體圖案_源極補償 圖案寄生電容的總合的恆定性，第一源極246與第一閘極 242邊界切齊處的寬度實質上等於第一源極補償圖案266 與第一導體圖案262邊界切齊處的寬度，也就是說，第一 寬度W1貫質上專於第_一寬度W2。如此一來，第—源極 246與第一閘極242的重疊面積以及第一源極補償圖案266 與第一導體圖案262的重疊面積的總合將與預定的圖案設 計相仿，甚至相同。 相似地’在本實施例中’第二源極256例如具有一第 三寬度W3，即第二源極256與第二閘極252邊界切齊處 的寬度為W3，第二源極補償圖案276例如具有—第四寬 度W4，即第二源極補償圖案276與第二導體圖案272邊 界切齊處的寬度為W4 ^為了閘極-源極寄生電容與導體圖 案-源極補償圖案寄生電容的總合的恆定性，第二源極 與第二閘極252邊界切齊處的寬度實質上等於第二源極補 償圖案276與第二導體圖案272邊界切齊處的寬度'，'也^ 是說’第三寬度W3實質上等於第四寬度^/4。如^—來\ 第二源極256與第二閘極252的重疊面積以及第二源極補 14 201128277 2009-1-P-D-030TW 33328twf.doc/n 償圖案276與第二·導體圖案272的重疊 定的圖案設計相仿，甚至相同。 、.心口將與預 藉這樣的圖案設計，本實施例可以維持 200的品質。即使製程對位精準产 皁列基板 下，晝素陣列基板2G0仍具有預設的品f。^^提的^形 當製程步驟中的對位偏移是背離方向D時，第、^ 260以及第二補償結構270的設計仍有助 貝= 第-掃描線上總的電阻-電容效應(R_C， 描線上總的電阻電容效雜_c effeet)值是相同的 之，本實施例的設計可以避免製程在平行或背離方向D ^ 產生對位偏移時對元件特性所造成的負面影響而使晝 列基板200具有相當不錯的品質及良率。 值得-提的是，第-導體圖案262與第二導體圖案奶 在平行方向D上的長度較佳是大於或至少等於圖案 中對位步驟可能產生的誤差。如此—來，對位步驟的誤差 使閘極242、252與源極246、祝在平行方向D或背離方 向D上所魅驗移射趨得補償料致造成晝素陣列 基板200的不良情形。另外，在對位誤差之下，本實施例 的第-源極補償圖案266與第二源極補償圖案276例如不 凸出於第一導體圖案遍肖第二導體圖案272之外以確保 能補償間極-源極寄生電容的改變。再者，雖然本實施例是 以條狀的源極246為例，但如圖3A與圖3B所示，在晝素 陣列基板200a中，源極246也可以具有馬蹄形結構。其中， 15 201128277 2009-I-P-D-030TW 33328twf.doc/n 晝素陣列基板2〇Ga的構成元件實質上與晝麟列基板2〇〇 相同且以相同標示表示，因此於此不贅述。 -般來說，在具有㈣極設計的晝料聽板中，由 於是以同-條資料線對兩側的晝素輪人訊號，因此當第一 導體層與第二導體狀生相對偏料，位於同-條資 側的晝素在閘極_源極寄生電容上會產生相反的 舉例來說，位於奇數行之畫素結制閘極-源極 一起變大’而位於偶數行之晝素結構的閘極- 生電容會—起變小，反之亦然。如此-來，顯示書 =心之產生對應的變化，使得顯示畫面上的缺陷會更力—口 刊顯。 極24^9在本實施财，在資料線DL⑽的—侧配置閘 : 52 *源極246、256，以及在同一條掃描 ίΓ 與閘極242、252及源極246、况相對應的 =^62、272與源極補償圖案施、頂。因= 相對偏移並不層與第二導體層之間的 源極補償圖ΐ 與閘極242之間的重疊面積及 補案266與導體圖案262之 合，以及源極256盥閘極252 $ + f " 圖案276 _體圖幸7^^之間的重疊面積及源極補償 閘椏^f _案_重疊面積的總合。亦即， 她人與導體補償《寄生電容的 ϋ ί Ϊ二。也就是說’導體__源_償圖案寄生電 電人^極~源極寄生電容的變化，使掃描線上的寄生 5為恒疋的。此外，由於掃描線的訊號傳輸品質與 16 201128277 2009-I-P-D-030TW 33328twf.d〇c/n 電，-電容效應(R-Ceffect)相關，因此在能使掃描線的寄生 電容維持一致的狀況下，掃描線能維持一致的RC值，故 晝素陣列基板具有較佳的顯示品質。因此，本發明的晝素 陣列基板不因製程上的對位誤差而對顯示效果產生負面影The first complement structure 270 is located on the first side 22U of the corresponding data line DL(m), in other words, the second compensation structure 27 is opposite to the opposite sides of the data line DL(m) corresponding to the second active element ^. The second compensation structure 1, the factory conductor 81 case 272, the second semiconductor pattern 274 and the second jf] 7, the second conductive pattern 272 and the second scan line su (] V » wrong _ half integrated pattern 274 is located at The second source-pole compensation pattern 276 is electrically connected to the data line sink (10) at least partially in the second conductor pattern 272. In this embodiment, the: source is, for example, the second scan line. The SL2 (8) is integrally formed, and the : ^ pattern 276 is formed integrally with the data line DL (m), for example, by the side of the star: the body = = if the pattern is formed by the first metal layer ^ the first pole complement pattern 276 is, for example, An element formed by the second metal layer g 12 201128277 2009-IPD-030TW 33328 twf.doc/n. Further, in the present embodiment, 'is a region in which the second semiconductor pattern 274 extends beyond the second conductor pattern 272. For example, in other embodiments, the second semiconductor pattern 274 may also be located in the region of the second conductor pattern 272. As can be seen from FIG. 2C and FIG. 2D, the pixel array substrate 200 further includes a gate dielectric layer 210 and protection. The layer 220, the gate dielectric layer 210 is formed on the substrate 201, which covers the gate 242, 252, scan lines SL1 (η), SL1 (n+1), SL1 (n+2), SL2 (nl), SL2 (8), SL2 (n+1), and conductor patterns 262, 272. The protective layer 220 is formed on the substrate 201. Upper, covering scan lines SL1(n), SL1(n+l), SU(n+2), SL2(nl), SL2(8), SL2(n+l), data lines DL(ml), DL(m) DL(m+l), active device 240, 250, gate dielectric layer 210, and compensation structures 260, 270. In addition, the pixel electrodes 249, 259 are contacted by the contact windows 222, 223 and the drain 248 in the protective layer 220. 258 is electrically connected. It is assumed that the relative positions of the elements in the pixel array substrate 200 should be the same as those depicted in the shell line of Fig. 2B. However, a misalignment error occurs in the patterned alignment step. The second metal layer is offset in the direction D so that the positional relationship of the data line DL(m) with the source electrodes 246, 256 with respect to the gates 242, 252 and the source compensation patterns 266, 276 with respect to the conductor pattern 262 272 is actually drawn as a dotted line. That is, the data line DL (10), the source 246, 256, the drain 248, 258 are integrally opposite to the left side of the plane 242, 252 toward the left side of the drawing, that is, the direction d, translation The first source is 246 heavy The area of the first gate 242 is thus increased, and the area of the first source compensation pattern 266 overlapping the first conductor pattern 262 is reduced. The area of the second source 256 overlapping the second gate 252 is thus reduced. Second 13 201128277 2009-IPD-030TW 33328twf.doc/n The area of the source compensation pattern 276 overlapping the second conductor pattern 272 is increased. In the present embodiment, the first source 246 has a first width W1, that is, the width of the first source 246 at the boundary of the first gate 242 is W1, and the first source compensation pattern 266 has, for example, a The second width W2, that is, the width at which the first source compensation pattern 266 is aligned with the boundary of the first conductor pattern 262 is W2. For the consistency of the sum of the gate-source parasitic capacitance and the conductor pattern_source compensation pattern parasitic capacitance, the width of the first source 246 at the boundary with the first gate 242 is substantially equal to the first source compensation. The width of the pattern 266 at the boundary with the first conductor pattern 262, that is, the first width W1 is qualitatively specific to the first width W2. As such, the overlapping area of the first source 246 and the first gate 242 and the overlapping area of the first source compensation pattern 266 and the first conductor pattern 262 will be similar or even the same as the predetermined pattern design. Similarly, in the present embodiment, the second source 256 has a third width W3, that is, a width W3 at the boundary between the second source 256 and the second gate 252, and the second source compensation pattern 276. For example, having a fourth width W4, that is, a width at which the second source compensation pattern 276 is flush with the boundary of the second conductor pattern 272 is W4 ^ for the gate-source parasitic capacitance and the conductor pattern-source compensation pattern parasitic capacitance. For the consistency of the sum, the width at which the second source is aligned with the boundary of the second gate 252 is substantially equal to the width at which the second source compensation pattern 276 is aligned with the boundary of the second conductor pattern 272, 'also Say 'the third width W3 is substantially equal to the fourth width ^/4. For example, the overlap area of the second source 256 and the second gate 252 and the second source complement 14 201128277 2009-1-PD-030TW 33328 twf.doc/n compensation pattern 276 and the second conductor pattern 272 The overlapping patterns are similar, even the same. , the heart will be designed with such a pattern, and this embodiment can maintain the quality of 200. The halogen array substrate 2G0 still has a preset product f even under the process alignment precision soap column substrate. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The value of the total resistance-capacitance _c effeet) on the trace is the same. The design of this embodiment can avoid the negative influence of the process on the characteristics of the component when the alignment shifts in parallel or away from the direction D ^. The array substrate 200 has a fairly good quality and yield. It is worth mentioning that the length of the first conductor pattern 262 and the second conductor pattern milk in the parallel direction D is preferably greater than or at least equal to the error that may occur in the alignment step in the pattern. As such, the error in the alignment step causes the gates 242, 252 and the source 246 to be moved in the parallel direction D or away from the direction D to cause the compensation material to cause a defect in the pixel array substrate 200. In addition, under the alignment error, the first source compensation pattern 266 and the second source compensation pattern 276 of the present embodiment are not protruded from the first conductor pattern, for example, beyond the second conductor pattern 272 to ensure compensation. The change of the interpole-source parasitic capacitance. Further, although the present embodiment is exemplified by strip-shaped source electrodes 246, as shown in Figs. 3A and 3B, in the pixel array substrate 200a, the source electrode 246 may have a horseshoe-shaped structure. Here, 15 201128277 2009-I-P-D-030TW 33328twf.doc/n The constituent elements of the halogen matrix substrate 2〇Ga are substantially the same as the unicorn column substrate 2A and are denoted by the same reference numerals, and thus will not be described herein. Generally speaking, in the tanning plate with the (four) pole design, since the same signal is on the opposite side of the data line, the first conductor layer and the second conductor are relatively biased. The singular elements on the same-source side will have the opposite on the gate-source parasitic capacitance. For example, the odd-numbered gate-sources of the odd-numbered rows become larger together and are located after the even-numbered rows. The gate-to-cell capacitance of the prime structure will become smaller and vice versa. In this way, the display book = the corresponding change in the heart, so that the defects on the display screen will be more powerful. In this implementation, the gate is disposed on the side of the data line DL (10): 52 * source 246, 256, and in the same scanning Γ 闸 闸 242, 252 and source 246, the corresponding = ^ 62, 272 and source compensation pattern application, top. Because the relative offset is not the source compensation map between the layer and the second conductor layer and the overlap area between the gate 242 and the complement 266 and the conductor pattern 262, and the source 256 盥 gate 252 $ + f " Pattern 276 _ Body image fortunately between 7^^ overlap area and source compensation gate 桠^f _ case _ overlap area sum. That is, she and the conductor compensate for the parasitic capacitance ϋ Ϊ Ϊ 。. That is to say, the 'conductor__source_compensation pattern parasitic electric-electrode-source parasitic capacitance changes, so that the parasitic 5 on the scanning line is constant. In addition, since the signal transmission quality of the scanning line is related to the electric-capacitance effect (R-Ceffect), the parasitic capacitance of the scanning line can be kept consistent. The scan line can maintain a consistent RC value, so the halogen array substrate has better display quality. Therefore, the halogen array substrate of the present invention does not adversely affect the display effect due to the alignment error on the process.
響。換言之，本發明的晝素陣列基板具有良好的品質以及 產品良率D 一土圖4A為本發明之第二實施例之一種晝素陣列基板的 • 不意圖，圖4B為圖4A之第一晝素230a與第二晝素230b 的不意圖。為了說明方便，圖4A中僅繪示兩個晝素列cn、 Cn+i作為代表，且在圖4B中以位於資料線DL(m)之兩側 的第一晝素230a與第二晝素230b來進行說明。請參照圖 4A，晝素陣列基板300的構成元件實質上與晝素陣列基板 2〇〇相同，因此畫素陣列基板3〇〇與晝素陣列基板2〇〇相 同的元件將以相同的元件符號標示。簡言之，晝素陣列基 板300包括基板3〇1、多條第一掃描線su(n)、su(n+1)、 SLl(n+2)與多條第二掃描線 SL2(n-l)、SL2(n)、SL2(n+l)、 夕條資料線DL(m-l)、DL(m)、DL(m+l)、多個晝素230a、 230b、多個第一補償結構26〇以及多個第二補償結構27〇。 特別注意到的是，晝素陣列基板300與畫素陣列基板2〇〇 的不同之處在於汲極248a、258a的圖案設計，以下將針對 汲極248a、258a的圖案設計進行說明。 請參照圖4B，在本實施例中，汲極248a、258a包括 環繞源極246、256的梳型部310以及一連接部314。舉 例而δ，梳型部310具有一第一分支31〇a、一第二分支3l〇b 17 201128277 2009-I-P-D-030TW 33328twf.doc/n 以及一條狀底部310c。也就是說，梳型部31〇可以為UB 圖案’不過梳型部310也可以具有三個或三個以上數目的 分支，即梳型部310可以具有兩個分支，也可以具有兩個 或兩個以上的分支。第一分支310a與第二分支31〇b例如 由條狀底部310c的兩端沿水平方向凸出以使梳型部31〇 圍繞源極246、256。連接部314的一端連接至條狀底部 310c’另一端則沿水平方向凸出於閘極242、252之外，因 此’連接部314會與閘極242、252部分重疊。 在本實施例中，梳型部310與連接部314實質上構成 一叉狀圖案。也就是說，梳型部31〇的底部連接一長條狀 的連接部314可構成一如叉子狀的圖形。另外，連接部314 具有接觸。卩316，接觸部316位於連接部314遠離梳型 部310的一端，且晝素電極249、259通過接觸部316以電 性連接至>及極248a、258a。由於晝素電極249、259與接 觸部316連接的方式是本領域中常用的技術，因此本實施 例不再另作說明。 值知一k的是，苐一分支310a延伸至閘極242、252 之外以定義出位於閘極242、252外的一凸出部312，且凸 出部312與第一分支31〇a之未延伸至閘極242、252之外 的部分具有相同寬度。同時，在這樣的圖案設計下，凸出 部312與連接部314分別位於閘極242、252的相對兩侧。 假设畫素陣列基板300中各元件的相對位置應為圖4B中 實線部份所繪示的樣貌。不過，在圖案化的對位步驟中發 生了對位誤差而使第二金屬層在方向〇上產生了偏移，於 201128277 2009-I-P-D-030TW 33328twf.doc/n 是資料線DL(m)、源極246、256以及没極248a、258a相 對於閘極242、252的位置關係實際上如虛線所繪示。也就 是說’資料線DL(m)、源極246、256、沒極248a、258a 整體地相對閘極242、252朝向圖面的左侧，也就是方向 D，平移。如第一實施例中所述’第一補償結構26〇以及 第一補償結構270的設計有助於補償閘極-源極寄生電容 的改變，使閘極-源極寄生電容與導體圖案-源極補償圖案 φ 寄生電容的總合維持恆定。 此外’在本實施例之第一晝素230a中，第一分支31〇a 重疊於閘極242的面積因而增大而連接部314重疊於閘極 242的面積則隨之縮小。也就是說，凸出部的面積在 對位誤差下被縮小了。相反地，在第二晝素23〇b中，第一 分支310a重疊於閘極252的面積因而縮小而連接部314 重疊於閘極252的面積則隨之增大。也就是說，凸出部312 的面積在對位誤差下被增大了。 • 在本貫施例之汲極248a中，第一分支3i〇a例如具有 一第五寬度W5，即凸出部312與閘極242邊界切齊處的 寬度為W5 ’第二分支31〇b例如具有一第六寬度w6 ,而 連接部314例如具有一第七寬度W7，即連接部314與閘 極242邊界切齊處的寬度為W7，其中位於閘極242相對 兩側的凸出部312與連接部314都分別由閘極242所在位 置凸出於閘極242之外。因此，為了使第一晝素23〇a之閘 極-汲極寄生電容的恒定性，凸出部3丨2與閘極2犯邊界切 4處的覓度μ質上等於連接部314與閘極242邊界切齊處 19 201128277 2009-1-P-D-030TW 33328twf.doc/n 的寬度，也就是說，第五寬度W5實質上等於第七寬度 W7。如此一來，、及極248a與閘極242的重疊面積將與預 定的圖案設計相仿’甚至相同以達到閘極-汲極寄生電容的 恒定。 本實施例之汲極258a中，第一分支3l〇a例如具有— 第八寬度W8，即凸出部312與閘極2 52邊界切齊處的寬 度為W8，第二分支310b例如具有一第九寬度W9，而連 接部314例如具有一第十寬度W10，即連接部314與閘極 252邊界切齊處的寬度為W10 ’其中位於閘極252相對兩 側的凸出部312與連接部314都分別由閘極252所在位置 凸出於閘極252之外。因此，為了使第二晝素23〇b之閘極 -没極寄生電容的恒定性，凸出部312與閘極252邊界切齊 處的寬度實質上等於連接部314與閘極252邊界切齊處的 寬度，也就是說，第八寬度W8實質上等於第十寬度wl〇。 如此一來’汲·極258a與閘極252的重疊面積將與預定的圖 案δ又计相仿’甚至相同以達到閘極_没極寄生電容的恒定。 洋吕之，梳型部310以及連接部314為一體成型的圖 案。所以’梳型部310以及連接部314相對於閘極242、 252的位移量是相同的。因此，第五寬度W5等於第七寬 度W7可使汲極248a與閘極242的重疊面積與預定的圖案 設計相仿而維持閘極二汲極寄生電容恒定性，以及第八寬度 W8等於第十寬度W10可使汲極248b與閘極252的重疊 面積與預疋的圖案設計相仿而維持閘極_没極寄生電容恒 定性。 20 201128277 ^^-x-r-D-OSOTW 33328twf.d〇c/n 土^件的疋，凸出部312在平行方向d上的長度較 仏疋大於或至対於圖案化餘巾對位步驟可能產生的誤 差。如此一來，對位步驟的誤差使閘極242、252與汲極 漁、、25如在平行方向D或背離方向D上所產生的位移 都可以獲得補償而不致造成晝素陣列基板·的不良情 开y ，外，在對位誤差之下，本實施例的第二分支31〇b 例=疋不凸出於閘極242、252之外以確保閑極_汲極寄生 •.電容的恆定。當然，本實施例僅是一種實施方式的說明， 為了維持閘極-汲極寄生電容的恒定性，還可以應用多種晝 素結構設計。這些晝素結構的設計主要是使相對於間極兩 側的凸出部與連接部在寬度上具有相等或相仿的數值以使 晝素陣列基板具有理想的品質。舉例來說，在一實施例中， 汲極248a、258a的第一分支310a與第二分支3丨0b皆突出 =閘極242、252之外，且第一分支3丨〇a的寬度W5、W8、 第二分支310b的寬度W6、W9與連接部314的寬度W7、 W10例如符合寬度W5與寬度W6的總和實質上等於寬度 鲁 W7的關係以及寬度W8與寬度W9的總和實質上等於寬度 W10的關係。再者，順帶一提的是，為了維持閘極-汲極寄 生電各的恒定性，在本實施例中是將汲極的第一分支31〇a 與第二分支310b設計成長度不同且第一分支31〇a凸出於 閘極242、252，但是本發明之補償結構的設計也適用於汲 極的弟一分支與第二分支的長度相同且皆未凸出於閘極的 晝素結構中。 在本貫施例中，第一補償結構260與第二補償結構270 21 -030TW 33328twf.doc/n 201128277 $補償•源極寄生電容的改變，以轉掃描線之寄生電 容總合的蚊’而汲極248a、2撕的圖案設計能進一步維 ，閘極1極寄生電容恒定性。因此本實施例可以維持畫素 陣=基板300的品質。即使製程對位精準度並非十分理想 的形下’晝素陣列基板3〇〇仍具有預設的品質。簡古之， 本實施例的設計可以避免製程在平行或舞方向D上。產生 對位偏移時對元件特性所造成的貞面影響岐 板:具有相當不錯的品質及良率。此外，由騎描線的 狀值與__源_生電敍陳雜衫電容相關，因 補，姻寄生電容之改變及維持閘極-汲極寄 -致狀態下，晝素陣列基板3〇0之掃描線能具有 ’使晝素陣列基板300具有較佳的顯示晝面。 、，好^上所述’本發明在資料線的—側配置閘極及源極， 另—側配置與間極及源極相對應的 中I:;:補償圖案。因此’在製作晝素結構的過程 減第二導體層之間的相對偏移並不影響閘 的重面積及導體圖案與源極補償圖案之間 面積的總合。亦即’導體圖案-源極補償圖案寄生電 ΐ容源極寄生電容的變化，使閘極·源極寄生 l 源極補償圖案寄生電容的總合為恒定 而a ’本發明的晝素陣列基板不因製程上的對位誤差 果有負面的影響。換言之’本發明的晝素陣列 基板具有良好的品質以及產品良率。 此外’本發明之晝素陣列基板的設計可以與其他能維 22 201128277 .v,U7-i-r>-D-030TW 33328twf.doc/n 持閘極-汲極寄生電容恆定的晝素結構結合，使晝素陣列基 板的閘極-源極寄生電容及閘極_汲極寄生電容皆維持 定。如此—來，可以進一步使掃描線的RC值保持一致， 進而使晝素陣列基板具有較佳的顯示晝面。 隹本發明已以貫施例揭露如上，然其並非用以限定 ^明，任何所屬技術領域中具有通常知識者，在不脫離 ^明之精神和範_ ’當可作些許之更誠潤飾，故本 • X明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知之一種晝素陣列基板的示意圖。 示意=。2八為本發明之第—實施例之一種晝素陣列基板的 圖2Β為圖2Α之第一晝素與第二晝素的示意圖。 立,丨而圖^與圖2D *別為沿圖2Β之Α_Α，線與Β-Β，線的 刮面不意圖。 · 春亍立^ 3Α為本發明之另—實施例之一種晝素陣列基板的 不思圍。 為圖3Α之第—晝素與第二晝素的示意圖。 示音。4八為本發明之第二實施例之一種晝素陣列基板的 圖4Β為圖3Α之第一晝素與第二晝素的示意圖。 23 201128277 /.uuy-i-r-i^-030TW 33328twf.doc/n 【主要元件符號說明】 100、200、200a、300 :晝素陣列基板 130a、130b、230a、230b :晝素 110a、110b、SL1 ⑻、SLl(n+l)、SLl(n+2)、SL2(n-l)、 SL2(n)、SL2(n+l):掃描線 120、DL(m-l)、DL(m)、DL(m+l):資料線 140、150、240、250 :主動元件 142、152、242、252 :閘極 144、154、246、256 :源極 # 146、156、248、248a、258、258a :汲極 201、301 :基板 210:閘介電層 220 :保護層 221a、221b :側 222、223 :接觸窗 244、254 :半導體層 249、259 :晝素電極 260、270 :補償結構 262、272 :導體圖案 264、274 :半導體圖案 266、276 :源極補償圖案 310 :梳型部 310a、310b :分支 310c ·條狀底部 24 201128277 zuuy-i-r-D-030TW 33328twf.doc/n 312 :凸出部 314 :連接部 316 :接觸部 Cn、Cn+i :晝素列 D :方向 W1〜W10 :寬度ring. In other words, the halogen matrix substrate of the present invention has good quality and product yield D. FIG. 4A is a schematic diagram of a halogen matrix substrate according to a second embodiment of the present invention, and FIG. 4B is the first layer of FIG. 4A. The intention of the prime 230a and the second halogen 230b. For convenience of explanation, only two halogen columns cn, Cn+i are represented in FIG. 4A, and in FIG. 4B, the first halogen 230a and the second halogen are located on both sides of the data line DL(m). 230b for explanation. Referring to FIG. 4A, the constituent elements of the pixel array substrate 300 are substantially the same as the pixel array substrate 2, so that the same elements of the pixel array substrate 3 and the pixel array substrate 2 will have the same component symbols. Marked. In short, the halogen array substrate 300 includes a substrate 3〇1, a plurality of first scan lines su(n), su(n+1), SL1(n+2), and a plurality of second scan lines SL2(nl). , SL2(n), SL2(n+l), TIME data line DL(ml), DL(m), DL(m+l), a plurality of elements 230a, 230b, and a plurality of first compensation structures 26〇 And a plurality of second compensation structures 27〇. It is particularly noted that the pixel array substrate 300 differs from the pixel array substrate 2A in the pattern design of the gate electrodes 248a, 258a, and the pattern design of the gate electrodes 248a, 258a will be described below. Referring to FIG. 4B, in the present embodiment, the drains 248a, 258a include a comb portion 310 surrounding the source electrodes 246, 256 and a connecting portion 314. For example, δ, comb portion 310 has a first branch 31〇a, a second branch 3l〇b 17 201128277 2009-I-P-D-030TW 33328twf.doc/n, and a strip bottom 310c. That is, the comb portion 31A may be a UB pattern 'but the comb portion 310 may have three or more branches, that is, the comb portion 310 may have two branches, or may have two or two More than one branch. The first branch 310a and the second branch 31〇b are, for example, protruded in the horizontal direction from both ends of the strip-shaped bottom portion 310c so that the comb portion 31〇 surrounds the source portions 246, 256. One end of the connecting portion 314 is connected to the strip bottom portion 310c' and the other end protrudes out of the gate electrodes 242, 252 in the horizontal direction, so that the connecting portion 314 partially overlaps the gate electrodes 242, 252. In the present embodiment, the comb portion 310 and the connecting portion 314 substantially constitute a fork pattern. That is, the bottom of the comb portion 31A is connected to a long connecting portion 314 to form a fork-like pattern. In addition, the connecting portion 314 has a contact.卩316, the contact portion 316 is located at one end of the connecting portion 314 away from the comb portion 310, and the halogen electrodes 249, 259 are electrically connected to the > and the poles 248a, 258a through the contact portion 316. Since the manner in which the halogen electrodes 249, 259 are connected to the contact portion 316 is a technique commonly used in the art, the present embodiment will not be further described. The value of a k is that the first branch 310a extends beyond the gates 242, 252 to define a projection 312 located outside the gates 242, 252, and the projections 312 and the first branches 31a Portions that do not extend beyond the gates 242, 252 have the same width. At the same time, in such a pattern design, the projections 312 and the connecting portions 314 are located on opposite sides of the gates 242, 252, respectively. It is assumed that the relative positions of the elements in the pixel array substrate 300 should be as shown in the solid line portion of Fig. 4B. However, a registration error occurs in the patterned alignment step and the second metal layer is shifted in the direction ,. In 201128277 2009-IPD-030TW 33328twf.doc/n is the data line DL(m), The positional relationship of the sources 246, 256 and the poles 248a, 258a with respect to the gates 242, 252 is actually depicted as a dashed line. That is to say, the data line DL (m), the source 246, 256, and the poles 248a, 258a are integrally oriented with respect to the left side of the plane 242, 252 toward the left side of the drawing, that is, the direction D, translation. The design of the 'first compensation structure 26' and the first compensation structure 270 as described in the first embodiment helps to compensate for the change of the gate-source parasitic capacitance, so that the gate-source parasitic capacitance and the conductor pattern-source The sum of the parasitic capacitances of the pole compensation pattern φ is kept constant. Further, in the first pixel 230a of the present embodiment, the area in which the first branch 31〇a overlaps the gate 242 is thus increased, and the area in which the connection portion 314 is overlapped with the gate 242 is reduced. That is, the area of the projection is reduced by the alignment error. Conversely, in the second element 23〇b, the area of the first branch 310a overlapping the gate 252 is thus reduced, and the area of the connection portion 314 overlapping the gate 252 is increased. That is, the area of the projection 312 is increased under the alignment error. • In the drain 248a of the present embodiment, the first branch 3i〇a has, for example, a fifth width W5, that is, the width of the convex portion 312 at the boundary with the gate 242 is W5 'the second branch 31〇b For example, it has a sixth width w6, and the connecting portion 314 has a seventh width W7, for example, a width W7 at which the connecting portion 314 is aligned with the boundary of the gate 242, wherein the protruding portion 312 is located on opposite sides of the gate 242. Both the connection portion 314 and the connection portion 314 protrude from the position of the gate 242 outside the gate 242. Therefore, in order to make the gate-drain parasitic capacitance of the first halogen 23〇a constant, the curvature of the protrusion 3丨2 and the gate 2 is 4, which is equal to the connection portion 314 and the gate. The width of the pole 242 boundary is 19 201128277 2009-1-PD-030TW 33328twf.doc / n, that is, the fifth width W5 is substantially equal to the seventh width W7. As a result, the overlap area of the pole 248a and the gate 242 will be similar to the predetermined pattern design, or even the same, to achieve a constant gate-drain parasitic capacitance. In the drain 258a of the present embodiment, the first branch 31a has, for example, an eighth width W8, that is, the width of the convex portion 312 and the boundary of the gate 2 52 is W8, and the second branch 310b has a first Nine width W9, and the connecting portion 314 has, for example, a tenth width W10, that is, the width of the connecting portion 314 at the boundary with the gate 252 is W10', wherein the protruding portion 312 and the connecting portion 314 are located on opposite sides of the gate 252. They are all protruded from the position of the gate 252 outside the gate 252. Therefore, in order to make the gate-to-pole parasitic capacitance of the second halogen 23〇b constant, the width of the convex portion 312 and the gate 252 are substantially equal to the boundary of the connection portion 314 and the gate 252. The width at which it is, that is, the eighth width W8 is substantially equal to the tenth width w1〇. As a result, the overlap area of the gate 258a and the gate 252 will be similar to that of the predetermined pattern δ to achieve a constant gate-to-pole parasitic capacitance. The foreign part, the comb portion 310 and the connecting portion 314 are integrally formed patterns. Therefore, the amount of displacement of the comb portion 310 and the connecting portion 314 with respect to the gates 242, 252 is the same. Therefore, the fifth width W5 is equal to the seventh width W7 such that the overlapping area of the drain 248a and the gate 242 is similar to the predetermined pattern design to maintain the gate-drain parasitic capacitance constancy, and the eighth width W8 is equal to the tenth width. W10 allows the overlap area of the drain 248b and the gate 252 to be similar to the premature pattern design to maintain gate-to-pole parasitic capacitance constancy. 20 201128277 ^^-xrD-OSOTW 33328twf.d〇c/n The 疋 of the soil member, the length of the projection 312 in the parallel direction d is greater than or equal to that which may be produced by the patterning waste alignment step. error. In this way, the error of the alignment step can compensate for the displacements generated by the gates 242, 252 and the gates, such as in the parallel direction D or the deviation direction D, without causing defects in the pixel array substrate. In addition, under the alignment error, the second branch 31〇b of the present embodiment = 疋 does not protrude beyond the gates 242, 252 to ensure the idle pole _ 汲 parasit. . Of course, this embodiment is merely an illustration of an embodiment. In order to maintain the constancy of the gate-drain parasitic capacitance, various pixel structure designs can also be applied. The design of these halogen structures is mainly such that the projections and the joints on both sides of the interpole have equal or similar values in width so that the halogen array substrate has a desired quality. For example, in one embodiment, the first branch 310a and the second branch 3丨0b of the drain 248a, 258a both protrude = outside the gate 242, 252, and the width W5 of the first branch 3丨〇a, W8, the widths W6, W9 of the second branch 310b and the widths W7, W10 of the connecting portion 314, for example, the sum of the width W5 and the width W6 is substantially equal to the relationship of the width Lu W7 and the sum of the width W8 and the width W9 is substantially equal to the width W10 Relationship. Furthermore, in order to maintain the constancy of the gate-drain parasitic power, in the present embodiment, the first branch 31〇a and the second branch 310b of the drain are designed to have different lengths and A branch 31〇a protrudes from the gates 242, 252, but the design of the compensation structure of the present invention is also applicable to a monolithic structure in which the length of the dipole and the second branch are the same and the gates are not protruded from the gate. in. In the present embodiment, the first compensation structure 260 and the second compensation structure 270 21 -030TW 33328twf.doc/n 201128277 $compensate the source parasitic capacitance change to the parasitic capacitance of the scan line summed with the mosquito' The pattern design of the bungee 248a and 2 tearing can further maintain the stability of the parasitic capacitance of the gate. Therefore, this embodiment can maintain the quality of the pixel matrix = substrate 300. Even if the process alignment accuracy is not very satisfactory, the 昼 阵列 array substrate 3 〇〇 still has a preset quality. Jane, the design of this embodiment can avoid the process in parallel or dance direction D. The resulting surface impact on the component characteristics caused by the offset of the alignment plate: has a very good quality and yield. In addition, the shape value of the riding line is related to the capacitance of the __source_sheng electric 陈 杂 , , , , , , , , , , 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因The scan line can have 'having a better display surface for the pixel array substrate 300. In the present invention, the gate and the source are disposed on the side of the data line, and the other side is disposed in the middle I:;: compensation pattern corresponding to the interpole and the source. Therefore, the process of fabricating the unitary structure minus the relative offset between the second conductor layers does not affect the sum of the area of the gate and the area between the conductor pattern and the source compensation pattern. That is, the change of the parasitic capacitance of the parasitic electric capacitance source of the conductor pattern-source compensation pattern makes the sum of the parasitic capacitances of the gate/source parasitic source compensation pattern constant and a 'the alizanic array substrate of the present invention It does not have a negative impact on the alignment error on the process. In other words, the halogen matrix substrate of the present invention has good quality and product yield. In addition, the design of the halogen array substrate of the present invention can be combined with other energy structure 22 201128277 .v, U7-i-r>-D-030TW 33328twf.doc/n with a gate-drain parasitic capacitance constant. The gate-source parasitic capacitance and the gate-drain parasitic capacitance of the halogen array substrate are maintained. In this way, the RC values of the scan lines can be further kept consistent, thereby further providing a better display surface for the pixel array substrate. The present invention has been disclosed in the above embodiments, but it is not intended to be limiting, and any person having ordinary knowledge in the technical field may not be divorced from the spirit and scope of the invention. • The scope of protection of X Ming is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional halogen matrix substrate. Signal =. 2 is a schematic diagram of a halogen matrix substrate according to a first embodiment of the present invention. FIG. 2 is a schematic view of the first and second halogen elements of FIG.立,丨 and the picture ^ and Figure 2D * Do not follow the figure Β Α Α 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线· 春亍立^3Α is another embodiment of the present invention. It is a schematic diagram of the first and second elements of Figure 3. Sound. 4 is a schematic diagram of a halogen matrix substrate according to a second embodiment of the present invention. FIG. 4 is a schematic view of the first and second halogen elements of FIG. 23 201128277 /.uuy-iri^-030TW 33328twf.doc/n [Description of main component symbols] 100, 200, 200a, 300: Alizarin array substrates 130a, 130b, 230a, 230b: Alizarins 110a, 110b, SL1 (8), SLl(n+l), SLl(n+2), SL2(nl), SL2(n), SL2(n+l): scan line 120, DL(ml), DL(m), DL(m+l) ): data lines 140, 150, 240, 250: active elements 142, 152, 242, 252: gates 144, 154, 246, 256: source # 146, 156, 248, 248a, 258, 258a: bungee 201 301: substrate 210: gate dielectric layer 220: protective layers 221a, 221b: sides 222, 223: contact windows 244, 254: semiconductor layers 249, 259: germanium electrodes 260, 270: compensation structures 262, 272: conductor patterns 264, 274: semiconductor pattern 266, 276: source compensation pattern 310: comb portion 310a, 310b: branch 310c - strip bottom 24 201128277 zuuy-irD-030TW 33328twf.doc/n 312: projection 314: connection portion 316: contact portion Cn, Cn+i: halogen column D: direction W1 to W10: width