TW202004715A - Pixel structure and manufacturing method thereof - Google Patents

Abstract

A pixel structure according to embodiments of the present disclosure includes first and second conductive layers, inter-electrode insulating pattern and oxide-semiconductor pattern. The first conductive layer is disposed on a substrate, and includes a data line, a first gate line and a pixel electrode. The data line and the first gate line respectively extend along first and second directions. The pixel electrode has an active region opening defining an active region. The inter-electrode insulating pattern covers the first conductive layer. The second conductive layer is disposed on the inter-electrode insulating pattern, and includes a second gate line and a gate pattern. The second gate line extends along the second direction, and is connected with the first gate line in parallel. The gate pattern extends into the active region from the second gate line. The oxide-semiconductor pattern covers the gate pattern, and is electrically connected with the data line and the pixel electrode.

Description

Pixel structure and its manufacturing method

The invention relates to a pixel structure and a manufacturing method thereof.

In recent years, flat display panels with superior characteristics such as low power, good space utilization efficiency, no radiation, and high image quality have gradually become mainstream displays. Common flat displays include liquid crystal displays, plasma displays, and organic electroluminescent displays.

Flat display panels mostly use thin film transistors as the switching elements of each pixel structure, and the performance of the switching elements depends on the characteristics of the active layer in the thin film transistors. Currently widely used active layers include amorphous silicon and low-temperature polysilicon. Amorphous silicon has problems of low carrier mobility and low opening rate. The disadvantage of low-temperature polysilicon is that the manufacturing process is complicated, the yield is low, and the leakage of the thin film transistor is increased.

The invention provides a pixel structure and a manufacturing method thereof, which can improve the switching characteristics of the thin film transistor and can prevent the gate line from being broken.

The pixel structure of the embodiment of the present invention includes a first conductive layer, an inter-electrode insulating pattern, a second conductive layer, and an oxide semiconductor pattern. The first conductive layer is disposed on the substrate and includes a data line, a first gate line, and a pixel electrode. The data line extends in the first direction. The first gate line extends in the second direction. The pixel electrode has an active area opening defining an active area. The data line, the first gate line and the pixel electrode surround the active area. The inter-electrode insulating pattern is provided on the substrate and covers the first conductive layer. The second conductive layer is disposed on the insulating pattern between the electrodes, and includes a second gate line and a gate pattern. The second gate line extends along the second direction and is parallel to the first gate line. The gate pattern extends from the second gate line into the active area. The oxide semiconductor pattern is disposed in the active area and covers the gate pattern. The oxide semiconductor pattern is electrically connected to the data line and the pixel electrode.

In an embodiment of the invention, the material of the oxide semiconductor pattern includes zinc oxide, tin oxide, tin-zinc oxide, aluminum-zinc oxide, zinc-magnesium oxide, tin-magnesium oxide, Indium-magnesium oxide, indium-gallium oxide, indium-gallium-zinc oxide, indium-aluminum-zinc oxide, indium-tin-zinc oxide, tin-gallium-zinc oxide, Aluminum-gallium-zinc-based oxide, indium-aluminum-zinc-based oxide, indium-tin-zinc-based oxide, tin-gallium-zinc-based oxide, aluminum-gallium-zinc-based oxide, or a combination thereof.

In an embodiment of the invention, the pixel structure further includes a channel protection pattern, which is disposed on the oxide semiconductor pattern and covers the gate pattern.

In an embodiment of the invention, the pixel structure further includes a gate oxide layer, which is disposed between the gate pattern and the oxide semiconductor pattern.

In an embodiment of the invention, the pixel structure further includes an insulating pattern and a transparent electrode. The insulating pattern is disposed on the second conductive layer. The transparent electrode is disposed on the insulating pattern and covers the pixel electrode. The transparent electrode has a plurality of slits.

In an embodiment of the invention, the oxide semiconductor pattern partially covers the pixel electrode and the data line.

In an embodiment of the invention, the inter-electrode insulating pattern has a source opening and a drain opening. The source opening exposes the data line. The pixel electrode is exposed by the drain opening. The oxide semiconductor pattern extends into the source opening and the drain opening to be electrically connected to the data line and the pixel electrode, respectively.

In an embodiment of the invention, the oxide semiconductor pattern does not overlap the data line and the pixel electrode.

In an embodiment of the invention, the first conductive layer further includes a source pattern and a drain pattern. The source pattern extends from the data line into the active area. The pixel electrode covers the first portion of the drain pattern, and the second portion of the drain pattern is located in the active area. The oxide semiconductor pattern is electrically connected to the source pattern and the drain pattern.

The method for manufacturing a pixel structure according to an embodiment of the present invention includes the following steps: forming a first conductive layer on a substrate, wherein the first conductive layer includes a data line, a first gate line, and a pixel electrode, and the data line extends along the first direction , The first gate line extends in the second direction, the pixel electrode has an active area opening defining the active area, and the data line, the first gate line and the pixel electrode surround the active area; on the substrate and the first conductive layer Forming an inter-electrode insulating pattern; forming a second conductive layer on the inter-electrode insulating pattern, wherein the second conductive layer includes a second gate line and a gate pattern, the second gate line extends along the second direction and is parallel to the first gate A pole line, the gate pattern extends from the second gate line into the active area; a gate oxide layer is formed on the surface of the gate pattern; and an oxide semiconductor pattern is formed in the active area, wherein the oxide semiconductor pattern covers the gate The pattern and the gate oxide layer, and the oxide semiconductor pattern is electrically connected to the data line and the pixel electrode.

In an embodiment of the invention, the manufacturing method of the pixel structure further includes: forming a channel protection pattern on the oxide semiconductor pattern, wherein the channel protection pattern covers the gate pattern.

In an embodiment of the invention, the oxide semiconductor pattern covers the pixel electrode and the data line.

In an embodiment of the invention, the inter-electrode insulating pattern has a source opening and a drain opening, the source opening exposes the data line, the drain opening exposes the pixel electrode, and the oxide semiconductor pattern extends into the source opening The drain opening is electrically connected to the data line and the pixel electrode respectively.

In an embodiment of the invention, the oxide semiconductor pattern does not overlap the data line and the pixel electrode.

In an embodiment of the invention, the first conductive layer further includes a source pattern and a drain pattern. The source pattern extends from the data line into the active area. The pixel electrode covers the first portion of the drain pattern, and the second portion of the drain pattern is located in the active area. The oxide semiconductor pattern is electrically connected to the drain pattern and the source pattern.

Based on the above, compared to the design in which the gate line and the data line are respectively provided below and above the active layer, the data line of the embodiment of the present invention can be provided together with the first gate line and the pixel electrode as the active layer Below the oxide semiconductor pattern. Therefore, the oxide semiconductor pattern can directly or indirectly contact the upper surface of the data line and the pixel electrode, and a lithography process can be saved. In addition, the active layer of the embodiment of the present invention is composed of an oxide semiconductor material with high carrier mobility and low leakage, so the size of the thin film transistor can be reduced and the switching characteristics can be improved, and the aperture ratio of the pixel structure can be increased. On the other hand, in the embodiments of the present invention, by providing the first gate line and the second gate line connected in parallel to each other, the problem of electrical abnormality caused by the disconnection of the first gate line or the second gate line can be avoided. In this way, the line width of the first gate line and the second gate line can be further reduced, so the aperture ratio of the pixel structure can be further increased.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

FIG. 1 is a flowchart of a method for manufacturing a pixel structure 10 according to some embodiments of the present invention. 2A to 2E are schematic top views of the structure at various stages in the method of manufacturing the pixel structure 10 shown in FIG. 1. Fig. 3A is a schematic cross-sectional view taken along line A-A' of Fig. 2E. Fig. 3B is a schematic cross-sectional view taken along line B-B' of Fig. 2E. Fig. 3C is a schematic cross-sectional view taken along line C-C' of Fig. 2E. In these embodiments, the manufacturing method of the pixel structure 10 includes the following steps.

Referring to FIGS. 1 and 2A, step S100 is performed to form the first conductive layer 110 on the substrate 100. In some embodiments, the substrate 100 may be a transparent substrate. For example, the material of the substrate 100 may include glass, quartz, organic polymer, a combination thereof, or the like. The first conductive layer 110 includes a data line DL, a first gate line GL1 and a pixel electrode PE. The data line DL and the first gate line GL1 extend along both sides of the pixel electrode PE, respectively. The data line DL extends in the first direction D1, and the first gate line GL1 extends in the second direction D2. The first direction D1 intersects the second direction D2. In some embodiments, the first direction D1 may be substantially perpendicular to the second direction D2. The first gate line GL1 is a discontinuous line segment. In some embodiments, the first gate line GL1 is not continuous at the intersection with the data line DL, so that the first gate line GL1 does not overlap the data line DL. The pixel electrode PE has an active area opening AP that defines an active area AA. In some embodiments, the active area opening AP is located at a corner of the pixel electrode PE adjacent to the intersection of the data line DL and the first gate line GL1. In this way, the data line DL, the first gate line GL1 and the pixel electrode PE may surround the active area AA. In some embodiments, the data line DL and the first gate line GL1 may include molybdenum, molybdenum/aluminum/molybdenum multilayer structure, or other metal materials, respectively. The pixel electrode PE may be a transparent conductive layer, for example, composed of indium tin oxide, indium zinc oxide, a combination thereof, or the like. In some embodiments, the line widths of the data line DL and the first gate line GL1 may be 1 μm to 3 μm, respectively.

In some embodiments, the first conductive layer 110 may include a plurality of data lines DL, a plurality of first gate lines GL1, and a plurality of pixel electrodes PE arranged in an array. The plurality of data lines DL are arranged along the first direction D1, and the plurality of first gate lines GL1 are arranged along the second direction D2. In this way, multiple data lines DL and multiple first gate lines GL1 can separate multiple pixel (sub-pixel) regions. Multiple pixel electrodes PE are located in multiple pixel (sub-pixel) regions, respectively.

Referring to FIGS. 1 and 2B, step S102 is performed to form an inter-electrode insulating pattern 120 on the substrate 100 and the first conductive layer 110. In some embodiments, the method of forming the inter-electrode insulating pattern 120 includes forming an insulating material layer (not shown) on the substrate 100. Subsequently, the insulating material layer is patterned to form the inter-electrode insulating pattern 120. The inter-electrode insulating pattern 120 includes a gate opening VG, a source opening VS, and a drain opening VD. The gate opening VG exposes the first gate line GL1. In some embodiments, the inter-electrode insulating pattern 120 has a plurality of gate openings VG. Each line segment of the first gate line GL1 may be exposed to at least two gate openings VG. The source opening VS exposes the data line DL, and the drain opening VD exposes the pixel electrode PE. The source opening VS and the drain opening VD may be located on opposite sides of the active area AA. In some embodiments, the material of the inter-electrode insulating pattern 120 may include silicon oxide, silicon nitride, a combination thereof, or the like.

Step S104 is performed to form the second conductive layer 130 on the inter-electrode insulating pattern 120. The second conductive layer 130 includes a second gate line GL2 and a gate pattern GE. The second gate line GL2 extends along the second direction D2. In some embodiments, the second gate line GL2 covers the first gate line GL1. In some embodiments, the line width of the second gate line GL2 may be 1 μm to 3 μm. In addition, the second gate line GL2 may be a continuous line segment. In this way, a part of the second gate line GL2 can cover and cross the data line DL. The second gate line GL2 is filled in the gate opening VG of the inter-electrode insulating pattern 120 so that the second gate line GL2 is electrically connected to the first gate line GL1. In some embodiments, both ends of each line segment of the first gate line GL1 are exposed to the two gate openings VG, so that the second gate line GL2 formed on the first gate line GL1 can be connected in parallel to Each line segment of the first gate line GL1. In other embodiments, each line segment of the first gate line GL1 may be exposed to more than three gate openings VG. The gate pattern GE extends from the second gate line GL2 into the active area AA along the first direction D1. The source opening VS and the drain opening VD may be located on opposite sides of the gate pattern GE. In some embodiments, the gate pattern GE is an extension of the second gate line GL2. In other words, the second gate line GL2 and the gate pattern GE may not have an interface, and may be formed of the same material and the same process steps. In some embodiments, the materials of the second gate line GL2 and the gate pattern GE may include aluminum alloys, such as aluminum neodymium alloys.

In some embodiments, after the second conductive layer 130 is formed, an oxidation process may be performed on the gate pattern GE. In this way, the gate oxide layer 132 can be formed on the surface of the gate pattern GE (please refer to FIG. 3A ). In some embodiments, the method of forming the gate oxide layer 132 is, for example, anodization. For example, the material of the gate oxide layer 132 may be aluminum oxide, and the thickness is 100 nm, for example. For brevity, the gate oxide layer 132 is omitted in FIGS. 2A to 2E.

Referring to FIGS. 1 and 2C, step S106 is performed to form an oxide semiconductor pattern 140 in the active area AA. The oxide semiconductor pattern 140 covers the gate pattern GE. In some embodiments, the oxide semiconductor pattern 140 extends along the second direction D2 onto the data line DL and the pixel electrode PE. In addition, the oxide semiconductor pattern 140 is filled in the source opening VS and the drain opening VD, and is electrically connected to the data line DL and the pixel electrode PE. From this, it can be seen that the oxide semiconductor pattern 140 is in contact with the upper surface of the data line DL and the pixel electrode PE. In some embodiments, the oxide semiconductor pattern 140 directly contacts the upper surface of the data line DL and the pixel electrode PE. In some embodiments, the material of the oxide semiconductor pattern 140 may include zinc oxide, tin oxide, tin-zinc oxide, aluminum-zinc oxide, zinc-magnesium oxide, tin-magnesium oxide, indium -Magnesium oxide, indium-gallium oxide, indium-gallium-zinc oxide, indium-aluminum-zinc oxide, indium-tin-zinc oxide, tin-gallium-zinc oxide, aluminum -Gallium-zinc-based oxide, indium-aluminum-zinc-based oxide, indium-tin-zinc-based oxide, tin-gallium-zinc-based oxide, aluminum-gallium-zinc-based oxide, or a combination thereof.

Referring to FIGS. 1 and 2D, step S108 is performed to form a channel protection pattern 150 on the oxide semiconductor pattern 140. The channel protection pattern 150 overlaps with the gate pattern GE. In some embodiments, the top view pattern of the channel protection pattern 150 may be I-shaped, and the straight line portion of the channel protection pattern 150 extends along the first direction D1. In addition, in some embodiments, the channel protection pattern 150 partially overlaps the oxide semiconductor pattern 140 without extending onto the data line DL and the pixel electrode PE. A part (or first part) of the oxide semiconductor pattern 140 covered by the channel protection pattern 150 can be prevented from being affected by oxygen molecules in the environment, while maintaining semiconductor properties (that is, having a high impedance). On the other hand, another part (or second part) of the oxide semiconductor pattern 140 that does not overlap with the channel protection pattern 150 may be affected by oxygen molecules in the environment and has a property that tends to be a conductor (that is, has a lower Impedance). In this way, the contact resistance between the data line DL and the second portion of the oxide semiconductor pattern 140 can be reduced to form a better ohmic contact. Similarly, the contact resistance between the pixel electrode PE and the second portion of the oxide semiconductor pattern 140 can also be reduced, and a better ohmic contact can be formed. Those skilled in the art can adjust the top-view pattern and area of the channel protection pattern 150 according to design requirements, and the invention is not limited thereto. In some embodiments, the material of the channel protection pattern 150 may include an organic photoresist.

The gate pattern GE, the gate oxide layer 132 (please refer to FIG. 3A) and the oxide semiconductor pattern 140 constitute a thin film transistor, which can be used as a switching element of a pixel structure. Specifically, the first portion of the oxide semiconductor pattern 140 covered by the channel protection pattern 150 may define the channel of the thin film transistor. The gate pattern GE may serve as the gate of the thin film transistor, and the gate oxide layer 132 may serve as the gate dielectric layer of the thin film transistor. In addition, the second portion of the oxide semiconductor pattern 140 not covered by the channel protection pattern 150 is filled in the drain opening VD and the source opening VS to serve as the drain and the source of the thin film transistor, respectively, and are electrically connected respectively The pixel electrode PE and the data line DL.

Referring to FIGS. 1 and 2E, step S110 is performed to form an insulating pattern 160 on the second conductive layer 130, the oxide semiconductor pattern 140, and the channel protection pattern 150. In some embodiments, the method of forming the insulating pattern 160 includes forming an insulating material layer (not shown) that completely covers the substrate 100. The insulating material layer covers the central display area and the edge trace area of the substrate 100. Next, the insulating material layer is patterned to form the insulating pattern 160. The insulating pattern 160 has a pad opening 162 and a pad opening 164 in the edge trace area. The pad opening 162 exposes the data line DL, and the pad opening 164 exposes the first gate line GL1. On the other hand, the insulating pattern 160 completely covers the central display area of the substrate 100. In other words, the insulating pattern 160 completely covers the first conductive layer 110, the inter-electrode insulating pattern 120, the second conductive layer 130, the oxide semiconductor pattern 140, and the channel protection pattern 150 in the central display area. In some embodiments, the material of the insulating pattern 160 may include silicon oxide, silicon nitride, a combination thereof, or the like.

Proceeding to step S112, a transparent electrode 170 is formed on the insulating pattern 160. The transparent electrode 170 partially covers the central display area of the substrate 100. Specifically, the transparent electrode 170 partially covers the pixel electrode PE, the first gate line GL1, the second gate line GL2, and the data line DL. In addition, the transparent electrode 170 does not overlap the active area AA, the source opening VS, and the drain opening VD. In other words, the transparent electrode 170 has openings to expose the gate pattern GE, the oxide semiconductor pattern 140, the channel protection pattern 150, the source opening VS, and the drain opening VD. In some embodiments, the transparent electrode 170 located in the central display area has a plurality of slits SL. The plurality of slits SL expose the insulating pattern 160. In some embodiments, the plurality of slits SL extend along the first direction D1 and are arranged along the second direction D2. In some embodiments, the plurality of slits SL may be elongated, and the lengths of the plurality of slits SL may be the same as or different from each other. In other embodiments, the plurality of slits SL may have other shapes. The present invention is not limited to the shape or size of the slits SL. On the other hand, the transparent electrode 170 covers the edge routing area of the substrate 100 so that the transparent electrode 170 is filled in the pad opening 162 and the pad opening 164. In this way, the transparent electrode 170 located in the edge trace area is electrically connected to the data line DL, the first gate line GL1 and the second gate line GL2.

So far, the manufacturing of the pixel structure 10 has been completed. In some embodiments, another substrate with color filters may be bonded to the pixel structure 10, and a liquid crystal layer is filled between the other substrate and the pixel structure 10 to form a display device. Next, the structure of the pixel structure 10 will be explained with reference to FIGS. 2E and 3A to 3C.

2E and 3A to 3C, the pixel structure 10 includes a first conductive layer 110, an inter-electrode insulating pattern 120, a second conductive layer 130, and an oxide semiconductor pattern 140. The first conductive layer 110 is disposed on the substrate 100 and includes a data line DL, a first gate line GL1, and a pixel electrode PE. The data line DL extends along the first direction D1. The first gate line GL1 extends in the second direction D2. The pixel electrode PE has an active area opening AP that defines an active area AA (as shown in FIG. 2A). The data line DL, the first gate line GL1 and the pixel electrode PE surround the active area AA. The inter-electrode insulating pattern 120 is disposed on the substrate 100 and covers the first conductive layer 110. The second conductive layer 130 is disposed on the inter-electrode insulating pattern 120 and includes the second gate line GL2 and the gate pattern GE. The second gate line GL2 extends along the second direction D2 and is parallel to the first gate line GL1. The gate pattern GE extends from the second gate line GL2 into the active area AA. The oxide semiconductor pattern 140 is disposed in the active area AA and covers the gate pattern GE. In addition, the oxide semiconductor pattern 140 is electrically connected to the data line DL and the pixel electrode PE.

In some embodiments, the pixel structure 10 further includes a channel protection pattern 150. The channel protection pattern 150 is disposed on the oxide semiconductor pattern 140 and covers the gate pattern GE. In some embodiments, the pixel structure 10 further includes a gate oxide layer 132. The gate oxide layer 132 is disposed between the gate pattern GE and the oxide semiconductor pattern 140. In some embodiments, the pixel structure 10 further includes an insulating pattern 160 and a transparent electrode 170. The insulating pattern 160 is disposed on the second conductive layer 130. The transparent electrode 170 is disposed on the insulating pattern 160 and covers the pixel electrode PE. The transparent electrode 170 has a plurality of slits SL. In some embodiments, the oxide semiconductor pattern 140 partially covers the pixel electrode PE and the data line DL. In such embodiments, the inter-electrode insulating pattern 120 has a source opening VS and a drain opening VD. The source opening VS exposes the data line DL. The drain electrode VD exposes the pixel electrode PE. The oxide semiconductor pattern 140 extends into the source opening VS and the drain opening VD to be electrically connected to the data line DL and the pixel electrode PE, respectively.

Based on the above, compared to the design in which the gate line and the data line are provided below and above the active layer, the data line DL of the embodiment of the present invention can be provided together with the first gate line GL1 and the pixel electrode PE as Below the oxide semiconductor pattern 140 of the active layer. Therefore, the oxide semiconductor pattern 140 can be in contact with the upper surface of the data line DL and the pixel electrode PE, and a lithography process can be saved. In addition, the active layer of the embodiment of the present invention is composed of an oxide semiconductor material with high carrier mobility and low leakage, so the size of the thin film transistor can be reduced and the switching characteristics can be improved, and the aperture ratio of the pixel structure 10 can be increased. On the other hand, in the embodiment of the present invention, by providing the first gate line GL1 and the second gate line GL2 connected in parallel to each other, the electrical property of the first gate line GL1 or the second gate line GL2 due to disconnection can be avoided Unusual problem. In this way, the line width of the first gate line GL1 and the second gate line GL2 can be further reduced, so the aperture ratio of the pixel structure 10 can be further increased.

4A to 4E are schematic top views of structures at various stages in the method of manufacturing the pixel structure 20 according to other embodiments of the present invention. Fig. 5A is a schematic cross-sectional view taken along the line D-D' of Fig. 4E. Fig. 5B is a schematic cross-sectional view taken along line E-E' of Fig. 4E. Fig. 5C is a schematic cross-sectional view taken along line F-F' of Fig. 4E.

The manufacturing method of the pixel structure 20 is similar to the manufacturing method of the pixel structure 10 shown in FIG. 2A to FIG. 2E. The following only describes the differences between the two, and the same or similar points will not be repeated. In addition, the same or similar element numbers represent the same or similar elements (for example, the first conductive layer 110 and the first conductive layer 210).

Referring to FIGS. 1 and 4A, step S100 is performed to form the first conductive layer 210 on the substrate 100. The first conductive layer 210 includes a data line DL, a first gate line GL1 and a pixel electrode PE, and further includes a source pattern SE and a drain pattern DE. In some embodiments, the data line DL, the first gate line GL1, the source pattern SE and the drain pattern DE are formed on the substrate 100, and then the pixel electrode PE is formed. The source pattern SE extends from the data line DL into the active area AA. In some embodiments, the source pattern SE is an extension of the data line DL. In other words, the data line DL and the source pattern SE may not have an interface, and may be formed by the same material and the same process steps. The drain pattern DE has a first part DE1 and a second part DE2. The pixel electrode PE covers the first portion DE1. The second portion DE2 extends from the first portion DE1 into the active area AA, and does not overlap the pixel electrode PE. The second portions DE2 of the source pattern SE and the drain pattern DE are opposed to each other, and are separated from each other without contacting each other.

1 and 4B, step S102 is performed to form an inter-electrode insulating pattern 220 on the substrate 100 and the first conductive layer 210. In some embodiments, the inter-electrode insulating pattern 220 includes the gate opening VG, but may not include the source opening VS and the drain opening VD as shown in FIG. 2B. Subsequently, step S104 is performed to form the second conductive layer 130 on the inter-electrode insulating pattern 220. The second conductive layer 130 includes a second gate line GL2 and a gate pattern GE. The gate pattern GE extends from the second gate line GL2 into the active area AA along the first direction D1, and is not in contact with the source pattern SE and the drain pattern DE. In some embodiments, after the second conductive layer 130 is formed, an oxidation process may be performed on the gate pattern GE. In this way, the gate oxide layer 132 can be formed on the surface of the gate pattern GE (please refer to FIG. 5B ).

Referring to FIGS. 1 and 4C, step S106 is performed to form an oxide semiconductor pattern 240 in the active area AA. The oxide semiconductor pattern 240 covers the gate pattern GE. In some embodiments, the oxide semiconductor pattern 240 extends along the second direction D2 and does not overlap the data line DL and the pixel electrode PE.

Referring to FIGS. 1 and 4D, step S108 is performed to form a channel protection pattern 250 on the oxide semiconductor pattern 240. In some embodiments, the channel protection pattern 250 extends along the first direction D1 and the second direction D2 to cover the data line DL, the first gate line GL1, and the second gate line GL2. In addition, the channel protection pattern 250 includes an extension that extends along the first direction D1 and covers the gate pattern GE. In some embodiments, the top view pattern of the extension of the channel protection pattern 250 may be I-shaped.

In step S110, an insulating pattern 260 is formed on the second conductive layer 130, the oxide semiconductor pattern 240, and the channel protection pattern 250. In some embodiments, the method of forming the insulating pattern 260 includes forming an insulating material layer (not shown) that completely covers the substrate 100. The insulating material layer covers the central display area and the edge trace area of the substrate 100. Next, the insulating material layer is patterned to form an insulating pattern 260. The insulating pattern 260 has a pad opening 162 and a pad opening 164 in the edge trace area. The pad opening 162 exposes the data line DL, and the pad opening 164 exposes the first gate line GL1. On the other hand, the insulating pattern 160 has a first source opening VS1, a second source opening VS2, a first drain opening VD1, and a second drain opening VD2 in the central display area. The first source opening VS1 and the first drain opening VD1 expose the oxide semiconductor pattern 240 and are located on opposite sides of the extension of the channel protection pattern 250. The second source opening VS2 exposes the source pattern SE, and the second drain opening VD2 exposes the second portion DE2 of the drain pattern DE.

Referring to FIGS. 1 and 4E, step S112 is performed to form a transparent electrode 270 on the insulating pattern 260. In some embodiments, the transparent electrode 270 may include a first portion 270a, a second portion 270b, and a third portion 270c. The first portion 270a and the second portion 270b are located in the central display area of the substrate 100. The first part 270a partially covers the pixel electrode PE, the first gate line GL1, the second gate line GL2, and the data line DL. In some embodiments, the first portion 270a of the transparent electrode 270 has a plurality of slits SL. In addition, the first portion 270a extends toward the active area AA to extend from the pixel electrode PE to the oxide semiconductor pattern 240 on the side of the channel protection pattern 250 via the second portion DE2 of the drain pattern DE. In this way, the extended portion of the first portion 270a is filled in the first drain opening VD1 and the second drain opening VD2 to electrically connect the oxide semiconductor pattern 240 exposed by the first drain opening VD1 and the first The second portion DE2 of the drain pattern DE exposed by the second drain opening VD2. The second portion 270b of the transparent electrode 270 covers the oxide semiconductor pattern 240 and the source pattern SE on the other side of the channel protection pattern 250. As such, the extension of the first portion 270a and the second portion 270b of the transparent electrode 270 are located on opposite sides of the channel protection pattern 250. In addition, the second portion 270b of the transparent electrode 270 is filled in the first source opening VS1 and the second source opening VS2 to electrically connect the oxide semiconductor pattern 240 exposed by the first source opening VS1 and the first The source pattern SE exposed by the two source openings VS2. In some embodiments, the second portion 270b of the transparent electrode 270 further covers part of the data line DL. On the other hand, the third portion 270c of the transparent electrode 270 covers the edge routing area of the substrate 100, so that the third portion 270c of the transparent electrode 270 is filled in the pad opening 162 and the pad opening 164. In this way, the third portion 270c of the transparent electrode 270 is electrically connected to the data line DL, the first gate line GL1, and the second gate line GL2.

So far, the manufacturing of the pixel structure 20 has been completed. 4E and 5A to 5C, in the pixel structure 20, the gate pattern GE, the gate oxide layer 132, the oxide semiconductor pattern 240, the source pattern SE and the drain pattern DE constitute a thin film transistor, It can be used as a switching element of the pixel structure 20. In addition, a portion of the oxide semiconductor pattern 240 covered by the channel protection pattern 250 may define a channel of the thin film transistor. The gate pattern GE may serve as the gate of the thin film transistor, and the gate oxide layer 132 may serve as the gate dielectric layer of the thin film transistor. The drain pattern DE and the source pattern SE can be used as the drain and source of the thin film transistor, respectively. In these embodiments, the oxide semiconductor pattern 240 does not directly extend to the data line DL and the pixel electrode PE, but is electrically connected to the drain through the first portion 270a and the second portion 270b of the transparent electrode 270, respectively The upper surface of the pattern DE and the source pattern SE. In other words, the oxide semiconductor patterns 240 are electrically connected to the upper surfaces of the pixel electrode PE and the data line DL, respectively.

In summary, compared to the design in which the gate line and the data line are respectively provided below and above the active layer, the data line of the embodiment of the present invention can be provided together with the first gate line and the pixel electrode as the active Layer under the oxide semiconductor pattern. Therefore, the oxide semiconductor pattern can directly or indirectly contact the upper surface of the data line and the pixel electrode, and a lithography process can be saved. In addition, the active layer of the embodiment of the present invention is composed of an oxide semiconductor material with high carrier mobility and low leakage, so the size of the thin film transistor can be reduced and the switching characteristics can be improved, and the aperture ratio of the pixel structure can be increased. On the other hand, in the embodiments of the present invention, by providing the first gate line and the second gate line connected in parallel to each other, the problem of electrical abnormality caused by the disconnection of the first gate line or the second gate line can be avoided. In this way, the line width of the first gate line and the second gate line can be further reduced, so the aperture ratio of the pixel structure can be further increased.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 20 ‧ ‧ ‧ pixel structure 100 ‧ ‧ ‧ substrate 110, 210 ‧ ‧ ‧ first conductive layer 120, 220 ‧ ‧ ‧ inter-electrode insulation pattern 130 ‧ ‧ ‧ second conductive layer 132 ‧ ‧ ‧ gate oxide layer 140, 240‧‧‧Oxide semiconductor pattern 150, 250‧‧‧ channel protection pattern 160, 260‧‧‧ insulation pattern 162, 164‧‧‧ pad opening 170, 270‧‧‧ transparent electrode 270a‧‧‧Part 1 270b‧‧‧Second part 270c‧‧‧ Third part AA‧‧‧Active area AP‧‧‧Active area opening D1‧‧‧ First direction D2‧‧‧Second direction DE‧‧‧Drain pattern DE1‧ ‧‧Part 1 DE2‧‧‧Part 2 DL‧‧‧Data line GE‧‧‧Gate pattern GL1‧‧‧First gate line GL2‧‧‧Second gate line PE‧‧‧Pixel electrode S100 , S102, S104, S106, S108, S110, S112 ‧‧‧ Step SE‧‧‧ Source pattern SL‧‧‧Slit VD‧‧‧Drain opening VD1‧‧‧First drain opening VD2‧‧‧ Second drain opening VG‧‧‧ Gate opening VS‧‧‧ Source opening VS1‧‧‧First source opening VS2‧‧‧Second source opening

FIG. 1 is a flowchart of a method for manufacturing a pixel structure according to some embodiments of the present invention. 2A to 2E are schematic top views of the structure at each stage in the method for manufacturing the pixel structure shown in FIG. 1. Fig. 3A is a schematic cross-sectional view taken along line A-A' of Fig. 2E. Fig. 3B is a schematic cross-sectional view taken along line B-B' of Fig. 2E. Fig. 3C is a schematic cross-sectional view taken along line C-C' of Fig. 2E. 4A to 4E are schematic top views of structures at various stages in a method of manufacturing a pixel structure according to other embodiments of the present invention. Fig. 5A is a schematic cross-sectional view taken along the line D-D' of Fig. 4E. Fig. 5B is a schematic cross-sectional view taken along line E-E' of Fig. 4E. Fig. 5C is a schematic cross-sectional view taken along line F-F' of Fig. 4E.

10‧‧‧ pixel structure

110‧‧‧ First conductive layer

130‧‧‧Second conductive layer

140‧‧‧oxide semiconductor pattern

150‧‧‧channel protection pattern

160‧‧‧Insulation pattern

162, 164‧‧‧ Pad opening

170‧‧‧Transparent electrode

D1‧‧‧First direction

D2‧‧‧Second direction

DL‧‧‧Data cable

GE‧‧‧Gate pattern

GL1‧‧‧First gate line

GL2‧‧‧Second Gate Line

PE‧‧‧Pixel electrode

SL‧‧‧Slit

VD‧‧‧Drain opening

VG‧‧‧gate opening

VS‧‧‧Source opening

Claims (15)

A pixel structure includes: a first conductive layer disposed on a substrate, wherein the first conductive layer includes: a data line extending in a first direction; a first gate line extending in a second direction; and a pixel The electrode has an active area opening defining an active area, wherein the data line, the first gate line and the pixel electrode surround the active area; an inter-electrode insulating pattern is provided on the substrate and covers The first conductive layer; the second conductive layer, disposed on the inter-electrode insulating pattern, wherein the second conductive layer includes: a second gate line extending in the second direction and parallel to the A first gate line; and a gate pattern extending from the second gate line into the active region; and an oxide semiconductor pattern disposed in the active region and covering the gate pattern, wherein The oxide semiconductor pattern is electrically connected to the data line and the pixel electrode. The pixel structure as described in item 1 of the patent application, wherein the material of the oxide semiconductor pattern includes zinc oxide, tin oxide, tin-zinc oxide, aluminum-zinc oxide, zinc-magnesium oxide , Tin-magnesium oxide, indium-magnesium oxide, indium-gallium oxide, indium-gallium-zinc oxide, indium-aluminum-zinc oxide, indium-tin-zinc oxide, tin -Gallium-zinc series oxide, aluminum-gallium-zinc series oxide, indium-aluminum-zinc series oxide, indium-tin-zinc series oxide, tin-gallium-zinc series oxide, aluminum-gallium-zinc series Oxides or combinations thereof. The pixel structure as described in item 1 of the patent application further includes: a channel protection pattern, which is provided on the oxide semiconductor pattern and covers the gate pattern. The pixel structure as described in item 1 of the patent application scope further includes: a gate oxide layer disposed between the gate pattern and the oxide semiconductor pattern. The pixel structure as described in item 1 of the patent application scope further includes: an insulating pattern provided on the second conductive layer; and a transparent electrode provided on the insulating pattern and covering the pixel electrode, wherein The transparent electrode has a plurality of slits. The pixel structure as described in item 1 of the patent application range, wherein the oxide semiconductor pattern partially covers the pixel electrode and the data line. The pixel structure as described in item 6 of the patent application range, wherein the inter-electrode insulating pattern has a source opening and a drain opening, the source opening exposes the data line, and the drain opening exposes The pixel electrode, and the oxide semiconductor pattern extends into the source opening and the drain opening to be electrically connected to the data line and the pixel electrode, respectively. The pixel structure as described in item 1 of the patent application range, wherein the oxide semiconductor pattern does not overlap the data line and the pixel electrode. The pixel structure as described in item 8 of the patent application scope, wherein the first conductive layer further comprises: a source pattern extending from the data line into the active area; and a drain pattern, wherein the picture The element electrode covers the first portion of the drain pattern, and the second portion of the drain pattern is located in the active region, wherein the oxide semiconductor pattern is electrically connected to the source pattern and the drain pattern. A method for manufacturing a pixel structure includes: forming a first conductive layer on a substrate, wherein the first conductive layer includes a data line, a first gate line, and a pixel electrode, and the data line extends in a first direction, The first gate line extends along the second direction, the pixel electrode has an active area opening defining an active area, and the data line, the first gate line, and the pixel electrode surround the An active region; forming an inter-electrode insulating pattern on the substrate and the first conductive layer; forming a second conductive layer on the inter-electrode insulating pattern, wherein the second conductive layer includes a second gate line and a gate A gate pattern, the second gate line extends along the second direction and is parallel to the first gate line, the gate pattern extends from the second gate line into the active region; Forming a gate oxide layer on the surface of the gate pattern; and forming an oxide semiconductor pattern in the active region, wherein the oxide semiconductor pattern covers the gate pattern and the gate oxide layer, and The oxide semiconductor pattern is electrically connected to the data line and the pixel electrode. The method for manufacturing a pixel structure as described in item 10 of the patent application scope further includes: forming a channel protection pattern on the oxide semiconductor pattern, wherein the channel protection pattern covers the gate pattern. The method for manufacturing a pixel structure as described in item 10 of the patent application range, wherein the oxide semiconductor pattern covers the pixel electrode and the data line. The method for manufacturing a pixel structure as described in item 12 of the patent application range, wherein the inter-electrode insulating pattern has a source opening and a drain opening, the source opening exposes the data line, and the drain opening The pixel electrode is exposed, and the oxide semiconductor pattern extends into the source opening and the drain opening to be electrically connected to the data line and the pixel electrode, respectively. The method for manufacturing a pixel structure as described in item 10 of the patent application range, wherein the oxide semiconductor pattern does not overlap the data line and the pixel electrode. The method for manufacturing a pixel structure as described in item 14 of the patent application range, wherein the first conductive layer further comprises: a source pattern extending from the data line into the active area; and a drain pattern, wherein The pixel electrode covers the first portion of the drain pattern, and the second portion of the drain pattern is located in the active region, wherein the oxide semiconductor pattern is electrically connected to the drain pattern and the Describe the source pattern.

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