TWI416231B - Pixel array substrate - Google Patents

Abstract

A pixel array substrate includes a substrate, a plurality of first and second scan lines, a plurality of pixels and a plurality of first and second compensation structures. The pixels include a plurality of first and second pixels and are disposed between a pair of the first and the second scan lines and the data lines. The first pixels are connected to the first scan lines and a first side of the data lines, and the second pixels are connected to the second scan lines and a second side of the data lines. The first and the second compensation structures are respectively disposed at the second side and the first side of the corresponding data lines, and include a conductive pattern, a semiconductor pattern and a source compensation pattern. The conductive patterns of the first and the second compensation structures are electrically connected to the first and the second scan lines, and at least overlap with the source compensation pattern of the first and the second pixels, respectively. The sources and the source compensation patterns are electrically connected to the data lines.

Description

Pixel array substrate

The present invention relates to a substrate, and more particularly to a pixel array substrate.

A general liquid crystal display is mainly composed of an active device array substrate, a pair of substrates, and a liquid crystal layer sandwiched between the two substrates. The active device array substrate mainly includes a plurality of scan lines, a plurality of data lines, an active component arranged between the scan lines and the data lines, and a pixel electrode (Pixel Electrode) corresponding to each active element. The above active device is usually a thin film transistor including a gate, a semiconductor layer, a source and a drain, which are used as switching elements of the liquid crystal display unit.

1 is a schematic view of a conventional pixel array substrate. Referring to FIG. 1, in the pixel array substrate 100, a plurality of pixels 130a and 130b are arranged in a plurality of columns, each column of pixels is located between two scanning lines 110a and 110b, and two scanning lines 110a and 110b are located in phase. Between the two columns of pixels. The pixels 130a and 130b are located on two sides of the data line 120. The gates 142 and 152 of the active elements 140 and 150 of the pixels 130a and 130b are electrically connected to the scan lines 110a and 110b, respectively, and the pixels 130a. The sources 144, 154 of the active components 140, 150 in 130b are electrically connected to the same data line 120.

Generally, in the process of fabricating the active device array substrate having the pixel array substrate 100, the gates 142, 152 of the active devices 140, 150 and the scan lines 110a, 110b are formed by a first conductor layer (Metal 1). Lord The source 144, 154, the drain 146, 156 of the movable element 140, 150 and the data line 120 are formed by a second conductor layer (Metal 2), and the first conductor layer and the second conductor layer are processed by different mask processes. maded. Therefore, when the precision of the machine is insufficient or the alignment error on the process, the relative displacement between the gates 142, 152 of the active elements 140, 150 and the sources 144, 154 and the drains 146, 156 is caused. The characteristics of the active components 140, 150 deviate from the original design values.

In detail, the signal transmission quality of the scan lines 110a, 110b is related to the parasitic capacitance on the scan lines 110a, 110b in addition to the impedance of the scan lines 110a, 110b itself, that is, the so-called resistance-capacitance effect. (RC effect). Further, the parasitic capacitance on the scan lines 110a, 110b is approximately proportional to the overlap area of the scan lines 110a, 110b and the drains 146, 156. Once the alignment error occurs on the process, the parasitic capacitance on the same scan line 110a or 110b will change accordingly. That is to say, the alignment error of the process will affect the signal transmission quality of the scan lines 110a, 110b.

The invention provides a pixel array substrate, which effectively improves the problem that the gate-source parasitic capacitance changes due to the alignment error in the process.

The invention provides a pixel array substrate, which comprises a substrate, a plurality of first scan lines, a plurality of second scan lines, a plurality of pixels, a plurality of first compensation structures and a plurality of second compensation structures. The first scan line and the second scan line are disposed in pairs on the substrate. The data line is disposed perpendicular to the first scan line and the second scan line. The plurality of pixels includes a plurality of first pixels and a plurality of second pixels, And located between a pair of first scan lines, a second scan line and data lines. The first pixel is connected to the first side of the first scan line and the data line, and the second pixel is connected to the second side of the second scan line and the data line. The first compensation structure is located on the second side of the corresponding data line, the first compensation structure includes a first conductor pattern, a first semiconductor pattern, and a first source compensation pattern, the first conductor pattern is connected to the first scan line, the first The semiconductor pattern is located above the first conductor pattern, and the first source compensation pattern is at least partially located on the first semiconductor pattern and electrically connected to the data line. The second compensation structure is located at a first side of the corresponding data line, the second compensation structure includes a second conductor pattern, a second semiconductor pattern, and a second source compensation pattern, the second conductor pattern is connected to the second scan line, and the second The semiconductor pattern is located above the second conductor pattern, and the second source compensation pattern is at least partially located on the second semiconductor pattern and electrically connected to the data line.

In an embodiment of the invention, the first pixel includes a first gate, a first semiconductor layer, a first drain, and a first source, and the first gate and the first scan line are electrically Optionally, the first semiconductor layer is located above the first gate, the first source and the first drain are at least partially located on the first semiconductor layer, and the first source is electrically connected to the data line.

In an embodiment of the invention, the first source has a first width aligned with the first gate boundary, and the first source compensation pattern has a second width at the same level as the first conductor pattern boundary. The first width is substantially equal to the second width.

In an embodiment of the invention, the second pixel includes a second gate, a second semiconductor layer, a second drain, and a second source. The second gate is electrically connected to the second scan line, the second semiconductor layer is located above the second gate, the second source and the second drain are at least partially located on the second semiconductor layer, and the second source and the data line are electrically connected. connection.

In an embodiment of the invention, the second source and the second gate have a third width at the same time, and the second source compensation pattern and the second conductor pattern have a fourth width. The third width is substantially equal to the fourth width.

In an embodiment of the invention, the first conductor pattern is integrally formed with the first scan line.

In an embodiment of the invention, the first source compensation pattern is integrally formed with the data line.

In an embodiment of the invention, the second conductor pattern is integrally formed with the second scan line.

In an embodiment of the invention, the second source compensation pattern is integrally formed with the data line.

In an embodiment of the invention, the first drain of the first pixel includes a comb portion and a connecting portion. The comb portion surrounds the first source, the comb portion having at least two branches, at least one of the branches extending beyond the first gate to define at least one protrusion located outside the first gate. The connecting portion extends from the comb portion to the outside of the first gate, and the protruding portion and the connecting portion are respectively located on opposite sides of the first gate, wherein the protruding portion has a fifth width at a line with the first gate boundary. The connection portion has a sixth width that is aligned with the first gate boundary, and the fifth width is substantially equal to the sixth width.

In an embodiment of the invention, one of the branches of the comb portion described above The extension extends beyond the first gate while the other is completely located in the region of the first gate such that the number of at least one projection is one.

In an embodiment of the invention, the second drain of the second pixel comprises a comb portion and a connecting portion. The comb portion surrounds the second source, the comb portion having at least two branches, at least one of the branches extending beyond the second gate to define at least one projection outside the second gate. The connecting portion extends from the comb portion to the outside of the second gate, and the protruding portion and the connecting portion are respectively located on opposite sides of the second gate, wherein the protruding portion has a seventh width at a line with the second gate boundary. The connecting portion is aligned with the second gate boundary at an eighth width, and the seventh width is substantially equal to the eighth width.

In an embodiment of the invention, one of the branches of the comb portion extends beyond the second gate, and the other is completely located in the region of the second gate so that at least one of the projections The quantity is one.

In an embodiment of the invention, the first semiconductor pattern is protruded from the first conductor pattern.

In an embodiment of the invention, the second semiconductor pattern is protruded from the second conductor pattern.

Based on the above, the present invention arranges the gate and the source on one side of the data line, and the conductor pattern and the source compensation pattern corresponding to the gate and the source on the other side of the same data line. Therefore, in the process of fabricating the pixel structure, the relative offset between the first conductor layer and the second conductor layer does not affect the overlap area between the gate and the source and the relationship between the conductor pattern and the source compensation pattern. The sum of the overlapping areas. That is, the conductor pattern-source compensation pattern parasitic capacitance can compensate for the gate-source parasitic capacitance variation, making the gate-source parasitic The sum of the capacitance and the conductor pattern-source compensation pattern parasitic capacitance is constant. Therefore, the pixel array substrate of the present invention does not adversely affect the display effect due to the alignment error on the process. In other words, the pixel array substrate of the present invention has good quality and product yield.

The above described features and advantages of the present invention will be more apparent from the following description.

2A is a schematic diagram of a pixel array substrate according to a first embodiment of the present invention, and FIG. 2B is a schematic diagram of the first pixel 230a and the second pixel 230b of FIG. 2A, and FIG. 2C and FIG. 2D are respectively along FIG. 2B. A schematic cross-sectional view of the A-A' line and the B-B' line. For convenience of explanation, only two pixel columns C _n , C _{n+1 are} represented as representative in FIG. 2A, and the first pixels 230a and second located on both sides of the data line DL(m) are shown in FIG. 2B. The pixel 230b is explained. Referring to FIG. 2A, in the embodiment, the pixel array substrate 200 includes a substrate 201, a plurality of first scan lines SL1(n), SL1(n+1), SL1(n+2), and a plurality of second scans. Lines SL2(n-1), SL2(n), SL2(n+1), a plurality of data lines DL(m-1), DL(m), DL(m+1), a plurality of pixels 230a, 230b a plurality of first compensation structures 260 and a plurality of second compensation structures 270. The first scan lines SL1(n), SL1(n+1), SL1(n+2) and the second scan lines SL2(n-1), SL2(n), and SL2(n+1) are in the column direction. Upward, and the first scan line SL1(n) and the second scan line SL2(n) are disposed in pairs on the substrate 201, the first scan line SL1(n+1) and the second scan line SL2(n+1) Paired on the substrate 201, and so on. The data lines DL(m-1), DL(m), and DL(m+1) extend in the row direction, and the first scan lines SL1(n), SL1(n+1), SL1(n+2), and The two scan lines SL2(n-1), SL2(n), SL2(n+1) and the data lines DL(m-1), DL(m), and DL(m+1) are vertically insulated from each other.

As shown in FIG. 2A, the pixel column Cn is located between the pair of first scan lines SL1(n) and the second scan line SL2(n), and the pixel column _Cn+1 is located in the pair of first scan lines SL1. Between (n+1) and the second scan line SL2(n+1), and so on. The plurality of pixels 230a, 230b include a plurality of first pixels 230a and a plurality of second pixels 230b arranged alternately, and are located in the pair of first scan lines SL1(n), SL1(n+1), SL1 ( n+2) and between the second scan lines SL2(n-1), SL2(n), SL2(n+1) and the data lines DL(m-1), DL(m), DL(m+1) . In detail, the first pixel 230a and the second pixel 230b shown in FIG. 2B, FIG. 2C, and FIG. 2D are described. The first pixel 230a and the first scanning line SL1(n) and the data line DL ( The first side 221a of m) is connected, and the second pixel 230b is connected to the second side 221b of the second scan line SL2(n) and the data line DL(m). In this embodiment, the first pixel 230a includes a first active device 240 and a first pixel electrode 249. The first active device 240 includes a first gate 242, a first semiconductor layer 244, a first source 246, and a first A bungee 248. The first gate 242 is electrically connected to the first scan line SL1(n), the first semiconductor layer 244 is located above the first gate 242, and the first source 246 and the first drain 248 are at least partially located in the first semiconductor. The layer 244 and the first source 246 are electrically connected to the data line DL(m). The first pixel electrode 249 is electrically connected to the first drain 248 to receive the signal transmitted on the data line DL(m) by turning on or off the first active device 240.

The second pixel 230b includes a second active component 250, a second active component 250 includes a second gate 252, a second semiconductor layer 254, a second source 256, a second drain 258, and a second pixel electrode 259. The second gate 252 is electrically connected to the second scan line SL2(n), the second semiconductor layer 254 is located above the second gate 252, and the second source 256 and the second drain 258 are at least partially located in the second semiconductor. The layer 254 and the second source 256 are electrically connected to the data line DL(m).

In this embodiment, the first gate 242, the second gate 252, the first scan line SL1(n), and the second scan line SL2(n) are, for example, elements patterned by the first metal layer, and The first source 246, the second source 256, the first drain 248, the second drain 258, and the data line DL(m) are, for example, elements patterned from the second metal layer. Once the patterning process of the first metal layer and the second metal layer occurs, the accuracy of the alignment is inaccurate, and the elements patterned by the two metal layers are shifted in relative positions. As a result, the overlapping area between the gates 242, 252 and the sources 246, 256 may vary to affect the element characteristics of the pixels 230a, 230b. In other words, the difference in gate-source parasitic capacitance mentioned in the prior art makes the pixel array substrate susceptible to display brightness unevenness during display.

Therefore, in order to avoid the problem of uneven display brightness, the first compensation structure 260 and the second compensation structure 270 are designed for the first pixel 230a and the second pixel 230b in the pixel array substrate 200, respectively. The concept is as follows. The first compensation structure 260 is located on the second side 221b of the corresponding data line DL(m). In other words, the first compensation structure 260 and the first active component 240 are located on opposite sides of the corresponding data line DL(m). The first compensation structure 260 includes a first conductor pattern 262 and a first semiconductor pattern 264 and a first source compensation pattern 266. The first conductor pattern 262 is connected to the first scan line SL1(n), the first semiconductor pattern 264 is located above the first conductor pattern 262, and the first source compensation pattern 266 is at least partially located on the first semiconductor pattern 262 and is connected to the data line. DL (m) is electrically connected. In the present embodiment, the first conductor pattern 262 is integrally formed, for example, with the first scan line SL1(n), and the first source compensation pattern 266 is formed integrally with the data line DL(m), for example. Specifically, the first conductor pattern 262 is, for example, an element patterned by the first metal layer described above, and the first source compensation pattern 266 is, for example, an element patterned by the second metal layer described above. Moreover, in the embodiment, the range of the region in which the first semiconductor pattern 264 is beyond the first conductor pattern 262 is taken as an example, but in other embodiments, the first semiconductor pattern 264 may also be located in the region of the first conductor pattern 262. Within the scope.

The second compensation structure 270 is located on the first side 221a of the corresponding data line DL(m). In other words, the second compensation structure 270 and the second active element 250 are located on opposite sides of the corresponding data line DL(m). The second compensation structure 270 includes a second conductor pattern 272, a second semiconductor pattern 274, and a second source compensation pattern 276. The second conductor pattern 272 is connected to the second scan line SL2(n), the second semiconductor pattern 274 is located above the second conductor pattern 272, and the second source compensation pattern 276 is at least partially located on the second conductor pattern 272 and is connected to the data line. DL (m) is electrically connected. In the present embodiment, the second conductor pattern 272 is integrally formed, for example, with the second scan line SL2(n), and the second source compensation pattern 276 is integrally formed, for example, with the data line DL(m). Specifically, the second conductor pattern 272 is, for example, an element patterned from a first metal layer, and the second source compensation pattern 276 is, for example, a second metal layer pattern. The components of the case. Moreover, in the embodiment, the range of the region in which the second semiconductor pattern 274 is beyond the second conductor pattern 272 is taken as an example, but in other embodiments, the second semiconductor pattern 274 may also be located in the region of the second conductor pattern 272. Within the scope. As shown in FIG. 2C and FIG. 2D, the pixel array substrate 200 further includes a gate dielectric layer 210 and a protective layer 220. The gate dielectric layer 210 is formed on the substrate 201, and covers the gates 242 and 252 and the scan line SL1(n). SL1(n+1), SL1(n+2), SL2(n-1), SL2(n), SL2(n+1), and conductor patterns 262, 272. The protective layer 220 is formed on the substrate 201 and covers the scan lines SL1(n), SL1(n+1), SL1(n+2), SL2(n-1), SL2(n), and SL2(n+1). Data lines DL(m-1), DL(m), DL(m+1), active devices 240, 250, gate dielectric layer 210, and compensation structures 260, 270. In addition, the pixel electrodes 249, 259 are electrically connected to the drains 248, 258 by the contact windows 222, 223 in the protective layer 220.

It is assumed that the relative positions of the elements in the pixel array substrate 200 should be as shown in the solid line portion of FIG. 2B. However, a registration error occurs in the patterned alignment step causing the second metal layer to shift in direction D, thus the data line DL(m) and the source 246, 256 are opposite to the gate 242, 252. The positional relationship and source compensation patterns 266, 276 are actually depicted as dashed lines with respect to the conductor patterns 262, 272. That is, the data line DL(m), the source 246, 256, and the drain 248, 258 are integrally translated relative to the gate 242, 252 toward the left side of the drawing, that is, the direction D. The area of the first source 246 overlapping the first gate 242 is thus increased and the area of the first source compensation pattern 266 overlapping the first conductor pattern 262 is reduced. The area of the second source 256 overlapping the second gate 252 is thus reduced and the second The area over which the source compensation pattern 276 overlaps the second conductor pattern 272 increases.

In the present embodiment, the first source 246 has a first width W1, that is, the width of the first source 246 at the boundary of the first gate 242 is W1, and the first source compensation pattern 266 has a The second width W2, that is, the width at which the first source compensation pattern 266 is aligned with the boundary of the first conductor pattern 262 is W2. For the consistency of the sum of the gate-source parasitic capacitance and the conductor pattern-source compensation pattern parasitic capacitance, the width of the first source 246 at the boundary with the first gate 242 is substantially equal to the first source compensation. The width of the pattern 266 at the boundary of the first conductor pattern 262, that is, the first width W1 is substantially equal to the second width W2. As such, the overlapping area of the first source 246 and the first gate 242 and the overlapping area of the first source compensation pattern 266 and the first conductor pattern 262 will be similar or even the same as the predetermined pattern design.

Similarly, in the embodiment, the second source 256 has a third width W3, that is, the width of the second source 256 and the second gate 252 are W3, and the second source compensation pattern 276. For example, it has a fourth width W4, that is, a width at which the second source compensation pattern 276 is aligned with the boundary of the second conductor pattern 272 is W4. For the consistency of the sum of the gate-source parasitic capacitance and the conductor pattern-source compensation pattern parasitic capacitance, the width at which the second source 256 is aligned with the second gate 252 is substantially equal to the second source compensation. The width of the pattern 276 at the boundary with the second conductor pattern 272, that is, the third width W3 is substantially equal to the fourth width W4. In this way, the overlapping area of the second source 256 and the second gate 252 and the second source complement The sum of the overlapping areas of the compensation pattern 276 and the second conductor pattern 272 will be similar or even identical to the predetermined pattern design.

With such a pattern design, the present embodiment can maintain the quality of the pixel array substrate 200. The pixel array substrate 200 still has a preset quality even if the process alignment accuracy is not ideal. It is worth mentioning that when the alignment offset in the process step is the deviation direction D, the design of the first compensation structure 260 and the second compensation structure 270 still helps to compensate for the change and maintenance of the gate-source parasitic capacitance. The gate-source parasitic capacitance is constant, such that the total resistance-capacitance effect (RC effect) value on the first scan line and the total resistance-capacitance effect (RC effect) value on the second scan line are the same. In short, the design of the present embodiment can avoid the negative influence on the device characteristics caused by the alignment shift in the parallel or deviating direction D, so that the pixel array substrate 200 has a fairly good quality and yield.

It is worth mentioning that the length of the first conductor pattern 262 and the second conductor pattern 272 in the parallel direction D is preferably greater than or at least equal to an error that may occur in the alignment step in the patterning process. As a result, the error of the alignment step can compensate for the displacement of the gates 242, 252 and the sources 246, 256 in the parallel direction D or the deviation direction D without causing a defect in the pixel array substrate 200. In addition, under the alignment error, the first source compensation pattern 266 and the second source compensation pattern 276 of the present embodiment are not protruded from the first conductor pattern 262 and the second conductor pattern 272, for example, to ensure compensation. Gate-source parasitic capacitance change. Furthermore, although the present embodiment is exemplified by a strip-shaped source 246, as shown in FIGS. 3A and 3B, in the pixel array substrate 200a, the source electrode 246 may have a horseshoe-shaped structure. among them, The constituent elements of the pixel array substrate 200a are substantially the same as those of the pixel array substrate 200 and are denoted by the same reference numerals, and thus will not be described herein.

Generally, in a pixel array substrate having a double gate design, since the pixels are input to the pixels on both sides by the same data line, a relative offset occurs between the first conductor layer and the second conductor layer. When the pixels on both sides of the same data line have opposite increases and decreases in the gate-source parasitic capacitance, for example, the gate-source parasitic capacitance of the pixel structure in odd rows will As they become larger together, the gate-source parasitic capacitance of the pixel structure in even rows will become smaller together, and vice versa. As a result, the display screen will have corresponding changes, which will make the defects on the display screen more obvious.

However, in the present embodiment, the gates 242, 252 and the sources 246, 256 are disposed on one side of the data line DL(m), and the gate 242 is disposed on the other side of the same scanning line DL(m). , 252 and source 246, 256 corresponding conductor patterns 262, 272 and source compensation patterns 266, 276. Therefore, in the process of fabricating the pixel structure, the relative offset between the first conductor layer and the second conductor layer does not affect the overlap area between the source 246 and the gate 242 and the source compensation pattern 266 and the conductor pattern. The sum of the overlap areas between 262, and the overlap area between source 256 and gate 252 and the sum of the overlap areas between source compensation pattern 276 and conductor pattern 272. That is, the sum of the gate-source parasitic capacitance and the parasitic capacitance of the conductor pattern-source compensation pattern is constant. That is to say, the conductor pattern-source compensation pattern parasitic capacitance can compensate for the variation of the gate-source parasitic capacitance, so that the parasitic capacitance on the scan line is always constant. In addition, due to the quality of the signal transmission of the scan line Since the resistance-capacitance effect (R-C effect) is related, the scanning line can maintain a uniform RC value while maintaining the parasitic capacitance of the scanning line in a uniform state, so that the pixel array substrate has better display quality. Therefore, the pixel array substrate of the present invention does not adversely affect the display effect due to the alignment error on the process. In other words, the pixel array substrate of the present invention has good quality and product yield.

4A is a schematic diagram of a pixel array substrate according to a second embodiment of the present invention, and FIG. 4B is a schematic diagram of the first pixel 230a and the second pixel 230b of FIG. 4A. For convenience of description, only two pixel columns C _n and C _{n+1 are} represented in FIG. 4A, and in FIG. 4B, first pixels 230a and second on both sides of the data line DL(m) are shown. The pixel 230b is explained. Referring to FIG. 4A, the constituent elements of the pixel array substrate 300 are substantially the same as those of the pixel array substrate 200. Therefore, the same elements of the pixel array substrate 300 and the pixel array substrate 200 will be denoted by the same reference numerals. In short, the pixel array substrate 300 includes a substrate 301, a plurality of first scan lines SL1(n), SL1(n+1), SL1(n+2), and a plurality of second scan lines SL2(n-1). , SL2(n), SL2(n+1), a plurality of data lines DL(m-1), DL(m), DL(m+1), a plurality of pixels 230a, 230b, and a plurality of first compensation structures 260 and a plurality of second compensation structures 270. It is particularly noted that the pixel array substrate 300 differs from the pixel array substrate 200 in the pattern design of the drain electrodes 248a, 258a, and the pattern design of the gate electrodes 248a, 258a will be described below.

Referring to FIG. 4B, in the present embodiment, the drains 248a, 258a include a comb portion 310 surrounding the source electrodes 246, 256 and a connecting portion 314. For example, the comb portion 310 has a first branch 310a and a second branch 310b. And a strip bottom 310c. That is, the comb portion 310 may be a U-shaped pattern, but the comb portion 310 may also have three or more branches, that is, the comb portion 310 may have two branches, or may have two or two More than one branch. The first branch 310a and the second branch 310b are, for example, protruded in the horizontal direction from both ends of the strip-shaped bottom portion 310c such that the comb portion 310 surrounds the source portions 246, 256. One end of the connecting portion 314 is connected to the strip bottom portion 310c, and the other end protrudes out of the gate electrodes 242, 252 in the horizontal direction. Therefore, the connecting portion 314 partially overlaps the gate electrodes 242, 252.

In the present embodiment, the comb portion 310 and the connecting portion 314 substantially form a fork pattern. That is to say, the bottom of the comb portion 310 is connected to a long connecting portion 314 to form a fork-like pattern. In addition, the connecting portion 314 has a contact portion 316 located at one end of the connecting portion 314 away from the comb portion 310, and the pixel electrodes 249, 259 are electrically connected to the drains 248a, 258a through the contact portion 316. Since the manner in which the pixel electrodes 249, 259 are connected to the contact portion 316 is a technique commonly used in the art, this embodiment will not be further described.

It is worth mentioning that the first branch 310a extends beyond the gates 242, 252 to define a protrusion 312 located outside the gates 242, 252, and the protrusions 312 and the first branches 310a do not extend to Portions other than the gates 242, 252 have the same width. Meanwhile, in such a pattern design, the protruding portion 312 and the connecting portion 314 are respectively located on opposite sides of the gates 242, 252. It is assumed that the relative positions of the elements in the pixel array substrate 300 should be as shown in the solid line portion of FIG. 4B. However, a registration error occurs in the patterned alignment step and the second metal layer is offset in direction D. The positional relationship of the data line DL(m), the source 246, 256, and the drains 248a, 258a with respect to the gates 242, 252 is actually depicted as a dashed line. That is, the data line DL(m), the source 246, 256, and the drain 248a, 258a are integrally translated relative to the gate 242, 252 toward the left side of the drawing, that is, the direction D. As described in the first embodiment, the design of the first compensation structure 260 and the second compensation structure 270 helps to compensate for changes in the gate-source parasitic capacitance, such that the gate-source parasitic capacitance and the conductor pattern-source The sum of the compensation pattern parasitic capacitances remains constant.

Further, in the first pixel 230a of the present embodiment, the area in which the first branch 310a overlaps the gate 242 is thus increased, and the area in which the connection portion 314 is overlapped with the gate 242 is reduced. That is, the area of the projection 312 is reduced by the alignment error. Conversely, in the second pixel 230b, the area of the first branch 310a overlapping the gate 252 is reduced, and the area of the connection portion 314 overlapping the gate 252 is increased. That is, the area of the projection 312 is increased under the alignment error.

In the drain 248a of the present embodiment, the first branch 310a has, for example, a fifth width W5, that is, the width of the convex portion 312 at the boundary with the gate 242 is W5, and the second branch 310b has a sixth width, for example. W6, and the connecting portion 314 has a seventh width W7, that is, a width W7 at which the connecting portion 314 is aligned with the boundary of the gate 242, wherein the protruding portion 312 and the connecting portion 314 on opposite sides of the gate 242 are respectively The position of the gate 242 protrudes beyond the gate 242. Therefore, in order to make the gate-drain parasitic capacitance of the first pixel 230a constant, the width of the convex portion 312 and the gate 242 are substantially equal to the boundary between the connecting portion 314 and the gate 242. The width, that is, the fifth width W5 is substantially equal to the seventh width W7. As a result, the overlap area of the drain 248a and the gate 242 will be similar to the predetermined pattern design, or even the same, to achieve a constant gate-drain parasitic capacitance.

In the drain 258a of the present embodiment, the first branch 310a has, for example, an eighth width W8, that is, the width of the protrusion 312 at the boundary with the gate 252 is W8, and the second branch 310b has a ninth width W9, for example. The connecting portion 314 has a tenth width W10, that is, a width W10 at which the connecting portion 314 is aligned with the boundary of the gate 252, wherein the protruding portion 312 and the connecting portion 314 on opposite sides of the gate 252 are respectively The location of the gate 252 protrudes beyond the gate 252. Therefore, in order to make the gate-drain parasitic capacitance of the second pixel 230b constant, the width at which the protrusion 312 and the gate 252 are aligned is substantially equal to the junction of the connection portion 314 and the gate 252. The width, that is, the eighth width W8 is substantially equal to the tenth width W10. As such, the overlap area of the drain 258a and the gate 252 will be similar to the predetermined pattern design, even the same to achieve a constant gate-drain parasitic capacitance.

In detail, the comb portion 310 and the connecting portion 314 are integrally formed patterns. Therefore, the amount of displacement of the comb portion 310 and the connecting portion 314 with respect to the gates 242, 252 is the same. Therefore, the fifth width W5 is equal to the seventh width W7 such that the overlapping area of the drain 248a and the gate 242 is similar to the predetermined pattern design to maintain the gate-drain parasitic capacitance constancy, and the eighth width W8 is equal to the tenth width. W10 allows the overlap area of the drain 248b and the gate 252 to be similar to a predetermined pattern design to maintain the gate-drain parasitic capacitance constancy.

It is worth mentioning that the length of the protrusion 312 in the parallel direction D is preferably greater than or at least equal to the error that may occur in the alignment step in the patterning process. As a result, the error of the alignment step can compensate for the displacement of the gates 242, 252 and the drains 248a, 258a in the parallel direction D or the deviation direction D without causing a defect in the pixel array substrate 300. In addition, under the alignment error, the second branch 310b of the present embodiment is, for example, not protruded beyond the gates 242, 252 to ensure a constant parasitic capacitance of the gate-drain. Of course, this embodiment is merely an illustration of an embodiment. In order to maintain the constancy of the gate-drain parasitic capacitance, a plurality of pixel structure designs can also be applied. The design of these pixel structures is mainly to make the protrusions and the connecting portions on both sides of the gate have equal or similar values in width so that the pixel array substrate has a desired quality. For example, in one embodiment, the first branch 310a and the second branch 310b of the drain 248a, 258a both protrude beyond the gates 242, 252, and the widths W5, W8, and the second branch of the first branch 310a The widths W6, W9 of the 310b and the widths W7, W10 of the connecting portion 314 are, for example, such that the sum of the width W5 and the width W6 is substantially equal to the width W7 and the sum of the width W8 and the width W9 is substantially equal to the width W10. Furthermore, in order to maintain the stability of the gate-drain parasitic capacitance, in the present embodiment, the first branch 310a and the second branch 310b of the drain are designed to have different lengths and the first branch 310a. The gates 242, 252 are protruded, but the design of the compensation structure of the present invention is also applicable to a pixel structure in which the first branch and the second branch of the drain are the same length and are not protruded from the gate.

In this embodiment, the first compensation structure 260 and the second compensation structure 270 The gate-source parasitic capacitance can be compensated for to maintain a constant sum of the parasitic capacitances of the scan lines, while the pattern design of the drains 248a, 258a can further maintain the gate-drain parasitic capacitance constancy. Therefore, the present embodiment can maintain the quality of the pixel array substrate 300. The pixel array substrate 300 still has a preset quality even if the process alignment accuracy is not ideal. In short, the design of the present embodiment can avoid the negative influence on the device characteristics caused by the alignment shift in the parallel or deviating direction D, so that the pixel array substrate 300 has a fairly good quality and yield. In addition, since the RC value of the scan line is related to the gate-source parasitic capacitance and the gate-drain parasitic capacitance, it can compensate for the gate-source parasitic capacitance change and maintain the gate-drain parasitic capacitance constant. In the state, the scanning lines of the pixel array substrate 300 can have a uniform RC value, so that the pixel array substrate 300 has a better display picture.

In summary, the present invention configures a gate and a source on one side of the data line, and a conductor pattern and a source compensation pattern corresponding to the gate and the source on the other side of the same data line. Therefore, in the process of fabricating the pixel structure, the relative offset between the first conductor layer and the second conductor layer does not affect the overlap area between the gate and the source and the relationship between the conductor pattern and the source compensation pattern. The sum of the overlapping areas. That is, the conductor pattern-source compensation pattern parasitic capacitance can compensate for the variation of the gate-source parasitic capacitance, so that the sum of the gate-source parasitic capacitance and the conductor pattern-source compensation pattern parasitic capacitance is constant. Therefore, the pixel array substrate of the present invention does not have a negative influence on the display effect due to the alignment error on the process. In other words, the pixel array substrate of the present invention has good quality and product yield.

In addition, the pixel array substrate of the present invention can be designed with other energy dimensions. The gate-source parasitic capacitance and the gate-drain parasitic capacitance of the pixel array substrate are maintained constant by a combination of a gate-bungy parasitic capacitance constant pixel structure. In this way, the RC values of the scan lines can be further kept consistent, thereby further providing a better display screen for the pixel array substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 200a, 300‧‧‧ pixel array substrate

130a, 130b, 230a, 230b‧‧‧ pixels

110a, 110b, SL1(n), SL1(n+1), SL1(n+2), SL2(n-1), SL2(n), SL2(n+1)‧‧‧ scan lines

120, DL (m-1), DL (m), DL (m + 1) ‧ ‧ data line

140, 150, 240, 250‧‧‧ active components

142, 152, 242, 252‧‧ ‧ gate

144, 154, 246, 256‧ ‧ source

146, 156, 248, 248a, 258, 258a‧‧ 汲 bungee

201, 301‧‧‧ substrate

210‧‧‧gate dielectric layer

220‧‧‧Protective layer

221a, 221b‧‧‧ side

222, 223‧‧ ‧ contact window

244, 254‧‧‧ semiconductor layer

249, 259‧‧‧ pixel electrodes

260, 270‧ ‧ compensation structure

262, 272‧‧‧ conductor pattern

264, 274‧‧‧ semiconductor pattern

266, 276‧‧‧ source compensation pattern

310‧‧‧ combing department

Branch 310a, 310b‧‧‧

310c‧‧‧ strip bottom

312‧‧‧Protruding

314‧‧‧Connecting Department

316‧‧‧Contacts

C _n , C _n+1 ‧‧‧ pictogram

D‧‧‧ Direction

W1~W10‧‧‧Width

1 is a schematic view of a conventional pixel array substrate.

2A is a schematic view of a pixel array substrate according to a first embodiment of the present invention.

2B is a schematic diagram of the first pixel and the second pixel of FIG. 2A.

2C and 2D are schematic cross-sectional views taken along line A-A' and line B-B' of Fig. 2B, respectively.

3A is a schematic diagram of a pixel array substrate according to another embodiment of the present invention.

FIG. 3B is a schematic diagram of the first pixel and the second pixel of FIG. 3A.

4A is a schematic view of a pixel array substrate according to a second embodiment of the present invention.

4B is a schematic diagram of the first pixel and the second pixel of FIG. 3A.

201‧‧‧Substrate

221a, 221b‧‧‧ side

222, 223‧‧ ‧ contact window

230a, 230b‧‧ ‧ pixels

240, 250‧‧‧ active components

242, 252‧‧ ‧ gate

244, 254‧‧‧ semiconductor layer

246, 256‧‧‧ source

248, 258‧‧‧汲

249, 259‧‧‧ pixel electrodes

260, 270‧ ‧ compensation structure

262, 272‧‧‧ conductor pattern

264, 274‧‧‧ semiconductor pattern

266, 276‧‧‧ source compensation pattern

D‧‧‧ Direction

DL(m)‧‧‧ data line

SL1(n), SL1(n+1), SL2(n-1), SL2(n)‧‧‧ scan lines

W1~W4‧‧‧Width

Claims (15)

A pixel array substrate includes: a substrate; a plurality of first scan lines and a plurality of second scan lines, wherein the first scan lines and the second scan lines are disposed in pairs on the substrate; and a plurality of data lines And vertically intersecting the first scan lines and the second scan lines; the plurality of pixels comprising a plurality of first pixels and a plurality of second pixels, and located in a pair of the first a scan line, a second scan line, and the data lines, wherein the first pixels are connected to the first scan lines and a first side of the data lines, and the second pixels are The second scan lines are connected to a second side of the data lines; a plurality of first compensation structures, each of the first compensation structures is located on the second side of the corresponding data line, and each of the first compensation structures The method includes: a first conductor pattern connected to the first scan line; a first semiconductor pattern located above the first conductor pattern; a first source compensation pattern at least partially located on the first semiconductor pattern and a data line electrical connection; and a plurality of second compensation structures, each of the second complement The second compensation structure includes: a second conductor pattern connected to the second scan line; a second semiconductor pattern located above the second conductor pattern; And a second source compensation pattern at least partially located in the second semiconductor The body pattern is electrically connected to the data line. The pixel array substrate of claim 1, wherein the first pixel comprises a first gate, a first semiconductor layer, a first source, and a first drain, the first gate The pole is electrically connected to the first scan line, the first semiconductor layer is located above the first gate, the first source and the first drain are at least partially located on the first semiconductor layer and the first source Electrically connected to the data line. The pixel array substrate of claim 2, wherein the first source and the first gate have a first width, the first source compensation pattern and the first conductor pattern The boundary is flushed to have a second width that is substantially equal to the second width. The pixel array substrate of claim 1, wherein the second pixel comprises a second gate, a second semiconductor layer, a second drain, and a second source, the second gate The pole is electrically connected to the second scan line, the second semiconductor layer is located above the second gate, the second source and the second drain are at least partially located on the second semiconductor layer and the second source Electrically connected to the data line. The pixel array substrate of claim 4, wherein the second source and the second gate have a third width, the second source compensation pattern and the second conductor pattern The boundary is flushed to have a fourth width that is substantially equal to the fourth width. The pixel array substrate of claim 1, wherein the first conductor patterns are integrally formed with the first scan lines. The pixel array substrate of claim 1, wherein the pixel array substrate The first source compensation patterns are integrally formed with the data lines. The pixel array substrate of claim 1, wherein the second conductor patterns are integrally formed with the second scan lines. The pixel array substrate of claim 1, wherein the second source compensation patterns are integrally formed with the data lines. The pixel array substrate of claim 2, wherein the first drain of each of the first pixels comprises: a comb portion surrounding the first source, the comb portion having at least two branches And at least one of the branches extends beyond the first gate to define at least one protrusion outside the first gate; and a connecting portion extending from the comb portion to the first portion a bump outside, and the protruding portion and the connecting portion are respectively located on opposite sides of the first gate, wherein the protruding portion has a fifth width at a line with the first gate boundary, the connecting portion There is a sixth width that is aligned with the first gate boundary, and the fifth width is substantially equal to the sixth width. The pixel array substrate of claim 10, wherein one of the branches of the comb portion extends beyond the first gate and the other is completely located at the first gate In the region, the number of the at least one protrusion is one. The pixel array substrate of claim 4, wherein the second drain of each of the second pixels comprises: a comb portion surrounding the second source, the comb portion having at least two branches At least one of the branches extending beyond the second gate to define at least one protrusion located outside the second gate; a connecting portion extending from the comb portion to the outside of the second gate, wherein the protruding portion and the connecting portion are respectively located on opposite sides of the second gate, wherein the protruding portion and the second gate The boundary is flushed to have a seventh width, and the connecting portion is aligned with the second gate boundary to have an eighth width, and the seventh width is substantially equal to the eighth width. The pixel array substrate of claim 12, wherein one of the branches of the comb portion extends beyond the second gate, and the other is completely located at the second gate In the region, the number of the at least one protrusion is one. The pixel array substrate of claim 1, wherein the first semiconductor pattern protrudes from the first conductor pattern. The pixel array substrate of claim 1, wherein the second semiconductor pattern protrudes from the second conductor pattern.