WO2011066699A1

WO2011066699A1 - Pixel structure

Info

Publication number: WO2011066699A1
Application number: PCT/CN2009/076055
Authority: WO
Inventors: 柳智忠; 黎昔耀
Original assignee: 深超光电（深圳）有限公司
Priority date: 2009-12-03
Filing date: 2009-12-25
Publication date: 2011-06-09
Also published as: CN101738805A; CN101738805B

Abstract

A pixel structure (100) comprises a scanning line（110）, a data line（120）, a gate electrode（130）, a semiconductor layer（140）, a source electrode（150）, a drain electrode（160）, an extending electrode（170）and a pixel electrode（180）. The scanning line（110）crosses the data line（120） and is electrically insulated from the data line（120）. The gate electrode(130) is electrically connected to the scanning line(110). The semiconductor layer(140) is on the gate electrode(130). The source electrode(150) is on the semiconductor pattern(190) and connected to the data line(120). The drain electrode(160) comprises a contacting portion(162), an electrode portion(164) and a connecting portion(166). The contacting portion(162) is outside of the gate electrode(130), and the electrode portion(164) is on the semiconductor pattern(190). The connecting portion(166) extends from the contacting portion(162) along one direction to be connected to the electrode portion(164) and partly overlaps the gate electrode(130). The pixel electrode(180) is connected to the connecting portion(166). The extending electrode(170) is connected to the scanning line(110). One end of the extending electrode(170) is directed to the semiconductor layer(140) along the direction to overlaps the drain electrode(160). A first width of the connecting portion(166) is equal to a second width of the extending electrode(170).

Description

Pixel structure

[Technical Field]

The present invention relates to a pixel structure, and more particularly to a pixel structure having a constant gate-drain parasitic capacitance.

【Background technique】

A general thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate, a pair of substrates, and a liquid crystal layer sandwiched between the two substrates. The thin film transistor array mainly includes a plurality of scan lines, a plurality of data lines, a thin film transistor array arranged between the scan lines and the data lines, and a pixel electrode (Pixel Electrode) corresponding to each thin film transistor, and the thin film transistor includes a gate A pole, a semiconductor layer, a source and a drain, which are used as switching elements of a liquid crystal display unit.

The fabrication process of a thin film transistor array substrate typically involves multiple development and etching steps. In a general manufacturing technique, the gate and scan lines are the first metal layer, and the source, drain and data lines are the second metal layer. Moreover, there is at least one dielectric layer between the first metal layer and the second metal layer. In the structure of the thin film transistor, the gate and the drain at least partially overlap, so that there is usually a so-called gate-drain parasitic capacitance (hereinafter referred to as Cgd) between the gate and the drain.

In the case of a liquid crystal display, there is a specific relationship between the voltage applied to the liquid crystal capacitor Clc and the light transmittance of the liquid crystal molecules. Therefore, as long as the voltage applied to the liquid crystal capacitor Clc is controlled in accordance with the picture to be displayed, the display can be made to display a predetermined picture. However, due to the presence of the gate-drain parasitic capacitance Cgd, the voltage held on the liquid crystal capacitor Clc will change as the signal on the data wiring changes. This voltage variation is called the feed-through voltage Δ Vp , which can be expressed as equation (1):

Δ Vp = [Cgd / (Clc + Cgd + Cst)] (Vgon - Vgoff) (1) where Vgon - Vgoff is the amplitude of the pulse voltage applied to the scanning line, and Cst is the storage capacitance. In the current active component array fabrication process, the amount of displacement deviation when the machine is moving will result in a difference in the relative positions of the various components. In particular, when the overlapping area of the gate and the drain is different, the gate-drain parasitic capacitance Cgd is made different. In this way, different display pixels have different feedthrough voltages A Vp , which in turn causes a problem of display brightness unevenness during display. That is, maintaining the constancy of the gate-drain parasitic capacitance Cgd is a goal that the active device array layout has always desired.

[Summary of the Invention]

The present invention provides a pixel structure in which the gate-drain parasitic capacitance does not float under process error. The present invention provides a pixel structure including a scan line, a data line, a gate, a semiconductor layer, a source, a drain, an extension electrode, and a pixel electrode. The scan lines and the data lines are staggered and electrically insulated from each other. The gate is electrically connected to the scan line. The semiconductor layer is above the gate. The source and the drain are both at least on the semiconductor pattern, and the source is connected to the data line. The drain includes a contact portion, an electrode portion, and a connection portion. The contact portion is located outside the gate electrode, and the electrode portion is located on the semiconductor pattern. The connecting portion is extended by the contact portion in one direction to be connected to the electrode portion and overlap the gate portion. The connecting portion has a first width. The extension electrode is connected to the scan line, and one end of the extension electrode is directed to the semiconductor layer in the above direction and overlaps the drain. The extension electrode has a second width and the first width is substantially equal to the second width. The pixel electrode is connected to the contact portion of the drain.

In an embodiment of the invention, the pixel structure further includes a semiconductor pattern. The semiconductor pattern is disposed, for example, between the extension electrode and the drain and is located in the overlap region of the extension electrode and the drain.

In an embodiment of the invention, one end of the extending electrode away from the end is connected to the scan line. For example, the shape of the extension electrode may be L-shaped. In addition, the extension electrode may also be substantially U-shaped.

In an embodiment of the invention, the electrode portion of the drain is a U-shaped portion surrounding the source, and the U-shaped portion has a bottom portion and two branches extending perpendicularly from both ends of the bottom portion. At this time, the connection portion of the drain is connected to the bottom of the U-shaped portion or one of the branches.

In an embodiment of the invention, the source may also be a U-type source, and the U-type source surrounds the electrode portion of the drain. When the source is extremely U-shaped, the electrode portion of the drain is connected to the connecting portion to form a long bar graph. Case.

In an embodiment of the invention, the drain further includes a protruding portion, and the contact portion is located between the connecting portion and the protruding portion, and the protruding portion overlaps the extending electrode in parallel with the extending direction.

In an embodiment of the invention, the drain further includes a protrusion that overlaps the edge of the gate without overlapping the gate, and the protrusion is connected to the contact portion to overlap the extension electrode.

In an embodiment of the invention, the drain is integrally formed.

In an embodiment of the invention, the source and the data line are integrally formed.

In an embodiment of the invention, the gate is located in the scan line. Therefore, the extension electrode can be connected to the gate.

In an embodiment of the invention, the gate is protruded from the scan line.

Based on the above, the present invention configures an extension electrode connected to the scan line or the gate, and the end of the extension electrode overlaps with the drain. Therefore, when the relative positions of the gate and the drain are shifted due to the alignment error in the manufacturing process, the gate-drain parasitic capacitance is still the same as the predetermined layout. As a result, the pixel structure of the present invention has high tolerance to process errors and stable quality.

The above described features and advantages of the invention will be apparent from the description and appended claims.

[Description of the Drawings]

1 is a partial top plan view of a pixel structure according to a first embodiment of the present invention.

2 is a partial top plan view of a pixel structure according to a second embodiment of the present invention.

3 is a partial top plan view of a pixel structure according to a third embodiment of the present invention.

4 is a partial top plan view of a pixel structure according to a fourth embodiment of the present invention.

FIG. 5 is a partial top plan view of a pixel structure according to a fifth embodiment of the present invention.

【detailed description】

1 is a partial top plan view of a pixel structure according to a first embodiment of the present invention. Referring to FIG. 1 , the pixel structure 100 includes a scan line 110 , a data line 120 , a gate 130 , and a semiconductor layer 140 . A source 150, a drain 160, an extension electrode 170, and a pixel electrode 180. The scan lines 110 and the data lines 120 are staggered and electrically insulated from each other. The gate 130 is electrically connected to the scan line 110. The semiconductor layer 140 is located above the gate 130. The source 150 and the drain 160 are both located on at least the semiconductor pattern 140, and the source 150 is connected to the data line 120. The extension electrode 170 is connected to the scan line 110, and the pixel electrode 180 is electrically connected to the drain 160. In addition, the pixel structure 100 further includes a semiconductor pattern 190. The semiconductor pattern 190 is disposed, for example, between the extension electrode 170 and the drain 160 and is located in a region where the extension electrode 170 and the drain 160 overlap. The gate electrode 130, the semiconductor layer 140, the source electrode 150, and the drain electrode 160 collectively constitute a thin film transistor TFT. When the pixel structure 100 displays a picture, the turning on of the thin film transistor TFT can transfer a signal on the data line 120 to the pixel electrode 180.

The drain 160 of this embodiment includes a contact portion 162, an electrode portion 164, and a connection portion 166. The contact portion 162 is located outside the gate 130, and the electrode portion 164 is located on the semiconductor pattern 140. The connecting portion 166 extends in a direction D by the contact portion 162 to be connected to the electrode portion 164 and partially overlap the gate electrode 130. In the present embodiment, the contact portion 162 is, for example, a portion where the drain electrode 160 is in contact with the pixel electrode 180, and the electrode portion 164 is, for example, a portion above the gate electrode 130 in contact with the semiconductor layer 140. In addition, a specific spacing is maintained between the electrode portion 164 and the source 150 to provide good operating efficiency of the thin film transistor TFT.

In this embodiment, the gate 130 and the extension electrode 170 are directly protruded from the scan line 110, so that the scan line 110, the gate 130 and the extension electrode 170 are electrically connected to each other. Generally, in the process of fabricating the pixel structure 100, the scan line 110, the gate 130 and the extension electrode 170 are patterned by a first metal layer, and the data line 120, the source 150 and the drain 160 are formed by a The second metal layer is patterned. In addition, it should be understood by those skilled in the art that at least one insulating layer (not shown) is additionally disposed between the first metal layer and the second metal layer and between the second metal layer and the pixel electrode 180. To maintain the electrical characteristics of each of the elements in the pixel structure 100.

In particular, the first metal layer and the second metal layer are patterned by a development etching process using different masks to form corresponding elements. Therefore, the relative positions of the scan lines 110, the gate electrodes 130, and the extension electrodes 170 are not changed by process errors. Similarly, the relative positions of the data line 120, the source 150, and the drain 160 are not changed by process errors. However, when the alignment step of the photolithography etching process occurs, an error occurs. The difference will cause the relative positions of the gate 130 and the drain 160 to change. That is, the error of the alignment step causes the relative positions of the gate 130 and the drain 160 to deviate from the preset layout. As a result, the area where the gate 130 overlaps the drain 160 will be different from the preset value, that is, the gate-drain parasitic capacitance will not be maintained constant. It is known from the prior art that the floating of the gate-drain parasitic capacitance has a negative influence on the display effect of the pixel structure 100. Therefore, the pixel structure 100 of the present embodiment has the extension electrode 170 to help maintain the constancy of the gate-drain parasitic capacitance.

Specifically, the relationship between the extension electrode 170 and the drain electrode 160 of the present embodiment is as follows. An end 172 of the extension electrode 170 is directed in the direction D toward the semiconductor layer 130 and overlaps the contact portion 162 of the drain 160. The extension electrode 170 is substantially L-shaped, and the extension electrode 170 is directly connected to the scan line 110 away from the other end 174 of the end 172, so the extension electrode 170 has the same potential as the scan line 110 or the gate 130. Since the extension electrode 170 is connected to the scan line 110 to electrically connect the gate 130 and the semiconductor pattern 190 is sandwiched between the extension electrode 170 and the contact portion 162, the capacitance between the extension electrode 170 and the drain 160 is substantially equivalent to the gate 130. The interaction with the drain 160. Therefore, the gate-drain parasitic capacitance in the pixel structure 100 is determined by the overlapping area of the extension electrode 170 and the contact portion 162 and the overlapping area of the gate electrode 130 and the drain electrode 160.

During the fabrication of the pixel structure 100, the alignment error causes the drain 160 to translate relative to the gate 130 in the direction D or away from the direction D. If the drain 160 moves in the direction D, the overlapping area of the connecting portion 166 and the gate 130 increases. At the same time, the contact portion 162 also moves closer to the gate 130 in the direction D. Therefore, the overlapping area of the contact portion 162 and the extension electrode 170 is reduced. In the present embodiment, the connecting portion 166 has a first width W1, and the end 172 of the extending electrode 170 has a second width W2, and the first width W1 is substantially equal to the second width W2. Therefore, under such a design, even if a registration error occurs in the process, the overlapping area of the extension electrode 170 and the contact portion 162 and the sum of the overlapping areas of the gate electrode 130 and the drain electrode 160 remain unchanged. That is, the gate-drain parasitic capacitance in the pixel structure 100 can still be maintained constant.

Specifically, in the present embodiment, the first width W1 is substantially equal to the second width W2. Therefore, under the alignment error, the increase in the area of overlap between the connection portion 166 and the gate electrode 130 can be substantially equal to the contact. The amount by which the portion 162 overlaps with the extension electrode 170 is reduced. Similarly, the alignment error causes the drain 160 to translate away from the direction D relative to the gate 130, and the amount of reduction in the area of overlap of the connection portion 166 with the gate 130 may be substantially equal to the amount of increase in the area of overlap of the contact portion 162 with the extension electrode 170. With such a design, the gate-drain parasitic capacitance in the pixel structure 100 is equal to a predetermined value after the registration error occurs. That is to say, the total area of the drain 160 overlapping the gate 130 and the extension electrode 170 is not changed by the alignment error. Therefore, the pixel structure 100 has a large tolerance to process errors and also has good quality.

The thin film transistor TFT of the above embodiment is only one design of the present invention. For example, in the present embodiment, the drain electrode 160 of the thin film transistor TFT has a U-shaped electrode portion 164, and the source 150 has an L shape. One end of the L-shaped source 150 is connected to the data line 120, and the other end is surrounded by the U-shaped electrode portion 164. Specifically, the U-shaped electrode portion 164 has a bottom portion 164a and two branches 164b and 164c extending perpendicularly from both ends of the bottom portion 164a. Further, one end of the connecting portion 166 is connected to one of the branches 164c. In other embodiments, the thin film transistor TFT may be arranged in other ways as described below, but the present invention is not limited thereto.

2 is a partial top plan view of a pixel structure according to a second embodiment of the present invention. Referring to Fig. 2, the pixel structure 200 is similar to the pixel structure 100 described above, so that the same component symbols in Fig. 1 and Fig. 2 denote the same components. Specifically, the difference between the two is the design of the source 250 and the drain 260. In particular, the drain 260 of the pixel structure 200 also has a U-shaped electrode portion 264. However, the difference from the foregoing embodiment is that in the drain 260, the connection portion 166 is connected to the bottom of the U-shaped electrode portion 264. Further, the source 250 of the present embodiment is, for example, a straight strip shape, and one end of the source 250 is connected to the data line 120 and the other end is surrounded by the U-shaped electrode portion 264.

It is worth mentioning that the extension electrode 170 and the semiconductor pattern 190 are also disposed in the pixel structure 200. The end of the extension electrode 170 is directed to the semiconductor layer 140 in the direction D, and the end of the extension electrode 170 overlaps with the contact portion 162. The semiconductor pattern 190 is sandwiched between the end of the extension electrode 170 and the contact portion 162. Therefore, the capacitive action between the extension electrode 170 and the contact portion 162 is substantially equivalent to the capacitive action between the electrode portion 264 and the gate. In addition, the end of the extension portion 170 is substantially the same as the connection portion 166. The width of the extension portion 170 and the connection portion 166 are respectively located on opposite sides of the contact portion 162, and the gate-drain parasitic capacitance in the thin film transistor TFT is still fixed after the drain electrode 260 is laterally shifted with respect to the gate electrode 130. . That is to say, the quality of the pixel structure 200 is quite good and is not easily adversely affected by process errors.

In addition, FIG. 3 is a partial top plan view of a pixel structure according to a third embodiment of the present invention. Referring to FIG. 3, except for the design of the source 350 and the drain 360 in the pixel structure 300 that is different from the design of the pixel structure 100, the remaining components are the same as the design of the pixel structure 100. Therefore, the same component symbols in Fig. 3 and Fig. 1 also represent the same components.

In particular, pixel structure 300 has a U-shaped source 350. Further, the electrode portion 364 of the drain 360 and the connecting portion 166 constitute an elongated pattern in which the U-shaped source 350 surrounds the electrode portion 364, for example. Actually, the electrode portion 364 and the connecting portion 166 are respectively different portions in the elongated pattern, the electrode portion 364 is a portion where the elongated pattern is surrounded by the source 350, and the connecting portion 166 is in contact with the elongated pattern. Portion 162 extends in direction D to extend to a location within the area where gate 130 is located.

In this embodiment, pixel structure 300 also has a constant gate-drain parasitic capacitance. That is, the present embodiment is also provided with the extension electrode 170 connecting the scan lines 110 and the corresponding semiconductor pattern 190, wherein the extension electrode 170 overlaps the contact portion 162 and the semiconductor pattern 190 is located in this overlap region. Further, the first width W1 of the connecting portion 166 is equal to the second width W2 of the end of the extension electrode 170. Therefore, when the relative positions of the gate 130 and the drain 360 are changed, the overlapping area of the drain 360 and the extension pattern 170 and the overlapping area of the drain 360 and the gate 130 are changed. In this way, even if a registration error occurs during the manufacturing process, the pixel structure 300 has the same operational efficiency as the preset layout, that is, the gate-drain parasitic capacitance is still the same as the preset layout. Therefore, the pixel structure 300 has a large process error tolerance and the quality is relatively easy to control.

Still further, FIG. 4 is a partial top plan view of a pixel structure according to a fourth embodiment of the present invention. Referring to FIG. 4, the design of the pixel structure 400 is extended by the design of the pixel structure 300. Therefore, the same component symbols in pixel structure 300 and pixel structure 400 represent the same components. Specifically, in order to maintain the constancy of the gate-drain parasitic capacitance, the drain 460 of the pixel structure 400 further includes a protrusion. Department 468. The contact portion 162 is located between the connecting portion 166 and the protruding portion 468. It is worth mentioning that in the present embodiment, the protruding portion 468 overlaps the extension electrode 170 in the parallel direction D.

That is, this embodiment extends the drain 460 away from the side of the connection portion 166 to form a protrusion 468 overlapping the extension electrode 170 to maintain a constant gate-drain parasitic capacitance. In addition, in order to ensure that the parasitic capacitance between the gate 130 and the drain 460 does not change under the alignment error, the protrusion 468 of the embodiment has a third width W3, and the third width W3 is at least equal to or greater than The second width W2. That is to say, under any conditions, the end of the extension electrode 170 is completely shielded by the projection 468 in the line width direction. As a result, the pixel structure 400 can have good quality and the tolerance for alignment errors is also greatly improved.

The above embodiments are all described with an L-shaped extension electrode. However, the shape of the extension electrodes can also vary with different pixel structure designs. For example, FIG. 5 is a partial top plan view of a pixel structure according to a fifth embodiment of the present invention. Referring to FIG. 5 , the pixel structure 500 includes a scan line 510 , a data line 120 , a gate 530 , a semiconductor layer 140 , a source 550 , a drain 560 , an extension electrode 570 , a pixel electrode 180 , and a Semiconductor pattern 190. The scan lines 510 and the data lines 120 are staggered and electrically insulated from each other. Gate 530 is substantially a portion of scan line 510. The semiconductor layer 140 is located above the gate 530. Both the source 550 and the drain 560 are located on at least the semiconductor pattern 140, and the source 550 is connected to the data line 120. The extension electrode 570 is connected to the scan line 510, and the extension electrode 570 is substantially extended by the position of the gate 530. In other words, the extension electrode 570 of the present embodiment is connected to the gate 530. The pixel electrode 180 is connected to the drain 560. In addition, the semiconductor pattern 190 is disposed, for example, between the extension electrode 570 and the drain 560 and in an overlapping region of the extension electrode 570 and the drain 560.

Specifically, the extension electrode 570 of the present embodiment is, for example, U-shaped, one end of which is connected to the gate 530 and the other end of which is not connected to other components. The drain 560 includes a contact portion 562, an electrode portion 564, a connecting portion 566, and a projection portion 568.

The contact portion 562 is located outside the scan line 510 and the gate 530. The electrode portion 564 is located on the semiconductor layer 140, and the electrode portion 564 is surrounded by the U-shaped source 550. The connection portion 566 is partially located outside the gate 530 and extends in the direction D by the contact portion 562 to be connected to the electrode portion 564. Projection portion 568 parallel gate The edge of 530 does not overlap with gate 530, and protrusion 568 is coupled to contact portion 562 to overlap extension electrode 570.

In the present embodiment, the extension electrode 570 has an end 572 that is not connected to any of the elements, and the end 572 is directed in the direction D toward the semiconductor layer 140 to overlap the protrusion 568 of the drain 560. When an error occurs in the alignment step in the direction D or away from the direction D, the relative positions of the gate 530 and the drain 560 are pulled closer or farther. When the relative positions of the gate 530 and the drain 560 are brought closer, the overlapping area of the connection portion 566 of the drain 560 and the gate 530 is increased. At this time, the overlapping area of the projections 568 and the extension electrodes 570 is reduced. On the contrary, when the relative positions of the gate 530 and the drain 560 are extended, the overlapping area of the connecting portion 566 and the gate 530 is reduced, and the overlapping area of the protruding portion 568 and the extending electrode 570 is increased.

Here, the extension electrode 570 is electrically connected to the gate 530, so the capacitance between the extension electrode 570 and the protrusion 568 is substantially equal to the capacitance between the connection portion 566 and the gate 530. Based on such a relationship, whether or not the gate-drain parasitic capacitance in the pixel structure 500 is changed may be determined by whether the overlapping area of the extension electrode 570 and the protrusion 568 and the overlapping area of the connection portion 566 and the gate 530 are changed. Therefore, in order to maintain the overlapping area of the gate 530 and the drain 560, a first width W1 of the connecting portion 566 is substantially equal to a second width W2 of the end 572. As a result, when the alignment error occurs during the fabrication of the pixel structure 500 and the relative positions of the gate 530 and the drain 560 are changed, the total area of the drain 560 overlapping the gate 530 and the extension electrode 570 does not change. Therefore, the gate-drain parasitic capacitance of the pixel structure 500 is constant and is not affected by process errors. Moreover, the pixel structure 500 has good quality and stable component characteristics.

In summary, the present invention configures an extension electrode electrically connected to the gate in the pixel structure, and the extension electrode overlaps the drain. Further, a portion where the extension electrode overlaps the drain is located on a side of the drain away from the gate. Therefore, in the process of fabricating the pixel structure, if a registration error occurs, the total area of the drain overlapping the gate and the extended electrode remains constant, so that the gate-drain parasitic capacitance in the pixel structure is not aligned. Change with error. As a result, the pixel structure has good quality, and the problem of flickering of the screen is not easily generated in the application of the display. In addition, the tolerance of the pixel structure of the present invention to the alignment error can be greatly improved. The present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims.

Claims

Rights request

1. A pixel structure comprising:

a scan line and a data line interlaced and electrically insulated from each other;

a gate electrically connected to the scan line;

a semiconductor layer located above the gate;

a source, at least on the semiconductor pattern and connected to the data line;

a drain, at least on the semiconductor pattern, the drain comprising:

a contact portion located outside the gate;

An electrode portion located on the semiconductor pattern;

a connecting portion extending from the contact portion in a direction to be connected to the electrode portion and overlapping the gate portion, and the connecting portion has a first width;

An extension electrode is connected to the scan line, and an end of the extension electrode is directed to and overlaps the semiconductor layer in the direction, and the extension electrode has a second width, and the first width is equal to the second width ; as well as

A pixel electrode is connected to the contact portion of the drain.

2. The pixel structure as claimed in claim 1, further comprising a semiconductor pattern disposed between the extension electrode and the drain and located at an overlapping region of the extension electrode and the drain.

3. The pixel structure according to claim 1, wherein an end of the extension electrode away from the end is connected to the scan line.

4. The pixel structure according to claim 3, wherein the extension electrode has an L shape.

5. The pixel structure of claim 3, wherein the extension electrode is U-shaped.

6. The pixel structure of claim 1, wherein the electrode portion of the drain is a U-shaped portion to surround the source, and the U-shaped portion has a bottom and two vertically extending from both ends of the bottom portion. Branch.

7. The pixel structure of claim 6, wherein the connection portion of the drain is connected to the U-type The bottom or one of the branches of the part.

8. The pixel structure of claim 1, wherein the source is a U-type source, and the U-type source surrounds the electrode portion of the drain.

9. The pixel structure according to claim 7, wherein the electrode portion of the drain is connected to the connecting portion in an elongated pattern.

10. The pixel structure as claimed in claim 1, wherein the drain further comprises a protrusion, the contact portion is located between the connecting portion and the protruding portion, and the protruding portion is parallel to the direction and the extension The electrodes overlap.

11. The pixel structure as claimed in claim 1, wherein the drain further comprises a protrusion parallel to an edge of the gate without overlapping the gate, and the protrusion is connected to the contact portion The extension electrodes overlap.

12. The pixel structure of claim 1 wherein the drain is integrally formed.

13. The pixel structure of claim 1, wherein the source and the data line are integrated

14. The pixel structure of claim 1 wherein the gate is located in the scan line.

15. The pixel structure of claim 14, wherein the extension electrode is connected to the gate,

16. The pixel structure of claim 1, wherein the gate is protruded from the scan line.