KR102596383B1 - Display Device - Google Patents

Abstract

This specification provides a display device including a substrate including a display area and a non-display area and signal lines arranged on the substrate. The signal line includes a first conductive layer connected to the pad and a second conductive layer spaced apart from the first conductive layer. In addition, the signal line is located on the first conductive layer and the second conductive layer, and has an exposed opening area between the end of the first conductive layer and the end of the second conductive layer and between the first conductive layer and the second conductive layer. It includes an insulating layer containing. The signal line is located in the opening area and includes a conductive pattern located on an end of the first conductive layer and an end of the second conductive layer exposed by the opening area.

Description

Display Device

This specification relates to a display device that displays images.

As the information society develops, the demand for display devices to display images is increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting devices have been developed. Various display devices such as OLED (Organic Light Emitting Diode Display Device) are being used.

Generally, a display device includes a driving circuit for driving a display panel. The driving circuit includes a gate driver that sequentially applies scan signals to the gate lines, and a data driver that applies image information to the pixels through data lines in response to the scan signals of the gate driver.

Recently, the resolution of display devices has been increasing in accordance with technological advancements and consumer demands. In addition, the increase in resolution may result in poor contact of the inspection pin when inspecting the signal line due to the addition of Auto-Prove (AP) inspection pins and the reduction of the pin-to-pin (PIN to PIN) pitch. You can.

Additionally, as resolution increases, heat generation increases in signal lines and pads, which may cause abnormal operation of the display device. Accordingly, there is a need for a method to eliminate problems caused by heat generation and minimize costs.

One embodiment is intended to provide a display device that prevents poor contact of inspection pins when inspecting signal lines.

In addition, in another embodiment, the present invention seeks to provide a display device that reduces power consumption and heat generation by lowering the resistance of signal lines and their pads.

In one aspect, a display device according to an embodiment includes a substrate including a display area and a non-display area and signal lines arranged on the substrate.

The signal line includes a first conductive layer connected to the pad and a second conductive layer spaced apart from the first conductive layer. In addition, the signal line is located on the first conductive layer and the second conductive layer, and includes an open area exposed between the end of the first conductive layer and the end of the second conductive layer, and between the first conductive layer and the second conductive layer. It includes an insulating layer. The signal line is located in the opening area and includes a conductive pattern located on an end of the first conductive layer and an end of the second conductive layer exposed by the opening area.

In another aspect, a display device according to another embodiment includes a substrate including a display area and a non-display area, a log line arranged on the substrate, and a connection line connecting the log line to a driving circuit.

The log line includes a conductive layer connected to the pad and an insulating layer located on the conductive layer. The insulating layer includes a first insulating layer including a first contact hole exposing a portion of the conductive layer, and a second contact hole located on the first insulating layer and exposing a portion of the first contact hole and the connection line. Includes a second insulating layer.

The log line includes a connection pattern located on a portion of a conductive layer and a connection line in the first contact hole and the second contact hole.

The display device according to one embodiment can prevent poor contact of inspection pins when inspecting signal lines.

Additionally, a display device according to another embodiment can reduce power consumption and heat generation by lowering the resistance of the signal line and its pad.

1 is a schematic configuration diagram of a display device according to the present embodiments.
FIG. 2 is a diagram schematically showing a portion of the display device of FIG. 1.
FIG. 3 is a diagram showing area X of FIG. 2 in detail.
FIG. 4 is a cross-sectional view taken along line A-A' of FIG. 3.
Figure 5 is a cross-sectional view taken along the indicator line B-B' in Figure 3.
FIG. 6 is a cross-sectional view taken along line C-C' of FIG. 3.
FIG. 7 is a diagram showing the Z region of FIG. 2 in detail.
FIG. 8 is a cross-sectional view taken along the indicator line E-E' of FIG. 7.
FIG. 9 is a diagram showing the Y area of FIG. 2 in detail.
Figure 10 is a cross-sectional view taken along the indicator line DD' in Figure 9.
Figure 11 is a cross-sectional view of the display device when the display device is a liquid crystal display device integrated with a touch screen panel.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

1 is a schematic configuration diagram of a display device according to the present embodiments.

Referring to FIG. 1, display devices according to the present embodiments include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode display device (OLED). ), etc. may be various display devices.

In the display device according to the present embodiments, a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm) intersect, and a thin film transistor (TFT) for driving a pixel (P) is installed at the intersection portion. A display panel 100 formed, a gate driver 110 for supplying scan signals to gate lines GL1 to GLn, and a data driver 120 for supplying data to data lines DL1 to DLm, It may include a timing controller 130 that controls the gate driver 110 and data driver 120.

The gate driver 110 may supply a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 130. A plurality of scan signals can sequentially enable a plurality of gate lines (GL1 to GLn) for a period of one horizontal synchronization signal. The gate driver 110 may include a plurality of gate driver integrated circuits.

The data driver 120 generates a plurality of pixel data voltages in response to data control signals (DCS) from the timing controller 130 whenever one of the plurality of gate lines GL1 to GLn is enabled. It can be supplied to a plurality of data lines (DL1 to DLm) on the display panel 100, respectively. The data driver 120 may include a plurality of data driver integrated circuits.

The timing controller 130 controls synchronization signals (Vsync, Hsync) supplied from an external system (for example, a graphics module of a computer system or an image demodulation module of a television reception system, not shown) and data enable ( A gate control signal (GCS) that controls the gate driver 110 and a data control signal (DCS) that controls the data driver 120 are generated using the DE) signal and the clock signal (Clk). Additionally, the timing controller 130 may align image data (Data) input from an external system and supply the sorted data (Vdata) to the data driver 120.

FIG. 2 is a diagram schematically showing a portion of the display device of FIG. 1.

Referring to FIG. 2, the display panel 100 includes a substrate 101 including a display area 104 that displays an image and a non-display area 105 that does not display an image around the display area 104. Includes.

The data printed circuit board 124 is a tab (tape automated bonding) method for connecting the driving circuit to the display panel in the non-display area 105 of the display panel 100, for example, a flexible film or It can be electrically and physically connected through a flexible printed circuit (128).

A data driver integrated circuit 122 constituting the data driver 120 shown in FIG. 1 is mounted on the flexible film 128. The flexible film 128 includes a plurality of data lead lines 126 electrically connected to a plurality of data lines DL and a plurality of gate lead lines electrically connected to the gate driver integrated circuit 111 constituting the gate driver 110 ( 113) may be included.

The plurality of data lead lines 126 are connected to the plurality of data lines DL disposed on the display panel 100 through a pad structure, so that image signals can be transmitted from the data driver integrated circuit 122 to the data lines DL. there is. The gate lead line 113 is connected to the start signal line (SSL) disposed on the display panel 110 through a pad structure and can transmit a start pulse to the gate driver integrated circuit 111.

Additionally, a log line lead wire 114 electrically connected to the log line (LOG) may be connected to the flexible film 128. The plurality of log line lead lines 114 may transmit control signals, clock signals, gate voltage, power voltage, ground voltage, etc. to the gate driver integrated circuit 111 through the log line (LOG).

The gate driver integrated circuit 111 generates a scan signal using control signals supplied through a log line (LOG), a clock signal, gate voltage, power voltage, ground voltage, and a start pulse supplied through a start signal line (SSL). Alternatively, the gate signal may be supplied to the gate lines GL of the display panel 100.

The above-described data line (DL), gate line (GL), log line (LOG), and start signal line (SSL) are referred to as signal lines arranged on the substrate 101. Below, with reference to FIGS. 3 to 5, it is exemplarily explained that the signal line is a data line (DL), and with reference to FIGS. 6 to 10, it is exemplarily explained that the signal line is a log line (LOG). In this specification, the signal line may be any signal line electrically connected to the flexible film 128, for example, a start signal line (SSL) or various power supply lines not shown.

FIG. 3 is a diagram showing area X of FIG. 2 in detail.

Referring to FIG. 3, the data line DL includes a first conductive layer 210 connected to the pad 205, a second conductive layer 212 spaced apart from the first conductive layer 210, and a first conductive layer. It is located between 210 and the second conductive layer 212 and includes a conductive pattern 230 electrically connected to the first conductive layer 210 and the second conductive layer 212.

As described with reference to FIG. 2 , the pad 205 is electrically connected to the data lead line 126 and can transmit an image signal from the data driver integrated circuit 122 to the data line DL.

FIG. 4 is a cross-sectional view taken along line A-A' of FIG. 3.

Referring to Figures 3 and 4, the first conductive layer 210 and the second conductive layer 212 are spaced apart from each other on the substrate 101. The first conductive layer 210 and the second conductive layer 212 may be made of the same material and located on the same layer. In terms of process, the first conductive layer 210 and the second conductive layer 212 may be formed simultaneously on the same layer and made of the same material.

An insulating layer 220 is located on the first conductive layer 210 and the second conductive layer 212. The insulating layer 220 is exposed between the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212, and between the first conductive layer 210 and the second conductive layer 212. Includes an open area (OA). The insulating layer 220 includes a first insulating layer 222 located on the first conductive layer 210 and the second conductive layer 212, and a second insulating layer 224 located on the first insulating layer 222. ) may include. The second insulating layer 224 may be inclined in the opening area OA as shown in FIG. 4, but is not limited thereto.

The conductive pattern 230 is located in the opening area OA and is located on the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212 exposed to the opening area OA. do. Accordingly, the first conductive layer 210 and the second conductive layer 212 are electrically connected through the conductive pattern 230.

This conductive pattern 230 may serve as an inspection pad for inspecting the data line DL, the data integrated circuit 122, and the pixel P. As the conductive pattern 230 is disposed in the opening area OA of the insulating layer 220 as shown in FIGS. 3 and 4, the auto-probe test pin for inspecting the data line DL contacts the data line (DL). DL), the data integrated circuit 122, and the pixel (P) can be inspected for abnormalities.

A metal oxide 240 may be located on the conductive pattern 230 . This metal oxide 240 may be the same material as the pixel electrode constituting the pixel P, as will be described later with reference to FIG. 11, but is not limited thereto. The metal oxide 240 may serve to shield the conductive pattern 230 from the outside.

Figure 5 is a cross-sectional view taken along the indicator line B-B' in Figure 3. FIG. 6 is a cross-sectional view taken along line C-C' of FIG. 3.

Referring to FIG. 5 , the line width W1 of the conductive pattern 230 may be wider than the line widths W2 of the first conductive layer 210 and the second conductive layer 212 . When the metal oxide 240 is located on the conductive pattern 230, the line width of the metal oxide 240 may be substantially the same as the line width W1 of the conductive pattern 230. Accordingly, the line width W1 of the metal oxide 240 may be wider than the line widths W2 of the first conductive layer 210 and the second conductive layer 212.

The line width (W1) of the conductive pattern 230 and the metal oxide 240 is wider than the line width (W2) of the first conductive layer 210, so the conductive pattern 230 and the metal oxide 240 are connected to the first conductive layer 210. It can cover the upper surface (210b) and the side surface (210c) of the end (210a). Likewise, the line width W1 of the conductive pattern 230 and the metal oxide 240 is wider than the line width W2 of the end 212a of the second conductive layer 212, so that the conductive pattern 230 and the metal oxide 240 are The top and side surfaces of the second conductive layer 212 may be covered.

Referring to FIGS. 5 and 6 simultaneously, the conductive pattern 230 is located between the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212. ), the width W4 of the upper surface 230a is the upper surface of the conductive pattern 230 located at the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212 ( It may be wider than the width (W3) of 230b).

When the metal oxide 240 is located on the conductive pattern 230, the width of the top surface of the metal oxide 240 may be substantially the same as the width of the top surface of the conductive pattern 230. Therefore, the width of the upper surface of the metal oxide 240 located on the conductive pattern 230 located between the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212. (W4) is the upper surface of the metal oxide 240 located on the conductive pattern 230 located at the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212. It can be wider than the width (W3).

As a comparative example, the first conductive layer 210 and the second conductive layer 212 are not disposed apart from each other on the substrate 101, but are connected by one conductive layer, and the opening area (OA) of the insulating layer 220 is ) can be placed in the conductive pattern 230. In this case, the width of the upper surface of the conductive pattern 230 is the same as that shown in FIG. 5, and the width of the conductive pattern located at the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212 is the same as that shown in FIG. It is equal to the width W3 of the upper surface 230a of the pattern 230.

In the comparative example, the width W3 of the upper surface of the conductive pattern 230 with which the auto-probe test pin contacts is narrow, so poor contact with the test pin may occur. As described above, as the resolution of the display device increases, Auto-Prove (AP) inspection pins are added for inspection of signal lines, and the pin-to-pin (PIN to PIN) pitch decreases, the upper portion of the conductive pattern 230 The width of the surface (W3) is narrow, which may cause poor contact with the test pin or even make the test itself impossible.

In the embodiment, the width W4 of the upper surface 230b of the conductive pattern 230 with which the auto-probe test pin contacts is wide, thereby preventing poor contact of the test pin.

FIG. 7 is a diagram showing the Z region of FIG. 2 in detail. FIG. 8 is a cross-sectional view taken along the indicator line E-E' of FIG. 7.

Referring to FIGS. 7 and 8 , the log line LOG may be bent and disposed in the non-display area 105 on the substrate 101 . The log line LOG is an insulating layer 320 in which an opening area OA1 different from the conductive layer 310 located on the substrate 101 is disposed, and a conductive pattern 330 located in the other opening area OA1. It includes a pad 305 including. This pad 305 can be called a log line pad.

The log line pad 305 is electrically connected to the log line lead wire 114, as described with reference to FIG. 2, and transmits control signals, clock signals, gate voltage, power supply voltage, ground voltage, etc. to the log line (LOG). It can be transmitted to the gate driver integrated circuit 111 through.

The insulating layer 320 may include a first insulating layer 322 located on the conductive layer 310 and a second insulating layer 324 located on the first insulating layer 322.

The conductive layer 310 may be made of the same material as the first conductive layer 210 and the second conductive layer 212 described with reference to FIGS. 3 to 6 and may be located on the same layer. In terms of process, the conductive layer 310 may be formed simultaneously on the same layer as the first conductive layer 210 and the second conductive layer 212 using the same material. The conductive pattern 330 may be made of the same material as the conductive pattern 230 described with reference to FIGS. 3 to 6 and may be located on the same layer. In terms of process, the conductive pattern 330 may be formed simultaneously on the same layer and using the same material as the conductive pattern 230.

Metal oxide 340 may be located on the conductive pattern 330. This metal oxide 340 may be the same material as the pixel electrode constituting the pixel P, as will be described later with reference to FIG. 11, but is not limited thereto. The metal oxide 340 may serve to shield the conductive pattern 330 from the outside.

In the comparative example, the log line pad may have only the metal oxide 340 disposed on the conductive layer 310 in the opening area OA1 of the insulating layer 320. At this time, the resistance (R) of the conductive layer 310 and the metal oxide 340 may be relatively large. Accordingly, in the comparative example ^, the power consumption (P=I ²

In an embodiment, the log line pad 305 including the conductive pattern 330 between the conductive layer 310 and the metal oxide 340 may reduce overall resistance. Through this, the log line pad 305 can reduce power consumption (P=I ² × R) and heat generation (Heat ∝ I ² × R × t) in proportion to the power consumption.

The structure of the log line pad 305 described above can be equally applied to the pad 205 shown in FIGS. 3 to 6. In addition, the structure of the log line pad 305 described above is equally applicable to any signal line electrically connected to the flexible film 128, for example, the start signal line (SSL) or the pad of various power supply lines not shown. can do.

FIG. 9 is a diagram showing the Y area of FIG. 2 in detail. FIG. 10 is a cross-sectional view taken along the indicator line D-D' of FIG. 9.

Referring to FIG. 9, the log line LOG arranged on the substrate 101 extends from the pad 305 shown in FIG. 7. This log line (LOG) is connected to the connection line (CL). This connection line CL connects the log line LOG to a driving circuit, for example, the gate driving integrated circuit 111 constituting the gate driver shown in FIG. 2.

The connection line (CL) is connected one-to-one with the log line (LOG), and various signals and voltages supplied to the log line (LOG) can be supplied to the gate driver integrated circuit 111. At this time, an anti-static circuit may be disposed at the input terminal of the gate driver integrated circuit 111 where various signals and voltages are input. The anti-static circuit can prevent static electricity from being generated in various signals and voltages supplied from the connection line CL.

Here, the connection line CL may be formed on the same plane as the data line DL. Additionally, the connection line CL may be formed of the same material as the data line DL. Since this connection line (CL) can be formed without additional processes, process cost and time can be reduced.

Referring to FIG. 10, the log line (LOG) is located on the conductive layer 410 connected to the pad 305 shown in FIGS. 7 and 8 and the conductive layer 410. A first insulating layer 422 including a partially exposed first contact hole OA2, and a portion of the first contact hole 0A2 and the connection line CL located on the first insulating layer 422. It includes a second insulating layer 420 including an exposed second contact hole OA3.

The connection pattern 430 is located on the conductive layer 410 and a portion (CLa) of the connection line (CL) in the first contact hole (0A2) and the second contact hole (OA3). A metal oxide 440 may be located on the connection pattern 330, but is not limited thereto. As a result, the connection pattern 430 and the metal oxide 440 may be disposed in the second contact hole OA3, as shown in FIG. 9.

As shown in FIG. 10 , the connection pattern 430 may contact the connection line CL connected to the gate driving integrated circuit 111 and the anti-static circuit (not shown) at the second contact hole OA3.

As described with reference to FIGS. 3 to 6, the first conductive layer 210 and the second conductive layer 212 of the data line DL, and the conductive layer of the pad 305 described with reference to FIGS. 7 and 8 ( 310), the conductive layer 410 of the log line (LOG) described with reference to FIGS. 9 and 10 may be formed of the same material, for example, a single-layer or multi-layer metal or metal alloy, through the same process. For example, the conductive layer 210, the second conductive layer 212, the conductive layer 310, and the conductive layer 410 may be formed simultaneously using the same material as the gate line GL and through the same process.

The conductive pattern 230 of the data line DL as described with reference to FIGS. 3 to 6, the conductive pattern 330 of the pad 305 as described with reference to FIGS. 7 and 8, and the conductive pattern 330 with reference to FIGS. 9 and 10. The connection pattern 430 of the described log line (LOG) may be formed of the same material, for example, a single-layer or multi-layer metal or metal alloy, through the same process. For example, the conductive pattern 230 of the data line DL, the conductive pattern 330 of the pad 305, and the connection pattern 430 of the log line LOG are displayed in the display area as will be described later with reference to FIG. 11. It can be formed at the same time using the same material and through the same process as the touch line that transmits the touch signal to the touch electrode disposed.

The metal oxide 240 of the data line DL as described with reference to FIGS. 3 to 6, the metal oxide 440 of the pad 305 as described with reference to FIGS. 7 and 8, and the metal oxide 440 of the pad 305 with reference to FIGS. 9 and 10. The metal oxide 440 of the described log line (LOG) may be formed from the same material through the same process. For example, the metal oxide 240 of the data line DL as described with reference to FIGS. 3 to 6, the metal oxide 440 of the pad 305 described with reference to FIGS. 7 and 8, and the metal oxide 440 of the pad 305 described with reference to FIGS. 9 and 8. The metal oxide 440 of the log line LOG described with reference to 10 may be formed simultaneously through the same process using the same material as the pixel electrode constituting the pixel P, as will be described later with reference to FIG. 11 .

The first insulating layer 222 and the second insulating layer 224 of the insulating layer 220 of the data line DL described with reference to FIGS. 3 to 6, and the pad 305 described with reference to FIGS. 7 and 8. The first insulating layer 322 and the second insulating layer 324 of the insulating layer 320, and the first insulating layer 422 of the insulating layer 420 of the log line (LOG) described with reference to FIGS. 9 and 10. And the second insulating layer 424 is made of the same material as one of the gate insulating layer, first protective layer, and second protective layer constituting the pixel P, and is made through the same process at the same time, as will be described later with reference to FIG. 11, respectively. can be formed.

Figure 11 is a cross-sectional view of the display device when the display device is a liquid crystal display device integrated with a touch screen panel.

Referring to FIG. 11, in the touch screen panel integrated liquid crystal display device according to one embodiment, for example, a gate line 502 is formed in a first direction on a first substrate 500, and a gate insulating layer (Gate) is formed thereon. Insulator, 504) is formed.

A data line 506 is formed on the gate insulating layer 504 in the second direction, and a first protective layer 508 is formed on it.

A pixel electrode 510 and a touch line 512 of each pixel area may be formed on the first protective layer 508, and a second protective layer 514 may be formed on the first protective layer 508. Here, the touch line 512 is connected to the touch integrated circuit from each of the common electrode and a plurality of electrodes serving as touch electrodes, and in the display driving mode, transmits the common voltage (Vcom) generated from the common voltage supply to the plurality of electrodes. In the touch driving mode, the touch driving signal generated by the touch integrated circuit is transmitted to a plurality of electrodes.

One electrode 516 serving as a common electrode and a touch electrode is formed on the second protective layer 514, and a liquid crystal layer 518 is formed on it. On the liquid crystal layer 518, an upper substrate 520 on which a black matrix (519a), a color filter (519b), etc. are formed is located.

Although the liquid crystal display device is explained in FIG. 11, the present invention is not limited thereto and can be applied to various display devices that can be combined with a touch panel.

Since the above-described display device uses a conductive layer with low resistance to construct the log line, line resistance can be lowered and power consumption and heat generation can be reduced. In particular, since the above-described display device uses a low-resistance touch line as the log line, it can be formed without an additional process in the formation process.

The above-mentioned display device adds an Auto-Prove (AP) inspection pin to inspect the signal line even if the resolution increases, and even if the pin-to-pin (PIN to PIN) pitch decreases, the inspection pin contacts the signal line when inspecting it. Defects can be prevented.

The above-mentioned display device can reduce power consumption and heat generation even if the resolution increases. In particular, since the above-mentioned display device is formed without additional processes during the formation process, manufacturing costs can be reduced and manufacturing time can be shortened.

The above description and attached drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art will be able to combine the components without departing from the essential characteristics of the present invention. , various modifications and transformations such as separation, substitution, and change will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display panel
101: substrate
DL: data line
GL: gate line
LOG: logline
Conductive layer: 210, 212, 310, 410
Insulating layer: 220, 320, 420
Challenge Pattern: 230, 330, 430
Metal oxides: 240, 340, 440

Claims (12)

A substrate including a display area and a non-display area; and
It includes signal lines arranged on the substrate,
The signal line is,
A first conductive layer connected to the first pad,
a second conductive layer spaced apart from the first conductive layer,
A first opening located on the first conductive layer and the second conductive layer, exposing an end of the first conductive layer, an end of the second conductive layer, and between the first conductive layer and the second conductive layer. a first insulating layer including a region;
A first conductive pattern located in the first opening area and located on an end of the first conductive layer exposed to the first opening area and an end of the second conductive layer,
A portion of the upper surface of the first conductive layer and a portion of the upper surface of the second conductive layer are each exposed by the first opening area,
The first conductive pattern includes a portion of the top surface and side surfaces of the first conductive layer exposed by the first opening region, a portion of the side surface of the second conductive layer, and the first conductive pattern exposed by the first opening region. It is disposed along the upper surface of the substrate between the first conductive layer and the second conductive layer,
The first conductive pattern is located between the display area where an image is displayed and a data driver integrated circuit, and is used as a test pad by contacting a test pin. According to paragraph 1,
A display device wherein the line width of the first conductive pattern is wider than the line widths of the first conductive layer and the second conductive layer. According to paragraph 2,
The first conductive pattern is,
The width of the upper surface of the first conductive pattern located between the end of the first conductive layer and the end of the second conductive layer is located between the end of the first conductive layer and the end of the second conductive layer. 1 A display device wider than the width of the upper surface of the conductive pattern. According to paragraph 1,
A display device further comprising a metal oxide located on the first conductive pattern. According to paragraph 1,
The first conductive layer and the second conductive layer are made of the same material and are located on the same layer. According to paragraph 1,
A display device in which the signal line is a data line that supplies an image signal. According to paragraph 1,
The signal line is a log line that supplies a control signal or power voltage to the gate driver. According to paragraph 1,
The first conductive pattern is made of the same material as a touch line that transmits a touch signal to the touch electrode disposed in the display area. According to paragraph 1,
The first pad includes a third conductive layer located on the substrate, a second insulating layer having a second opening region different from the first opening region, and a second conductive pattern located in the second opening region. display device. According to paragraph 1,
log lines arranged on the substrate; and
It includes a connection line connecting the log line to the driving circuit,
The log line is,
A fourth conductive layer connected to the second pad,
A third lower insulating layer located on the fourth conductive layer and including a first contact hole exposing a portion of the fourth conductive layer, and located on the third lower insulating layer and including the first contact hole and the A third insulating layer including a third upper insulating layer including a second contact hole exposing a portion of the connection line,
A display device comprising a connection pattern located in the first contact hole and the second contact hole and on a portion of the fourth conductive layer and the connection line. According to clause 10,
The connection pattern is made of the same material as the touch line that transmits a touch signal to the touch electrode disposed in the display area. According to clause 10,
The second pad includes a fifth conductive layer located on the substrate, a fourth insulating layer having a third opening area, and a third conductive pattern located in the third opening area.

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