KR101712204B1 - Display device and fabricating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device which improves the electrostatic property of a link pad and a method of manufacturing the same. A display device of the present invention includes data lines; Link lines connected to the data lines; And link pads connecting the link lines and the data lines through a first contact hole formed in the link lines and a second contact hole formed in the data lines, And the distance between the end of the link lines and the end of the data lines is in the range of 7.5 to 9.5 mu m.

Description

DISPLAY APPARATUS AND FABRICATION METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device which improves the electrostatic property of a link pad and a method of manufacturing the same.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display controls an electric field applied to liquid crystal cells to modulate light incident from a backlight unit to display an image.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a TFT (Thin Film Transistor) formed for each pixel and switching a data voltage supplied to the pixel electrode, a data driving circuit for supplying a data voltage to the data lines of the liquid crystal display panel A gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the gate lines of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

In a liquid crystal display device, a data drive circuit converts digital video data into a data voltage in a source drive IC and supplies the data voltage to a liquid crystal display panel. The output lines of the source drive IC are connected to the data pads of the liquid crystal display panel, and the data pads are connected to the data lines through the link lines.

1 is a plan view showing a link pad 4 connecting the link lines LL and the data lines DL. Referring to FIG. 1, the link lines LL and the data lines DL are electrically connected through the transparent electrode pattern 1. The link lines LL are formed in a gate metal pattern, and the data lines DL are formed in a source-drain metal pattern. The transparent electrode pattern 1 connects the first contact hole 2 formed on the link lines LL and the second contact hole 3 formed on the data lines DL to form the data lines DL, Thereby electrically connecting the lines DL.

1, the distance d ₁ between the gate metal pattern of the link lines LL and the source-drain metal pattern of the data lines DL is as short as about 4.5 mu m. Therefore, when static electricity flows from the outside, static electricity is generated between the link lines LL and the data lines DL having a small separation distance d ₁ .

FIGS. 2A and 2B are microscope images showing electrostatic failures occurring in the link pad 4 of FIG. 3A to 3C are images obtained by observing the electrostatic failure of FIG. 2 with a focused ion beam (FIB) apparatus. As a result of such electrostatic defects, not only the link pads 4 but also data pads and thin film transistors (TFTs) are damaged.

The present invention provides a display device capable of reducing the electrostatic property of a link pad and a manufacturing method thereof.

In order to achieve the above object, a display device of the present invention includes data lines; Link lines connected to the data lines; And link pads connecting the link lines and the data lines through a first contact hole formed in the link lines and a second contact hole formed in the data lines, And the distance between the end of the link lines and the end of the data lines is in the range of 7.5 to 9.5 mu m.

A manufacturing method of a display device of the present invention includes: data lines; Link lines connected to the data lines; And link pads connecting the link lines and the data lines through a first contact hole formed in the link lines and a second contact hole formed in the data lines, the method comprising: Forming the link lines such that the ends of the lines include concave corrugations; Forming the data lines such that a distance between the ends of the link lines and the end of the data lines is 7.5 占 퐉 to 9.5 占 퐉, the ends of the data lines facing the link lines include concave curved portions, .

In the present invention, the ends of the link lines and the ends of the data lines in the link pad are curved to increase the separation distance between the link lines and the data lines. As a result, the present invention can reduce the electrostatic failure of the link pad, thereby increasing the process yield.

1 is a plan view showing a link pad connecting the link lines and the data lines.
2A and 2B are micrographs showing electrostatic failures occurring in the link pad of FIG.
3A to 3C are images obtained by observing the electrostatic failure of FIG. 2 with FIB equipment.
4 is a block diagram showing a display device according to an embodiment of the present invention.
5 is a plan view showing the detail of part A of FIG.
6 is a cross-sectional view taken along the line I-I 'in Fig.
7 is a plan view showing a link pad according to the first embodiment of the present invention.
8 is a plan view showing a link pad according to a second embodiment of the present invention.
9 is a plan view showing a link pad according to a third embodiment of the present invention.
10 is a flowchart showing a manufacturing method of a display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

4 is a block diagram showing a display device according to an embodiment of the present invention. Referring to FIG. 4, the display device of the present invention includes a display panel 10, a gate driving circuit, a data driving circuit, and a timing controller 50.

The display panel 10 includes a pixel array (PIXEL ARRAY) including data lines and gate lines intersecting with each other and pixels arranged in a matrix form. The display panel 10 may be implemented as a display panel of any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD). Although the display panel 10 of the present invention is exemplified by the liquid crystal display panel as a center, it should be noted that the present invention is not limited to the liquid crystal display panel.

The data driver circuit includes a plurality of source drive ICs 40. [ The source drive ICs 40 receive the digital video data RGB from the timing controller 50. The source driver ICs 40 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 50 to generate a data voltage and synchronize the data voltage with the gate pulse To the data lines of the display panel 10. The source drive ICs 40 may be connected to the data lines of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit includes a level shifter 30 connected between the timing controller 50 and the gate lines of the display panel 10 and a shift register 20. The level shifter 30 is mounted on a PCB (Printed Circuit Board) 60 together with the timing controller 50. The level shifter 30 outputs a transistor-transistor-logic (TTL) logic level voltage of a gate shift clock (GSC) input from the timing controller 50 to a gate high voltage VGH and a gate low voltage VGL, Level shifting. The shift register 20 shifts gate start pulses (GSP) input from the timing controller 50 in response to gate shift clocks GSC input from the level shifter 30, And sequentially outputs pulses.

The timing controller 50 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 50 transmits digital video data (RGB) input from the host computer to the source drive ICs 40.

The timing controller 50 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK from the host computer through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 50 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host computer. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 40 and the polarity of the data voltage.

The gate timing control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP is input to the shift register to control the shift start timing. The gate shift clock is input to the level shifter, level shifted, and then input to the shift register, and is used as a clock signal for shifting the gate start pulse (GSP). The gate output enable signal GOE controls the output timing of the shift register.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 40. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 40 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 50 and the source drive ICs 40 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

5 is a plan view showing the detail of part A of FIG. 6 is a cross-sectional view taken along the line I-I 'in Fig. Part A of FIG. 4 shows the top of the data link portion (DATA LINK) and the pixel array (PIXEL ARRAY).

5 and 6, the data link unit includes data pads 70 and link lines LL connected to the data pads 70. [ The output lines of the source drive ICs 40 are connected to the data pads 70 and each of the link lines LL is connected to the data line DL through the link pad 80. The data voltages output from the source drive ICs 40 are supplied to the data lines DL through the data pads 70, the link lines LL, and the link pads 80. [

The data pads 70 and the link lines LL are formed with the gate metal pattern 102. [ On the other hand, the data lines DL are formed of the source-drain metal pattern 106. [ The source-drain metal pattern 106 of the gate metal pattern 102 and the data lines DL of the link lines LL is electrically connected to the link pad LL 80 via the second transparent electrode pattern 81. [

The data pad 70 includes a gate metal pattern 102 formed on the lower substrate 101, a gate insulating film 103 covering the gate metal pattern 102, a protective film 107 formed on the gate insulating film 103, . The first transparent electrode pattern 71 is connected to the gate metal pattern 102 through the third contact hole 72 passing through the gate insulating film 103 and the protective film 107.

The link pad 80 includes a gate metal pattern 102 of the link line LL, a gate insulating film 103 covering the gate metal pattern 102, and a predetermined distance d ₂₎ is formed to leave on the active layer 104 formed on the gate insulating film 103, the ohmic contact layer 105 and the ohmic contact layer 105 is formed on the active layer 104, a data line ( And a protective film 107 covering the source-drain metal pattern 106 and the source-drain metal pattern 106. The source- The fourth contact hole 82 penetrates the gate insulating film 103 and the protective film 107 and the fifth contact hole 83 penetrates the protective film 107. The second transparent electrode pattern 81 is connected to the gate metal pattern 102 through the fourth contact hole 82 and to the source-drain metal pattern 106 through the fifth contact hole 83. A predetermined distance (d ₂₎ will be described below in conjunction to Fig.

Gate lines GL and data lines DL are formed in a pixel array PIXEL ARRAY and TFTs 90 are formed in a portion where gate lines GL and data lines DL intersect each other. A pixel electrode 91 connected to the TFT 90 is formed in the unit pixel, and an image is displayed by switching of the TFT 90. [

The TFT 90 includes a gate metal pattern 102 branched from the gate line GL, a gate insulating film 103 covering the gate metal pattern 102 and a gate insulating film 103 on the gate metal pattern 102 An active layer 104 formed on the ohmic contact layer 105 and an ohmic contact layer 105 formed on both ends of the active layer 104 and a source-drain metal layer 104 formed on the ohmic contact layer 105, A pattern 106, and a protective film 107 covering the source-drain metal pattern 106. As shown in Fig. The pixel electrode 91 is connected to the source-drain metal pattern 106 through a sixth contact hole 92 penetrating the protective film 107.

The gate metal pattern 102 is made of a metal such as any one of aluminum (Al), AlNd, and copper (Cu) or an alloy thereof. The gate lines GL of the TFTs 90 and the gate lines GL connected to the gate electrodes of the TFTs 90 are formed of the gate metal pattern 102. [ The gate insulating film 103 includes an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The semiconductor pattern includes an active layer 104 and an ohmic contact layer 105. The source-drain metal pattern 106 is formed of a metal such as copper (Cu), aluminum (Al), AlNd, or molybdenum (Mo) or an alloy thereof, and is formed on the semiconductor pattern. The first transparent electrode pattern 71, the second transparent electrode pattern 81 and the pixel electrode 91 are formed of a transparent conductive material such as ITO (indium tin oxide), TO (tin oxide), and IZO (indium zinc oxide) . The third to sixth contact holes 72, 82, 83, and 92 may be formed through an etching process.

7 is a plan view showing a link pad 80 according to the first embodiment of the present invention. 7, the end 84 of the link line LL and the end 85 of the data line DL are connected in parallel to each other to prevent electrostatic discharge between the link line LL and the data line DL. (D ₃ ) of the distance from the center. The minimum distance d ₅ and the maximum distance d ₆ from the fourth contact hole 82 to the end 84 of the link line LL are formed differently so as to be spaced apart from the predetermined distance d ₃ . The point P from the point P of the end 84 of the link line LL is formed to have a maximum distance d ₆ from the fourth contact hole 82. The distance from the R point to the S point of the end 84 of the link line LL is formed to have a minimum distance d ₅ from the fourth contact hole 82. The curve from the point Q to the point R of the end 84 of the link line LL is formed as a gentle curve.

The end 85 of the data line DL is also formed as the end 84 of the link line LL. However, to be spaced a predetermined distance (d _3), the point having the minimum distance (d ₅₎ to the fourth contact hole 82 from the end 84 of the link line (LL) are the data line (DL (D ₆ ) from the end 85 of the second contact hole 83 to the fifth contact hole 83. The points having the maximum distance d ₆ from the end 84 of the link line LL to the fourth contact hole 82 extend from the end 85 of the data line DL to the fifth contact hole 83 (D ₅ ).

A predetermined distance (d ₃₎ may be formed of a 7.5㎛ to 9.5㎛. However, in consideration of the process margin and the electrical characteristics of the link pad 80, it is preferable to be formed to be 8.5 탆. The minimum distance d ₅ from the fourth contact hole 82 to the end of the link line LL is formed to be not less than 3 μm and less than 5 μm and the distance from the fourth contact hole 82 to the end of the link line LL The maximum distance d ₆ may be formed to be not less than 5 탆 and not more than 7 탆. The minimum distance d ₄ from the Q point of the end 84 of the link line LL to the gentle curve pattern of the end 85 of the data line DL may be 8.85 μm or more.

The distance d ₇ from the T point to the U point of the fourth contact hole 82 is 2/3 or less of the length d ₈ of the fourth contact hole 82 for securing the process margin . The fourth contact hole 82 may be formed of two or more contact holes. In this case, the length d ₈ of the fourth contact hole 82 is a distance from the contact hole at one end to the contact hole at the other end it means. The T point of the fourth contact hole 82 is the edge portion of the fourth contact hole 82 having the minimum distance d ₅ from the end 84 of the link line LL to the fourth contact hole 82 . The U point of the fourth contact hole 82 is a point having a maximum distance d ₅ from the end 84 of the link line LL to the fourth contact hole 82, Point corresponding to the point. At the end 84 of the link line LL, both the corner portions P and S are chamfered to prevent the electric field from being biased toward the corner.

8 is a plan view showing a link pad according to a second embodiment of the present invention. Referring to Fig. 8, in the second embodiment of the present invention, the end 84 of the link line LL is formed to have a plurality of concave patterns. In order to avoid static fires, the end 85 of the tip 84 and the data line (DL) of the link line (LL) is to be spaced by a predetermined distance (d _9). The point V which is the center of the concave pattern in the end 84 of the link line LL is a point having a minimum distance d ₁₀ from the fourth contact hole 82 to the end 84 of the link line LL. The W point which is the end of the concave pattern in the end 84 of the link line LL is a point having the maximum distance d ₁₁ from the fourth contact hole 82 to the end 84 of the link line LL.

The end 85 of the data line DL is also formed as the end 84 of the link line LL. However, to be spaced a predetermined distance (d _9), the point having the minimum distance (d ₁₀₎ to the fourth contact hole 82 from the end 84 of the link line (LL) are the data line (DL (D ₁₁ ) from the end 85 of the first contact hole 83 to the fifth contact hole 83. The points having the maximum distance d ₁₁ from the end 84 of the link line LL to the fourth contact hole 82 extend from the end 85 of the data line DL to the fifth contact hole 83 (D ₁₀ ).

The predetermined separation distance d ₉ may be formed to be 7.5 mu m to 9.5 mu m. However, in consideration of the process margin and the electrical characteristics of the link pad 80, it is preferable to be formed to be 8.5 탆. The minimum distance d ₁₀ from the fourth contact hole 82 to the end 84 of the link line LL is formed to be 3 탆 or more and less than 5 탆 and the distance from the fourth contact hole 82 to the link line LL The maximum distance d ₁₁ to the end 84 of the first electrode 12 may be 5 탆 or more and 7 탆 or less. Further, at the end 84 of the link line LL, both corner portions are formed in a chamfered structure to prevent the electric field from being biased toward the corner.

9 is a plan view showing a link pad according to a third embodiment of the present invention. Referring to Fig. 9, in the third embodiment of the present invention, the ends 84 of the link lines LL are formed wider than the concave pattern of Fig. 8 like a wavy pattern. The end 84 of the link line LL and the end 85 of the data line DL should be separated by a predetermined distance d ₁₂ in order to prevent electrostatic discharge. The X point which is the center of the concave pattern in the end 84 of the link line LL is a point having the minimum distance d ₁₃ from the fourth contact hole 82 to the end 84 of the link line LL. The Y point which is the end of the concave pattern in the end 84 of the link line LL is a point having the maximum distance d ₁₄ from the fourth contact hole 82 to the end 84 of the link line LL.

The end 85 of the data line DL is also formed as the end 84 of the link line LL. However, to be spaced a predetermined distance (d _12), the point having the minimum distance (d ₁₃₎ to the fourth contact hole 82 from the end 84 of the link line (LL) are the data line (DL And a maximum distance d ₁₄ from the end 85 of the second contact hole 83 to the fifth contact hole 83. The points having the maximum distance d ₁₄ from the end 84 of the link line LL to the fourth contact hole 82 extend from the end 85 of the data line DL to the fifth contact hole 83 (D ₁₃ ).

The predetermined separation distance d ₁₂ may be formed to be 7.5 탆 to 9.5 탆. However, in consideration of the process margin and the electrical characteristics of the link pad 80, it is preferable to be formed to be 8.5 탆. The minimum distance d ₁₃ from the fourth contact hole 82 to the end 84 of the link line LL is formed to be not less than 3 탆 and less than 5 탆 and from the fourth contact hole 82 to the link line LL, The maximum distance d ₁₄ to the end 84 of the first semiconductor layer ₁₂ may be formed to be not less than 5 탆 and not more than 7 탆. Further, at the end 84 of the link line LL, both corner portions are formed in a chamfered structure to prevent the electric field from being biased toward the corner.

10 is a flowchart showing a manufacturing method of a display device according to an embodiment of the present invention. This will be described with reference to Figs. 7 to 9. Fig.

The manufacturing method of the display device including the link pad 80 according to the embodiment of the present invention first forms the link lines LL so that the ends of the link lines LL include concave curved portions. At this time, the ends 84 of the link lines LL are formed in consideration of the distance from the data lines DL. The link lines LL are located at points where the end 84 of the link lines LL has a minimum distance from the end 84 of the link lines LL to the fourth contact hole 82, And a point having a maximum distance from the end (84) to the fourth contact hole (82). (S1)

The second end of the data lines opposite to the link lines includes a concave curved portion and the distance between the end of the link lines and the end of the data lines is 7.5 占 퐉 to 9.5 占 퐉. . The distance between the end of the link lines and the end of the data lines is preferably 8.5 탆 in consideration of the process margin or the electrical characteristics of the link pad 80. The data lines DL are formed at positions where the ends 85 of the data lines DL have a minimum distance from the end 85 of the data lines DL to the fifth contact holes 83, And a point having a maximum distance from the first contact hole 85 to the fifth contact hole 83. At this time, the points having the minimum distance from the end 84 of the link lines LL to the fourth contact hole 82 have a maximum distance from the end 85 of the data line DL to the fifth contact hole 83 And the points having the maximum distance from the end 84 of the link lines LL to the fourth contact hole 82 extend from the end 85 of the data line DL to the fifth contact hole 83 ) With a minimum distance. The minimum distance may be not less than 3 mu m and less than 5 mu m, and the maximum distance may be not less than 5 mu m and not more than 7 mu m. (S2)

Each of the third to sixth contact holes 72, 82, 83, and 92 may be formed of a plurality of contact holes.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

1: transparent electrode pattern 2: first contact hole
3: second contact hole 4: link pad
10: display panel 20: shift register
30: Level shifter 40: Source drive IC
50: Timing controller 60: PCB
70: Data pad 71: First transparent electrode pattern
72: third contact hole 80: link pad
81: second transparent electrode pattern 82: fourth contact hole
83: fifth contact hole 84: end of the link line
85: end of data line 90: TFT
91: pixel electrode 92: sixth contact hole
101: lower substrate 102: gate metal pattern
103: gate insulating film 104: active layer
105: ohmic contact layer 106: source-drain metal pattern
107: Protective film LL: Link line
DL: Data line GL: Gate line

Claims (18)

Data lines;
Link lines spaced apart from each other by a predetermined distance so as not to overlap with the data lines; And
And a second contact hole formed in the data lines and connecting the data lines to the link lines,
The ends of the link lines include points having a minimum distance from the end of the link lines to the first contact hole and points having a maximum distance from the end of the link lines to the first contact hole,
The ends of the data lines include points having a minimum distance from the end of the data lines to the second contact hole and points having a maximum distance from the end of the data lines to the second contact hole,
The points having the minimum distance of the link lines are opposed to the points having the maximum distance of the data lines,
Wherein points having the maximum distance of the link lines are opposed to points having the minimum distance of the data lines. The method according to claim 1,
And a distance between an end of the link lines and an end of the data lines is 8.5 m. delete The method according to claim 1,
Wherein the minimum distance is not less than 3 占 퐉 and less than 5 占 퐉, and the maximum distance is not less than 5 占 퐉 and not more than 7 占 퐉. The method according to claim 1,
Wherein the link lines are formed in a gate metal pattern, and the data lines are formed in a source-drain metal pattern. The method according to claim 1,
Wherein both edges of the ends of the link lines and both edges of the ends of the data lines are formed by a chamfer structure. Data lines; Link lines spaced apart from each other by a predetermined distance so as not to overlap with the data lines; And link pads connecting the link lines and the data lines through a first contact hole formed in the link lines and a second contact hole formed in the data lines,
Forming the link lines including points having a minimum distance from an end of the link lines to the first contact hole and points having a maximum distance from an end of the link lines to the first contact hole; And
Forming the data lines including points having a maximum distance from an end of the data lines to the second contact hole and a point having a minimum distance from an end of the data lines to the second contact hole ,
The points having the minimum distance from the end of the link lines to the first contact hole are opposed to the points having the maximum distance from the end of the data lines to the second contact hole,
Wherein points having a maximum distance from an end of the link lines to the first contact hole are opposed to points having a minimum distance from an end of the data lines to the second contact hole. 8. The method of claim 7,
Wherein a distance between an end of the link lines and an end of the data lines is 8.5 占 퐉. delete delete delete 8. The method of claim 7,
Wherein the minimum distance is 3 占 퐉 or more and less than 5 占 퐉, and the maximum distance is 5 占 퐉 or more and 7 占 퐉 or less. The method according to claim 1,
Wherein the ends of the link lines and the end of the data lines opposite to the link lines each include at least one curved portion concavely waved. The method according to claim 1,
Wherein a distance between an end of the link lines and an end of the data lines is 7.5 mu m to 9.5 mu m. The method according to claim 1,
The distance between the points having the minimum distance of the link lines and the points having the maximum distance of the opposite data lines,
And a distance between the points having the maximum distance of the link lines and the points having the minimum distance of the data lines facing the same. 8. The method of claim 7,
Wherein the ends of the link lines and the ends of the data lines facing the link lines each include at least one curved portion concavely waved. 8. The method of claim 7,
Wherein a distance between an end of the link lines and an end of the data lines is 7.5 占 퐉 to 9.5 占 퐉. 8. The method of claim 7,
The distance between the points having the minimum distance of the link lines and the points having the maximum distance of the opposite data lines,
And a distance between the points having the maximum distance of the link lines and the points having the minimum distance of the data lines facing the same.

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