KR20120030724A - Display device and method of cutting off static electricity and noise thereof - Google Patents

Abstract

PURPOSE: A display device and a method for blocking static electricity and noise from the display device are provided to block static electricity and low frequency noise which can be inputted to a display panel. CONSTITUTION: A start pulse wire supplies a start pulse to a gate driving circuit. The start pulse starts an operation of the gate driving circuit. An inductor(L) is connected to the start pulse wire. A capacitor(C) is connected between a low potential voltage wire and the inductor. A low potential voltage is supplied to the low potential voltage wire. A start signal input terminal of the gate driving circuit is connected to a node between the inductor and the capacitor.

Description

DISPLAY DEVICE AND METHOD OF CUTTING OFF STATIC ELECTRICITY AND NOISE THEREOF}

The present invention relates to a display device for removing static electricity and low frequency noise introduced into a display panel using a filter composed of a combination of an inductor (L) and a capacitor (C), and a method of blocking the static electricity and noise.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes. The liquid crystal display forms a liquid crystal layer having anisotropic dielectric constants of upper and lower transparent substrates, and adjusts the intensity of an electric field formed in the liquid crystal layer according to video data to change the molecular arrangement of the liquid crystal material to display a desired image.

The driving circuit of the liquid crystal display device includes a data driving circuit for supplying a data voltage of video data to data lines of the display panel, and a gate pulse synchronized with the data voltage to the gate lines (or scan lines) of the display panel. It includes a gate driving circuit for supplying. The gate driving circuit may be directly formed on the lower substrate of the display panel together with the pixel array by a gate in panel (GIP) process. The gate driving circuit includes a shift register formed on the display panel and a level shifter formed on a printed circuit board (hereinafter, referred to as a “PCB”) electrically connected to the display panel. .

As shown in FIGS. 1 and 2, the shift register includes a plurality of clock signals CLK1 to n, a high potential power voltage VDD, a low potential power voltage VSS, and a start pulse VST that are inputted and cascaded. It includes the stages ST1 to STn. The clock signals CLK1 to n are k (k is a natural number of two or more) phase clock signals whose phases are sequentially delayed, and the voltage level is adjusted through a level shifter and input to the shift register. The level shifter adjusts the voltage level of the start pulse VST together with the clock signals CLK1 to n and supplies it to the shift register.

Each of the stages STn-1 to STn outputs a pull-up transistor T1 that outputs the gate high voltage VGH of the i-th clock signal CLKi according to the Q node voltage, and a QB node voltage. A pull-down transistor (T2) for discharging the voltage to the low potential voltage (VSS), and a node control circuit (NCON) for controlling the Q node and the QB node. The node control circuit NCON controls the gate voltage of the pull-up transistor T1 and the pull-down transistor T2 by charging / discharging the Q node and the QB node with the start pulse VST or the output voltage of the previous stage. The node control circuit NCON may turn on the pull-up transistor T1 by charging the Q node with the start pulse VST or the output voltage of the previous stage in response to the i-1 th clock signal CLKi-1. . The node control circuit NCON may charge the QB node in response to the i + 1 th clock signal CLKi + 1 to turn on the pull-down transistor T2.

The start pulse VST is supplied to the first stage ST1 of the shift register through the start pulse wiring as shown in FIG. 3. The start pulse VST is generated once at the beginning of the frame period in every frame period. If static electricity flows into the display panel, internal bursts may occur in the shift register of the gate driving circuit and the thin film layers of the pixel array, which may cause driving failure of the display panel. A large capacitor (C _EMI ) is formed between the start pulse wiring and the VSS wiring to which the low potential power voltage (VSS or GND) is supplied so that static electricity does not flow through the start pulse wiring. The large capacitor C _EMI discharges the static electricity into the low potential power supply voltage source VSS as a dotted line when static electricity flows through the start pulse wiring to block static electricity that may flow into the display panel. Meanwhile, the large capacitor C _EMI may not prevent low frequency noise flowing between the low potential voltage source VSS and the display panel. When low-frequency noise flows between the low potential voltage source VSS and the display panel, the gate line is low due to low-frequency noise while the gate line voltage maintains the gate-low voltage VGL after the gate pulse is output from the shift register formed in the display panel. The voltage VGL fluctuates and reliability is low.

The present invention provides a display device capable of blocking static electricity and low frequency noise that may flow into a display panel, and a method of blocking the static electricity and noise.

A display device according to the present invention includes a start pulse wiring for supplying a start pulse for starting the operation of a gate driving circuit to the gate driving circuit; An inductor connected to the start pulse wiring; And a capacitor connected between the low potential voltage line to which the low potential voltage is supplied, and the inductor. The start signal input terminal of the gate driving circuit is connected to a node between the inductor and the capacitor.

The static electricity and noise blocking method of the display device may include: connecting an inductor and a capacitor connected in series with a start pulse line for supplying a start pulse for starting the operation of a gate driving circuit to the gate driving circuit; And connecting a start signal input terminal of the gate driving circuit to a node between the inductor and the capacitor.

According to an exemplary embodiment of the present invention, an inductor and a capacitor may be connected to a start pulse line to block static electricity and low frequency noise that may flow into the display panel.

1 is a block diagram schematically illustrating a shift register of a gate driving circuit.
2 is a circuit diagram showing a stage circuit configuration of a shift register.
3 is a circuit diagram illustrating a static electricity blocking capacitor connected to a start pulse wire.
4 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a circuit diagram showing a filter connected to the start pulse wiring.
FIG. 6 is a circuit diagram illustrating a low pass filter circuit configuration of the filter illustrated in FIG. 5.
FIG. 7 is a circuit diagram illustrating a configuration of a low pass filter circuit of the filter illustrated in FIG. 5.
8 is a plan view showing in detail the filter shown in FIG.
FIG. 9 is a diagram illustrating a cross-sectional structure of the inductor cut along the line "I-I '" and the line "II-II'" in FIG. 8.
FIG. 10 is a view showing a cross-sectional structure of the inductor cut along the line "III-III '" in FIG. 8.
11 is a cross-sectional view illustrating a TFT structure of a pixel array and a shift register formed in a display panel.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The display device of the present invention includes any display device which sequentially supplies scan pulses to the scan lines and writes video data to the pixels by line sequential scanning. For example, the display device of the present invention may be implemented by any one of a liquid crystal display (LCD) and an organic light emitting diode (OLED) display. The liquid crystal display may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, or a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. The liquid crystal mode applicable to the present invention is a vertical electric field driving method such as twisted nematic (TN) mode and a vertical alignment (VA) mode, or a horizontal electric field driving such as IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) mode. The method may be applied, and all other liquid crystal modes currently known may be applied.

Referring to FIG. 4, the display device of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

The display panel 10 includes data lines and gate lines (or scan lines) that cross each other and pixels arranged in a matrix form. The display panel 10 may be implemented as any one of a liquid crystal display (LCD) and an organic light emitting diode display (OLED).

The data driver circuit includes a plurality of source drive ICs 12. The source drive ICs 12 receive digital video data RGB from the timing controller 11. The source drive ICs 12 convert the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronize the data voltage with a scan pulse. The data lines of the display panel 10 may be supplied to each other. The source drive ICs may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit (or scan driving circuit) includes a level shifter 15 and a shift register 13 connected between the timing controller 11 and the scan lines of the display panel 10. Each of the level shifters 15 uses the gate shift clock signals input from the timing controller 11 and the TTL logic level voltages of the start pulses VST and the gate high voltage VGH and the gate low voltage. Level shifted to (VGL) to output clock signals CLK1 to n. Each of the level shifters 15 may down-modulate the gate high voltage VGH at the falling edge of the gate shift clocks in response to an FLK signal (not shown) input from the timing controller 11.

Each of the shift registers 13 includes a circuit configuration as shown in FIGS. 1 and 2 to shift the gate start pulse VST to match the clock signals CLK1 to n. When the output nodes of the shift registers 13 are connected to both gate lines, one of them can operate in the forward shift mode and the other can operate in the reverse shift mode.

The gate driving circuit may be directly formed on the lower substrate of the display panel 10 by a gate in panel (GIP) process. In the GIP process, the level shifter 15 may be mounted on the PCB 14, and the shift register 13 may be formed on the lower substrate of the display panel 10. As shown in FIG. 4, the gate driving circuit may be formed on both sides of the display panel 10 or on only one side thereof.

The timing controller 11 is mounted on the PCB 14. The timing controller 11 receives digital video data (RGB) from an external host system through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 11 transmits digital video data RGB input from the host computer to the source drive ICs 12.

The timing controller 11 performs timing of a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from the host system through an LVDS or TMDS interface receiving circuit. Receive a signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse (VST), gate shift clock signals, a gate output enable signal (Gate Output Enable, GOE), and the like. The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), a source output enable signal (Source Output Enable, SOE), and the like. It includes. The source start pulse SSP controls the shift start timing of the source drive ICs 12. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

On the substrate of the display panel 10, a start pulse wiring to which the start pulse VST is supplied, and a filter 20 are formed. The start pulse wiring is connected between the level shifter 15 and the first stage ST1 of the shift register 13 to supply the start pulse VST to the start signal input terminal of the first stage ST1. The start pulse wiring is supplied with the start pulse VST generated once at the beginning of the frame period every frame period and maintains the low potential power supply voltage VSS for the remaining period. The filter 20 includes an inductor L and a capacitor C connected between the start pulse wiring and the VSS wiring to which the low potential power voltage VSS is supplied, as shown in FIG. 5. The start pulse VST is applied to the start signal input terminal of the first stage ST1 in the shift register 13 through a wire connected to the node between the inductor L and the capacitor C. The filter 20 in which the inductor L and the capacitor C are combined is a low pass filter (LPF) that removes high frequency noise when viewed from the start pulse wiring toward the display panel 10 as shown in FIG. 6. 7 is a high pass filter (HPF) that removes low frequency noise when viewed from the low potential voltage source VSS toward the display panel 10. Static electricity flowing from the PCB 14 toward the display panel 10 is removed through the low pass filter LPF, and low frequency noise flowing into the VSS wiring is removed through the high pass filter HPF. The inductor L may be implemented as a spiral inductor implemented on a plane as shown in FIGS. 8 and 9.

8 is a plan view showing in detail the filter shown in FIG. FIG. 9 is a cross-sectional view illustrating a cross-sectional structure of the inductor cut along the line "I-I '" and the line "II-II'" in FIG. 8. FIG. 10 is a cross-sectional view illustrating a cross-sectional structure of the inductor taken along the line "III-III '" in FIG. 8. FIG. 11 is a cross-sectional view illustrating a TFT structure of a pixel array and a shift register 13 formed in the display panel 10.

8 to 11, the display panel 10 includes gate metal patterns, a gate insulating layer GI covering the gate metal patterns, a semiconductor pattern formed on the gate insulating layer, and source-drain metal patterns. Gate metal patterns are formed by depositing a metal, such as one of aluminum (Al), AlNd, copper (Cu), or an alloy thereof, on a lower substrate of the display panel 10 and patterning the metal by a photolithography process. . The gate metal patterns include the gate electrode TGM of the TFT, the gate line connected to the gate electrode TGM of the TFT, the start pulse wiring VSTL, the lower electrode CGM of the capacitor C, and the lower electrode of the capacitor C LC connection pattern CE extending from CGM toward inductor L, and the like.

The gate insulating layer GI is formed by depositing an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) on a substrate to cover the gate metal patterns. The semiconductor pattern is made of a semiconductor material such as amorphous silicon or polysilicon, and is formed on the gate insulating film GI. The semiconductor pattern includes an active layer ACT and an ohmic contact layer OHM. The source-drain metal pattern is made of metal such as copper (Cu), aluminum (Al), AlNd, molybdenum (Mo), or an alloy thereof, and is formed on the ohmic contact layer (OHM). In the inductor L and the capacitor C of the filter 20, a semiconductor pattern, which is omitted in the drawing, may be formed under the source drain metal pattern. The source-drain metal pattern includes a data line connected to any one of the source and drain electrodes TSD of the TFT, the source and drain electrodes TSD of the TFT, the spiral pattern ISDM of the inductor L, and the upper portion of the capacitor C. Electrodes (CSDM) and the like. The spiral pattern ISDM of the inductor L is patterned in a spiral shape on a plane. The LC connection pattern CE of the capacitor C overlaps one end of the spiral pattern ISDM positioned at the center of the spiral pattern ISDM across the spiral pattern ISDM of the inductor L. One end of the spiral pattern ISDM of the inductor L overlaps a portion of the LC connection pattern CE with the gate insulating film GI therebetween, and the other end thereof starts pulses with the gate insulating film GI therebetween. It overlaps with one side of the wiring VSTL.

The display panel 10 includes a passivation layer PASSI and transparent electrode patterns. The passivation layer (PASSI) includes an inorganic insulating material such as a gate insulating film (GI), an organic insulating material such as an acryl-based organic compound having a low dielectric constant, a benzo cyclobutene (BCB), or a perfluorocyclobutane (PFCB), and a TFT filter. The inductor L and the capacitor C of 20 are covered. A plurality of contact holes are formed in the passivation layer PASSI by patterning the passivation layer material by a photolithography process. The contact holes include first to third contact holes. The first contact hole penetrates through one end of the passivation layer PASSI and the spiral pattern ISDM to expose the side surface of the spiral pattern ISDM and expose the upper surface of the LC connection pattern CE of the capacitor C. The second contact hole penetrates through the other end of the passivation layer PASSI and the spiral pattern ISDM to expose the side surface of the spiral pattern ISDM and expose the top surface of the start pulse wiring VSTL. The third contact hole penetrates through the passivation layer PASSI in the pixel array and the TFT of the shift register to expose any one of the source and drain electrodes of the TFT.

The transparent electrode patterns are transparent such as indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). A conductive material is formed on the passivation layer (PASSI) by depositing a conductive material on the passivation layer (PASSI) and patterning it by a photolithography process. The transparent electrode patterns include first to third transparent electrode patterns. The first transparent electrode pattern contacts the one end side of the spiral pattern ISDM and the top surface of the LC connection pattern CE through the first contact hole to electrically connect the lower electrode CGM of the inductor L and the capacitor C. Connect with The first transparent electrode pattern penetrates the other end of the passivation layer (PASSI) and the spiral pattern (ISDM) through the second contact hole and contacts the side of the other end of the spiral pattern (ISDM) and the top surface of the start pulse wiring (VSTL). (L) and start pulse wiring (VSTL) are electrically connected. The third transparent electrode pattern is connected to any one of the source and drain electrodes of the TFT to serve as a pixel electrode.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

13: level shifter 15: shift register
20 filter L: inductor
C: Capacitor VSTL: Start Pulse Wiring

Claims (5)

A display device comprising a gate driving circuit formed directly on a substrate of a display panel together with a pixel array.
A start pulse wiring for supplying a start pulse for starting the operation of the gate driving circuit to the gate driving circuit;
An inductor connected to the start pulse wiring; And
A low potential voltage wiring supplied with a low potential voltage, and a capacitor connected between the inductor,
And a start signal input terminal of the gate driving circuit is connected to a node between the inductor and the capacitor. The method of claim 1,
The start pulse wiring is formed on the substrate with a first gate metal pattern,
The capacitor,
A lower electrode formed of a second gate metal pattern formed on the substrate, an upper electrode formed of a first source-drain metal pattern overlapping the lower electrode with a gate insulating layer interposed therebetween, and a third electrode extending from the lower electrode toward the inductor And an LC connection pattern formed of a gate metal pattern. The method of claim 2,
The inductor is,
And a spiral pattern formed of a second source-drain metal pattern overlapping one side of the start pulse line with the gate insulating layer interposed therebetween and overlapping one end of the LC connection pattern of the capacitor. . The method of claim 3, wherein
A passivation layer covering the inductor and the capacitor;
A first transparent electrode pattern electrically connecting the side surface of one end of the spiral pattern to the lower electrode of the storage capacitor through a first contact hole penetrating through the passivation layer and one end of the spiral pattern; And
And a second transparent electrode pattern electrically connecting the other end side of the spiral pattern and one side of the start pulse wire through a second contact hole penetrating through the passivation layer and the other end of the spiral pattern. Display. In the electrostatic and noise blocking method of the display device including a gate driving circuit formed directly on the substrate of the display panel with a pixel array,
Connecting an inductor and a capacitor in series with a start pulse wiring for supplying a start pulse for starting the operation of the gate driving circuit to the gate driving circuit; And
Connecting the start signal input terminal of the gate driving circuit to a node between the inductor and the capacitor.

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