CN104749844A - Electrostatic protection circuit, array substrate, display panel and display device - Google Patents
Electrostatic protection circuit, array substrate, display panel and display device Download PDFInfo
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- CN104749844A CN104749844A CN201510180921.5A CN201510180921A CN104749844A CN 104749844 A CN104749844 A CN 104749844A CN 201510180921 A CN201510180921 A CN 201510180921A CN 104749844 A CN104749844 A CN 104749844A
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- 239000000758 substrate Substances 0.000 title abstract description 7
- 238000009413 insulation Methods 0.000 claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 1
- 239000010408 film Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract 8
- 230000005611 electricity Effects 0.000 abstract 5
- 230000003068 static effect Effects 0.000 abstract 5
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides an electrostatic protection circuit, an array substrate, a display panel and a display device. The electrostatic protection circuit comprises a first capacitor and a second capacitor which are connected in series; the first capacitor comprises a first electrode layer, a second electrode layer and a first insulation layer which is located between the first electrode layer and the second electrode layer; the second capacitor comprises a third electrode layer, a fourth electrode layer and a second insulation layer which is located between the third electrode layer and the fourth electrode layer; the second electrode layer is electrically connected with the third electrode layer; the fourth electrode layer and the first electrode layer are mutually insulated. Accordingly, the static electricity can be stored in the first capacitor or the second capacitor so as to avoid the damage caused by the static electricity and the second capacitor can still be used for storing the static electricity when the breakdown short-circuit of the first capacitor is caused by the too large static electricity and accordingly the problem that the display performance of the array substrate, the display panel and the display device is affected by the static electricity is solved.
Description
Technical field
The present invention relates to display technique field, more particularly, relate to a kind of electrostatic discharge protection circuit, array base palte, display panel and display device.
Background technology
Existing display panel, comprise viewing area and the non-display area being positioned at this viewing area surrounding, wherein, the pixel cell that viewing area comprises many gate lines, a plurality of data lines and surrounded by gate line and data line, non-display area comprises the gate driver circuit and data circuit etc. that are electrically connected with gate line.
But, because non-display area comprises a large amount of electronic devices and components and conductive lead wire etc., therefore, in the process of display panel work, inevitably can produce electrostatic, these electrostatic can make the electronic devices and components in display panel damage because of short circuit, affect the display effect of display panel.
Summary of the invention
In view of this, the invention provides a kind of electrostatic discharge protection circuit, array base palte, display panel and display device, to solve the problem affecting display panel display effect in prior art due to electrostatic damage electronic devices and components.
For achieving the above object, the invention provides following technical scheme:
A kind of electrostatic discharge protection circuit, described electrostatic discharge protection circuit comprises the first electric capacity and second electric capacity of series connection, described first electric capacity comprises the first electrode layer, the second electrode lay and the first insulation course between described first electrode layer and the second electrode lay, described second electric capacity comprises the 3rd electrode layer, the 4th electrode layer and the second insulation course between described 3rd electrode layer and the 4th electrode layer, described the second electrode lay is electrically connected with described 3rd electrode layer, described 4th electrode layer and described first electrode layer mutually insulated.
A kind of array base palte, described array base palte comprises viewing area and is positioned at the non-display area of described viewing area surrounding, described non-display area comprises multiple shift register and provides the drive wire of drive singal to described shift register and provide the reference voltage line of reference voltage to described shift register, described array base palte also comprises the electrostatic discharge protection circuit being positioned at described non-display area, described electrostatic discharge protection circuit is electrostatic discharge protection circuit as above, first electrode layer of described electrostatic discharge protection circuit is electrically connected with described drive wire, 4th electrode layer of described electrostatic discharge protection circuit is electrically connected with described reference voltage line.
A kind of display panel, comprises the array base palte described in above-mentioned any one.
A kind of display device, comprises display panel as above.
Compared with prior art, technical scheme provided by the present invention has the following advantages:
Electrostatic discharge protection circuit provided by the present invention, array base palte, display panel and display device, electrostatic discharge protection circuit comprises the first electric capacity and second electric capacity of series connection, first electric capacity comprises the first electrode layer, the second electrode lay and the first insulation course between the first electrode layer and the second electrode lay, second electric capacity comprises the 3rd electrode layer, the 4th electrode layer and the second insulation course between the 3rd electrode layer and the 4th electrode layer, the second electrode lay is electrically connected with the 3rd electrode layer, the 4th electrode layer and the first electrode layer mutually insulated.It can thus be appreciated that, first electric capacity and the second electric capacity all can store electrostatic, avoid the damage that electrostatic causes, and, when electrostatic is excessive cause the first electric capacity puncture short time, second electric capacity still can play the effect storing electrostatic, thus avoids the problem affecting array base palte, display panel and display device display performance due to electrostatic.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The circuit diagram of the electrostatic discharge protection circuit that Fig. 1 provides for one embodiment of the present of invention;
The tangent plane structural representation of a kind of electrostatic discharge protection circuit that Fig. 2 provides for one embodiment of the present of invention;
The structure vertical view of a kind of electrostatic discharge protection circuit that Fig. 3 provides for one embodiment of the present of invention;
The tangent plane structural representation of the another kind of electrostatic discharge protection circuit that Fig. 4 provides for one embodiment of the present of invention;
The tangent plane structural representation of another electrostatic discharge protection circuit that Fig. 5 provides for one embodiment of the present of invention;
The structural representation of the array base palte that Fig. 6 provides for an alternative embodiment of the invention;
A kind of tangent plane structural representation of electrostatic discharge protection circuit in the array base palte that Fig. 7 provides for an alternative embodiment of the invention;
The tangent plane structural representation of another kind of electrostatic discharge protection circuit in the array base palte that Fig. 8 provides for an alternative embodiment of the invention;
The tangent plane structural representation of another electrostatic discharge protection circuit in the array base palte that Fig. 9 provides for an alternative embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
An embodiment provides a kind of electrostatic discharge protection circuit, as shown in Figure 1, this electrostatic discharge protection circuit comprises the first electric capacity C1 and the second electric capacity C2 of series connection.
The tangent plane structural drawing of a kind of electrostatic discharge protection circuit that the present embodiment provides as shown in Figure 2, described first electric capacity C1 comprises the first electrode layer 30, the second electrode lay 31 and the first insulation course 32 between described first electrode layer 30 and the second electrode lay 31, described second electric capacity C2 comprises the 3rd electrode layer 33, 4th electrode layer 34 and the second insulation course 35 between described 3rd electrode layer 33 and the 4th electrode layer 34, wherein, described 4th electrode layer 34 and the first electrode layer 30 mutually insulated, described the second electrode lay 31 and the 3rd electrode layer 33 are electrically connected, mutually connect to make described first electric capacity C1 and the second electric capacity C2.
In the present embodiment, as shown in Figure 2, first electrode layer 30 and the 4th electrode layer 34 are positioned at same layer, and the first electrode layer 30 and the spaced setting of the 4th electrode layer 34, the second electrode lay 31 and the 3rd electrode layer 33 are positioned at same layer, and the second electrode lay 31 and the 3rd electrode layer 33 are continuous print integrative-structure.Because the second electrode lay 31 and the 3rd electrode layer 33 are the same layer metal level adopting same technique to prepare, therefore, the second electrode lay 31 and the 3rd electrode layer 33 are electrically connected.
The plan structure figure of a kind of electrostatic discharge protection circuit that the present embodiment provides as shown in Figure 3, the second electrode lay 31 and the 3rd electrode layer 33 are the suspended metal layer of same layer, and the current potential being meant to this metal level of described suspended metal layer is in floating (floating) state.And, first electrode layer 30 has the contact conductor 301 extended to first direction, the second electrode lay 34 has the contact conductor 341 extended to second direction, described first direction is contrary with second direction, certainly, the present invention is not limited to this, and described first direction and second direction can be same direction, also can be orthogonal direction.
Present embodiments provide another kind of electrostatic discharge protection circuit, as shown in Figure 4, first electrode layer 30 of the first electric capacity C1 and the 3rd electrode layer 33 of the second electric capacity C2 are positioned at same layer, and the first electrode layer 30 and the spaced setting of the 3rd electrode layer 33; The second electrode lay 31 of the first electric capacity C1 and the 4th electrode layer 34 of the second electric capacity C2 are positioned at same layer, and the second electrode lay 31 and the spaced setting of the 4th electrode layer 34.Based on this, the second electrode lay 31 and the 3rd electrode layer 33 are electrically connected by least one via hole 36, and described via hole 36 runs through described first insulation course 32 and/or the second insulation course 35, to realize the series connection of the first electric capacity C1 and the second electric capacity C2.
The present embodiment additionally provides a kind of electrostatic discharge protection circuit, as shown in Figure 5, the second electrode lay and the 3rd electrode layer are continuous print unified electrode structure layer 33/31, described electrode structure layer 33/31 comprises relative first surface 310 and second surface 311, first insulation course 32 is arranged at first surface 310, and the first electrode layer 30 is arranged at the surface of the first insulation course 32 away from electrode structure layer; Described second insulation course 35 is arranged at second surface 311, and the 4th electrode layer 34 is arranged at the surface of the second insulation course 35 away from electrode structure layer.That is, the first insulation course 32 and the first electrode layer 30 that are positioned at first surface 310 form the first electric capacity C1 with described electrode structure layer 33/31, and the second insulation course 35 and the 4th electrode layer 34 that are positioned at second surface 311 form the second electric capacity C2 with described electrode structure layer 33/31.Because the second electrode lay and the 3rd electrode layer are integrated electrode structure layer 33/31, therefore, between the first electric capacity C1 and the second electric capacity C2 be series connection mutually.
The electrostatic discharge protection circuit that the present embodiment provides, first electric capacity of mutual series connection and the second electric capacity all can be used for first storing electrostatic slow releasing electrostatic again, avoid the damage that electrostatic causes, and, when electrostatic is excessive cause one of them electric capacity as the first electric capacity puncture short time, another electric capacity such as the second electric capacity still can play the effect storing electrostatic, thus can avoid the problem of electrostatic influence array base palte, display panel and display device display performance.
An alternative embodiment of the invention provides a kind of array base palte, as shown in Figure 6, this array base palte comprises viewing area 70 and is positioned at the non-display area 71 of described viewing area 70 surrounding, described non-display area 71 comprises multiple shift register 710, there is provided the drive wire IN of drive singal to described shift register 710 and the reference voltage line VGL of reference voltage is provided to described shift register 710, in the present embodiment, described array base palte also comprises the electrostatic discharge protection circuit 711 being positioned at described non-display area 71, the electrostatic discharge protection circuit that described electrostatic discharge protection circuit 711 provides for above-described embodiment, namely described electrostatic discharge protection circuit 711 comprises the first electric capacity and second electric capacity of series connection mutually, first electrode layer 30 of described electrostatic discharge protection circuit 711 is electrically connected with described drive wire IN, 4th electrode layer 34 of described electrostatic discharge protection circuit 711 is electrically connected with described reference voltage line VGL, namely drive wire IN is electrically connected with the contact conductor 301 of the first electrode layer 30, reference voltage line VGL is electrically connected with the contact conductor 341 of the 4th electrode layer 34.Wherein, in the array base palte that provides of the present embodiment, the number of electrostatic discharge protection circuit 711 is not limit.
Array base palte in the present embodiment also comprises multiple pixel cell 712, the sectional drawing of array base palte as shown in Figure 7, described pixel cell 712 comprises thin film transistor (TFT) 713, described thin film transistor (TFT) 713 comprises grid 7130, be positioned at described grid 7130 away from gate insulator 7131, the silicon island layer 7132 on substrate 7 surface and be positioned at described silicon island layer 7132 away from the source electrode 7133 on substrate 7 surface and drain electrode 7134, and described first insulation course 32 and/or the second insulation course 35 are positioned at same layer with described silicon island layer 7132 and/or passivation layer 714.
As shown in Figure 7, described first electrode layer 30 and the 4th electrode layer 34 is spaced is arranged at same layer, and described first electrode layer 30 and described 4th electrode layer 34 are arranged at same layer with described grid 7130 is spaced; Described the second electrode lay 31 and the 3rd electrode layer 33 are positioned at same layer, described the second electrode lay 31 and the 3rd electrode layer 33 are continuous print integrative-structure, and described the second electrode lay 31 and the 3rd electrode layer 33 and described source electrode 7133 and drain and 7134 be spacedly arranged at same layer; Described first insulation course 32 and the second insulation course 35 are arranged at same layer with described silicon island layer 7132.
As shown in Figure 8, described first electrode layer 30 and the 3rd electrode layer 33 are positioned at same layer, and described first electrode layer 30 and the 3rd electrode layer 33 are arranged at same layer with described grid 7130 is spaced; Described the second electrode lay 31 is positioned at same layer with described 4th electrode layer 34, and described the second electrode lay 31 and described 4th electrode layer 34 and described source electrode 7133 and drain and 7134 be spacedly arranged at same layer, and the second electrode lay 31 is electrically connected by least one via hole 36 with the 3rd electrode layer 33, described via hole 36 runs through described first insulation course 32 or the second insulation course 35; Described first insulation course 32 and the second insulation course 35 and described silicon island layer 7132 are arranged at same layer.
As shown in Figure 9, described the second electrode lay 31 and the 3rd electrode layer 33 are continuous print unified electrode structure layer, and described electrode structure layer and described source electrode 7133 and drain and 7134 be spacedly arranged at same layer, described electrode structure layer comprises relative first surface 310 and second surface 311, described first insulation course 32 is arranged at described first surface 310, and described first insulation course 32 is arranged at same layer with described silicon island layer 7132 is spaced, described first electrode layer 30 is arranged at the surface of described first insulation course 32 away from described electrode structure layer, and described first electrode layer 30 is arranged at same layer with described grid 7130 is spaced, described second insulation course 35 is arranged at described second surface 311, and described second insulation course 35 is arranged at same layer with described passivation layer 714, described 4th electrode layer 34 is arranged at the surface of described second insulation course 35 away from described electrode structure layer, and described 4th electrode layer 34 is arranged at same layer with described pixel electrode layer 715 is spaced.
The array base palte that the present embodiment provides, first electric capacity of mutual series connection and the second electric capacity all can be used for first storing electrostatic slow releasing electrostatic again, avoid the damage that electrostatic causes, and, when electrostatic is excessive cause one of them electric capacity as the first electric capacity puncture short time, another electric capacity such as the second electric capacity still can play the effect storing electrostatic, thus can avoid the problem of electrostatic influence array base palte, display panel and display device display performance.
Another embodiment of the present invention provides a kind of display panel, and this display panel comprises array base palte that above-described embodiment provides and the counter substrate that array base palte is oppositely arranged and the liquid crystal layer be arranged between described array base palte and counter substrate or organic luminous layer etc.
Of the present invention other embodiment still provides a kind of display device, comprise the display panel that above-described embodiment provides, the chip providing drive singal for display panel.When the display panel of display device is display panels, display device also can comprise for display panel provides the backlight etc. of light source.
The display panel that the present embodiment provides and display device, first electric capacity of mutual series connection and the second electric capacity all can be used for first storing electrostatic slow releasing electrostatic again, avoid the damage that electrostatic causes, and, when electrostatic is excessive cause one of them electric capacity as the first electric capacity puncture short time, another electric capacity such as the second electric capacity still can play the effect storing electrostatic, thus can avoid the problem of electrostatic influence display panel and display device display performance.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (13)
1. an electrostatic discharge protection circuit, it is characterized in that, described electrostatic discharge protection circuit comprises the first electric capacity and second electric capacity of series connection, described first electric capacity comprises the first electrode layer, the second electrode lay and the first insulation course between described first electrode layer and the second electrode lay, described second electric capacity comprises the 3rd electrode layer, the 4th electrode layer and the second insulation course between described 3rd electrode layer and the 4th electrode layer, described the second electrode lay is electrically connected with described 3rd electrode layer, described 4th electrode layer and described first electrode layer mutually insulated.
2. circuit according to claim 1, is characterized in that, described first insulation course and described second insulation course are positioned at same layer, and are continuous print integrative-structure.
3. circuit according to claim 2, is characterized in that, described first electrode layer and described 4th electrode layer are positioned at same layer, and interval is arranged; Described the second electrode lay and described 3rd electrode layer are positioned at same layer, and are continuous print integrative-structure.
4. circuit according to claim 2, is characterized in that, described first electrode layer and described 3rd electrode layer are positioned at same layer, and interval is arranged; Described the second electrode lay and described 4th electrode layer are positioned at same layer, and interval is arranged.
5. circuit according to claim 4, is characterized in that, described the second electrode lay and described 3rd electrode layer are electrically connected by least one via hole, and described via hole runs through described first insulation course or the second insulation course.
6. circuit according to claim 1, is characterized in that, described the second electrode lay and the 3rd electrode layer are continuous print unified electrode structure layer; Described electrode structure layer comprises relative first surface and second surface, and described first insulation course is arranged at described first surface, and described first electrode layer is arranged at the surface of described first insulation course away from described electrode structure layer; Described second insulation course is arranged at described second surface, and described 4th electrode layer is arranged at the surface of described second insulation course away from described electrode structure layer.
7. an array base palte, described array base palte comprises viewing area and is positioned at the non-display area of described viewing area surrounding, described non-display area comprises multiple shift register, there is provided the drive wire of drive singal to described shift register and the reference voltage line of reference voltage is provided to described shift register, it is characterized in that, described array base palte also comprises the electrostatic discharge protection circuit being positioned at described non-display area, described electrostatic discharge protection circuit is electrostatic discharge protection circuit according to claim 1, first electrode layer of described electrostatic discharge protection circuit is electrically connected with described drive wire, 4th electrode layer of described electrostatic discharge protection circuit is electrically connected with described reference voltage line.
8. array base palte according to claim 7, described array base palte also comprises multiple pixel cell, described pixel cell comprises thin film transistor (TFT), described thin film transistor (TFT) comprises grid, is positioned at the silicon island layer of described gate surface and is positioned at source electrode and the drain electrode on layer surface, described silicon island, it is characterized in that, described first insulation course and the second insulation course and described silicon island layer are positioned at same layer.
9. array base palte according to claim 8, is characterized in that, described first electrode layer and the 4th electrode layer and described grid is spaced is arranged at same layer; Described the second electrode lay and the 3rd electrode layer and described source electrode and drain electrode are arranged at same layer, and described the second electrode lay and described 3rd electrode layer are continuous print integrative-structure.
10. array base palte according to claim 8, is characterized in that, described first electrode layer and the 3rd electrode layer and described grid is spaced is arranged at same layer; Described the second electrode lay and described 4th electrode layer and described source electrode and drain and be spacedly arranged at same layer; Described the second electrode lay and described 3rd electrode layer are electrically connected by least one via hole, and described via hole runs through described first insulation course or the second insulation course.
11. array base paltes according to claim 7, described array base palte also comprises multiple pixel cell, described pixel cell comprises thin film transistor (TFT), be positioned at passivation layer and the pixel electrode layer of described film crystal tube-surface, described thin film transistor (TFT) comprises grid, be positioned at the silicon island layer of described gate surface and be positioned at source electrode and the drain electrode on layer surface, described silicon island, it is characterized in that, described the second electrode lay and the 3rd electrode layer are continuous print unified electrode structure layer, and described electrode structure layer and described source electrode and drain and be spacedly arranged at same layer, described electrode structure layer comprises relative first surface and second surface, described first insulation course is arranged at described first surface, and described first insulation course and described silicon island layer is spaced is arranged at same layer, described first electrode layer is arranged at the surface of described first insulation course away from described electrode structure layer, and described first electrode layer and described grid is spaced is arranged at same layer, described second insulation course is arranged at described second surface, and described second insulation course and described passivation layer are arranged at same layer, described 4th electrode layer is arranged at the surface of described second insulation course away from described electrode structure layer, and described 4th electrode layer and described pixel electrode layer is spaced is arranged at same layer.
12. 1 kinds of display panels, is characterized in that, comprise the array base palte described in any one of claim 7-11.
13. 1 kinds of display device, is characterized in that, comprise display panel according to claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510180921.5A CN104749844A (en) | 2015-04-16 | 2015-04-16 | Electrostatic protection circuit, array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510180921.5A CN104749844A (en) | 2015-04-16 | 2015-04-16 | Electrostatic protection circuit, array substrate, display panel and display device |
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| CN104749844A true CN104749844A (en) | 2015-07-01 |
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| CN201510180921.5A Pending CN104749844A (en) | 2015-04-16 | 2015-04-16 | Electrostatic protection circuit, array substrate, display panel and display device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024781A (en) * | 2016-07-22 | 2016-10-12 | 京东方科技集团股份有限公司 | Electrostatic discharge device and manufacturing method thereof, array substrate, display panel and device |
| CN107219699A (en) * | 2017-06-22 | 2017-09-29 | 武汉华星光电技术有限公司 | A kind of array base palte |
| CN107505747A (en) * | 2017-07-25 | 2017-12-22 | 武汉华星光电技术有限公司 | A kind of preparation method of array base palte, display panel and substrate |
| CN107949199A (en) * | 2017-12-19 | 2018-04-20 | 惠科股份有限公司 | Display device and its display panel |
| WO2019056513A1 (en) * | 2017-09-21 | 2019-03-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and display apparatus |
| WO2020062537A1 (en) * | 2018-09-29 | 2020-04-02 | 武汉华星光电技术有限公司 | Array substrate and display device |
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Application publication date: 20150701 |