CN104460155A - Display panel, display panel manufacturing method and display - Google Patents
Display panel, display panel manufacturing method and display Download PDFInfo
- Publication number
- CN104460155A CN104460155A CN201410785265.7A CN201410785265A CN104460155A CN 104460155 A CN104460155 A CN 104460155A CN 201410785265 A CN201410785265 A CN 201410785265A CN 104460155 A CN104460155 A CN 104460155A
- Authority
- CN
- China
- Prior art keywords
- display panel
- mark
- active region
- film transistor
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133374—Constructional arrangements; Manufacturing methods for displaying permanent signs or marks
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a display panel. The display panel comprises an active region with pixels and a peripheral circuit region without pixels. A plurality of parallel data lines at intervals are arranged in the active region; fan-out leads used for connection with a driver chip are arranged in the peripheral circuit region; the active region is provided with first identifications, and the first identifications are formed at intervals on a plurality of ITO (indium tin oxide) layers of a thin film transistor array substrate by etching and used for distinguishing the data lines connected with the fan-out leads. By the first identifications arranged on the at least one ITO layer of the thin film transistor array substrate of the display panel, directly etching number identifications on metal grids in the prior art is replaced, quantity of the metal grids with etched number identifications is greatly decreased, each single metal data line on the display panel can be wider, and accordingly possibility of breakage of the metal data lines is reduced while ratio of rejects due to vertical lines generated on products is decreased. The invention further provides a display.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of display panel, the manufacture method of display panel and display.
Background technology
Display panels is made up of a colored optical filtering substrates with chromatic filter layer, thin film transistor (TFT) (TFT) array base palte and the liquid crystal layer be arranged between this two substrates.
Current display panels is mainly development trend with frivolous large-size screen monitors, this just requires to have high density, small size, freely fitted a new generation encapsulation technology can meet above demand, based on this, COF (Chip on Film, namely brilliant film is covered) encapsulation technology arises at the historic moment, and this Technology application flexible circuit board is made packaged chip carrier and is engaged with flexible base plate circuit by chip, is the crystal grain mantle structure packing technique be fixed on by driving chip in flexible circuit board.
As shown in Figure 1, display panels can be divided into active region (active area) 10 and perimeter circuit district (peripheral circuit area) 11.Multiple pixel is configured with to form pel array (sign) in active region 10, the pixel electrode that each pixel includes a thin film transistor (TFT) and is connected with this thin film transistor (TFT), and each pixel is surrounded by two adjacent sweep traces 12 and two adjacent data lines 13,11, perimeter circuit district is designed with fan-out (fan out) and goes between 110, and the region that fan-out lead-in wire 110 is concentrated is fanout area 110S.Usually, these sweep traces 12 and data line 13 can extend to perimeter circuit district 11 by active region 10, and to be held with driving chip (driver IC) 1 i.e. COF by fan-out lead-in wire 110 and be electrically connected.
In order to reduce costs, usually the COF module 1S quantity of product data line side is reduced to 1.Meanwhile, as Fig. 2, on 110S place, fanout area, the even metal grid 12a that is connected with sweep trace 12, etch Digital ID 2 in active region 10, in order to distinguish each data line 13 numbering, realize fan-out lead-in wire 110 and be connected with accurate aligning of data line 13.
But when COF module 1S join domain is narrower, the width of the data line 13 in Digital ID 2 region is too small, is easy to cause data line metal 13 to rupture, and forms vertical light line, causes the fraction defective of product to increase.
Summary of the invention
In view of the deficiency that prior art exists, the invention provides a kind ofly reduce data line metal fracture probability, reduce the display panel of product fraction defective, the manufacture method of display panel and display.
In order to realize above-mentioned object, present invention employs following technical scheme:
A kind of display panel, comprises the active region with pixel and the perimeter circuit district without pixel, and described active region is provided with many parallel and spaced data lines; Described perimeter circuit district is provided with the fan-out lead-in wire for connecting driving chip, described active region is provided with the first mark, described first identifies spaced etch in multiple ITO layer of thin-film transistor array base-plate, for distinguishing the described data line connecting described fan-out lead-in wire.
Wherein, the quantity of described driving chip is 1.
Wherein, every two described first mark between at least between be separated with one without mark ITO layer.
Wherein, described active region is also provided with the second mark near described perimeter circuit district, and described second mark is arranged at least one grid of thin-film transistor array base-plate.
Wherein, described second be designated multiple, each described first mark with described second mark between at least between be separated with one without mark ITO layer.
Wherein, the quantity of described first mark is greater than described second mark, and is arranged at intervals with at least one first mark between every two described second marks.
Wherein, 4 first marks are arranged at intervals with between every two described second marks.
Meanwhile, present invention also offers a kind of manufacture method of above-mentioned display panel, wherein, before the described fan-out lead-in wire of connection with described data line, the first mark described in spaced etch in multiple ITO layer of thin-film transistor array base-plate.
Wherein, at least one grid of thin-film transistor array base-plate etches described second mark.
In addition, present invention also offers a kind of display, comprise COF module and above-mentioned display panel.
The present invention by being provided with the first mark at least one ITO layer of the thin-film transistor array base-plate of display panel, thus instead of prior art and directly on metal gates, etch Digital ID, the metal gates quantity etching Digital ID is greatly reduced, single metal data line on display panel can design wider, reduce data line metal fracture probability, reduce the fraction defective that product produces vertical light line simultaneously.
Accompanying drawing explanation
Fig. 1 is the display device structure schematic diagram of prior art.
Fig. 2 is the display panel identified areas structural representation of prior art.
Fig. 3 is the display device structure schematic diagram of the embodiment of the present invention.
Fig. 4 is the thin-film transistor array base-plate partial sectional view of the embodiment of the present invention.
Fig. 5 is the display panel identified areas structural representation of the embodiment of the present invention.
Fig. 6 is the manufacture method schematic diagram of the display panel of the embodiment of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is described in more detail.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 3, the display panel 100 of the embodiment of the present invention comprises active region 10 and perimeter circuit district 11, has pixel cell in active region 10, and is provided with many parallel and spaced data lines 213; Perimeter circuit district 11 does not have pixel cell, and is provided with the fan-out lead-in wire 110 for connecting driving chip 1.Composition graphs 4, wherein, tft array substrate (not shown) comprise stack gradually glass substrate 212S, grid 212a, dielectric layers 212d, source/drain 212c between transparent conductive film (i.e. ITO) layer 212b and dielectric layers 212d.The active region 10 of the display panel 100 of the present embodiment is provided with the first mark 300 near perimeter circuit district 11, composition graphs 5, particularly, multiple first mark 300 is etched on multiple ITO layer 212b of tft array substrate in compartment of terrain respectively, for numbering to facilitate differentiation to data line 213, be conducive to accurately connecting fan-out lead-in wire 110, the drive singal of outside be passed to each pixel cell in display panel 100.
The COF module 1S that display comprises display panel 100 and is attached thereto, wherein, in order to cost-saving, the present embodiment only has a COF module 1S, this COF module 1S comprises driving chip 1 and lead-out terminal (figure does not mark), and COF module 1S is connected on fan-out lead-in wire 110 by lead-out terminal.It is fan-shaped that fan-out lead-in wire 110 arrangement forms fanout area 110S, fanout area 110S, can effectively shorten length of arrangement wire and save wiring space.
Wherein, first mark 300 be specifically provided with multiple, every two first mark 300 between at least between be separated with one without mark ITO layer 212b.The active region 10 of display panel 100 is provided with the second mark 200, second mark 200 and is specifically etched at least one grid 212a of TFT row substrate near perimeter circuit district 11.Meanwhile, the second mark 200 also be multiple, between each first mark 300 and the second mark 200 at least between be separated with one without the ITO layer 212b identified.The quantity of the first mark 300 is greater than the second mark 200, and is arranged at intervals with at least one first mark 300 between every two second marks 200.By such setting, fan-out lead-in wire 110 can accurately be electrically connected with the source/drain 212c on display panel 10, is namely electrically connected with data line 213, communicated data signal.Because the first mark 300 and first to identify between 300, second identifies and 200 and second to identify between 200, first identify 300 and second and identify 200 equal intervals with or without the ITO layer 212b identified, decrease the quantity of mark display panel 100 etching formation, while simplifying manufacturing process, compared to existing technology, data line 213 can do wider.
In the present embodiment, for reducing the quantity of the second mark 200 to greatest extent, increase the width of data line 213, the data line 213 of preferred dual numbers numbering identifies, in the mark of every 10 data lines 213, only comprise one second mark 200, all the other 4 marks are the first mark 300, are namely arranged at intervals with 4 first marks 300 between every two second marks 200.Be understandable that, between each mark, the quantity of the data line 213 at interval also can freely be arranged, and such as, also can identify once every 2 or 3 data lines 213.
As shown in Figure 6, present invention also offers a kind of manufacture method of above-mentioned display panel, wherein, in step S02: before connecting fan-out lead-in wire 110 and data line 213, also comprise step S01: spaced etch first identifies 300 in multiple ITO layer of thin-film transistor array base-plate, at least one grid of thin-film transistor array base-plate etches the second mark 200.Further, the second mark 200 is multiple and interval setting.
The present invention has the first mark by spaced etch in multiple ITO layer of the thin-film transistor array base-plate at display panel, thus instead of prior art and directly on metal gates, etch Digital ID, the metal gates quantity etching Digital ID is greatly reduced, single metal data line on display panel can design wider, reduce data line metal fracture probability, reduce the fraction defective that product produces vertical light line simultaneously.
The above is only the embodiment of the application; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection domain of the application.
Claims (10)
1. a display panel, it is characterized in that, comprise the active region (10) with pixel and the perimeter circuit district (11) without pixel, described active region (10) are provided with many parallel and spaced data lines (213); Described perimeter circuit district (11) is provided with fan-out lead-in wire (110) for connecting driving chip (1), described active region (10) is provided with the first mark (300) near described perimeter circuit district (11), described first identifies (300) spaced etch in multiple ITO layer of thin-film transistor array base-plate, for distinguishing the described data line (213) connecting described fan-out lead-in wire (110).
2. display panel according to claim 1, is characterized in that, the quantity of described driving chip (1) is 1.
3. display panel according to claim 1 and 2, is characterized in that, every two described first mark (300) between at least between be separated with one without mark ITO layer.
4. display panel according to claim 3, it is characterized in that, described active region (10) is also provided with the second mark (200) near described perimeter circuit district (11), and described second mark (200) is arranged at least one grid of thin-film transistor array base-plate.
5. display panel according to claim 4, it is characterized in that, described second mark (200) for multiple, each described first mark (300) and described second mark (200) between at least between be separated with one without identify ITO layer.
6. display panel according to claim 5, it is characterized in that, the quantity of described first mark (300) is greater than described second mark (200), and is arranged at intervals with at least one first mark (300) between every two described second marks (200).
7. display panel according to claim 6, is characterized in that, is arranged at intervals with 4 first marks (300) between every two described second marks (200).
8. one kind as arbitrary in claim 1 ~ 7 as described in the manufacture method of display panel, it is characterized in that, front at connection described fan-out lead-in wire (110) and described data line (213), the first mark (300) described in spaced etch in multiple ITO layer of thin-film transistor array base-plate.
9. the manufacture method of display panel according to claim 8, is characterized in that, at least one grid of thin-film transistor array base-plate etches described second mark (200).
10. a display, is characterized in that, comprises COF module (1S) and the arbitrary described display panel of claim 1 ~ 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410785265.7A CN104460155B (en) | 2014-12-16 | 2014-12-16 | A kind of display panel, the manufacture method of display panel and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410785265.7A CN104460155B (en) | 2014-12-16 | 2014-12-16 | A kind of display panel, the manufacture method of display panel and display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104460155A true CN104460155A (en) | 2015-03-25 |
| CN104460155B CN104460155B (en) | 2017-08-11 |
Family
ID=52906447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410785265.7A Active CN104460155B (en) | 2014-12-16 | 2014-12-16 | A kind of display panel, the manufacture method of display panel and display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104460155B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
| CN107145016A (en) * | 2017-07-13 | 2017-09-08 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, liquid crystal panel and display device and array base palte |
| CN107843992A (en) * | 2017-10-26 | 2018-03-27 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel |
| CN108594548A (en) * | 2018-04-19 | 2018-09-28 | 深圳市华星光电技术有限公司 | Liquid crystal display panel fanout area and liquid crystal display panel |
| CN108957885A (en) * | 2018-07-20 | 2018-12-07 | 深圳市华星光电技术有限公司 | Array substrate |
| CN109581770A (en) * | 2018-12-15 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | A kind of method for numbering serial of data line |
| CN111128965A (en) * | 2019-12-16 | 2020-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| US10861881B2 (en) | 2018-07-20 | 2020-12-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253751C (en) * | 2002-07-04 | 2006-04-26 | Nec液晶技术株式会社 | LCD device with address mark connected with wiring |
| CN100576023C (en) * | 2008-06-02 | 2009-12-30 | 友达光电股份有限公司 | Circuit and use its display panels |
| CN101441376B (en) * | 2008-11-24 | 2010-06-09 | 友达光电股份有限公司 | Active element array substrate and liquid crystal display panel |
| CN102867823B (en) * | 2012-09-27 | 2015-05-27 | 合肥京东方光电科技有限公司 | Array substrate and manufacturing method and display device thereof |
| CN202975550U (en) * | 2012-12-26 | 2013-06-05 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and display device |
| CN103926716B (en) * | 2013-12-24 | 2018-01-09 | 上海天马微电子有限公司 | Substrate and signal line marking method thereof |
| CN103823313A (en) * | 2014-02-28 | 2014-05-28 | 友达光电(厦门)有限公司 | Liquid crystal display panel and manufacturing method thereof |
-
2014
- 2014-12-16 CN CN201410785265.7A patent/CN104460155B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
| CN107145016A (en) * | 2017-07-13 | 2017-09-08 | 深圳市华星光电技术有限公司 | The preparation method of array base palte, liquid crystal panel and display device and array base palte |
| CN107843992A (en) * | 2017-10-26 | 2018-03-27 | 武汉华星光电半导体显示技术有限公司 | A kind of display panel |
| CN108594548A (en) * | 2018-04-19 | 2018-09-28 | 深圳市华星光电技术有限公司 | Liquid crystal display panel fanout area and liquid crystal display panel |
| CN108594548B (en) * | 2018-04-19 | 2020-11-24 | 深圳市华星光电技术有限公司 | Liquid crystal panel fan-out area and liquid crystal panel |
| CN108957885A (en) * | 2018-07-20 | 2018-12-07 | 深圳市华星光电技术有限公司 | Array substrate |
| US10861881B2 (en) | 2018-07-20 | 2020-12-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Array substrate |
| CN109581770A (en) * | 2018-12-15 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | A kind of method for numbering serial of data line |
| CN111128965A (en) * | 2019-12-16 | 2020-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111128965B (en) * | 2019-12-16 | 2022-05-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104460155B (en) | 2017-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104460155A (en) | Display panel, display panel manufacturing method and display | |
| CN101110443B (en) | Display substrate, method of manufacturing and display device comprising the substrate | |
| CN109449140B (en) | Display panel and mother board | |
| CN102566167B (en) | Array substrate | |
| KR101398094B1 (en) | Liquid crystal display and array substrate | |
| CN105182646B (en) | Array substrate, display device | |
| CN111367125B (en) | Array substrate and display panel | |
| US8154674B2 (en) | Liquid crystal display, array substrate and mother glass thereof | |
| CN101833200B (en) | Horizontal electric field type liquid crystal display device and manufacturing method thereof | |
| CN103217845B (en) | Lower substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal displayer | |
| CN104375347B (en) | Array base palte, patch, display panel and the method for repairing array base palte | |
| CN102998865B (en) | Array substrate, as well as manufacture method and display device thereof | |
| US9360724B2 (en) | Array substrate and display device | |
| CN108803177A (en) | Array substrate, display panel and its detection method | |
| CN104698710A (en) | Array substrate and liquid crystal display device | |
| CN106647054B (en) | Liquid crystal display panel and liquid crystal display | |
| CN103279217A (en) | Built-in touch screen and display device | |
| CN104656327B (en) | A kind of array base palte and liquid crystal display panel | |
| CN107505789B (en) | Array substrate and display panel | |
| CN104965368A (en) | Liquid crystal panel and display device | |
| CN107123384B (en) | Test method of display substrate and substrate applied to display equipment | |
| CN104749844A (en) | Electrostatic protection circuit, array substrate, display panel and display device | |
| CN103296021A (en) | TFT array substrate | |
| US9792867B2 (en) | Display apparatus | |
| CN105093729A (en) | Array substrate, manufacturing method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |