CN109449140B - Display panel and mother board - Google Patents
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- CN109449140B CN109449140B CN201811291804.6A CN201811291804A CN109449140B CN 109449140 B CN109449140 B CN 109449140B CN 201811291804 A CN201811291804 A CN 201811291804A CN 109449140 B CN109449140 B CN 109449140B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses a display panel and a mother board, wherein the display panel mother board comprises a plurality of display panels which are arranged in an array mode, a display area and a non-display area on the periphery of the display area are defined on the surface of each display panel, the non-display area is provided with a plurality of conductive gaskets and a plurality of short circuit connecting wires, and at least the non-display area of the display panel which is not the first row is provided with an electrostatic short circuit ring; one end of each short circuit connecting wire in each display panel in the same column is respectively connected to the conductive gaskets, and the other end of each short circuit connecting wire is electrically connected with the electrostatic short circuit ring of the adjacent display panel in the next row. Through the mode, the static electricity generated to the display panel by the display panel mother board in the testing or cutting process can be eliminated, and the static protection effect of the panel is improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel and a motherboard.
Background
The existing display panel is formed by cutting a display panel mother board, cutting lines are arranged on the display panel mother board, the cutting lines divide the display panel mother board into a plurality of display panel units, and after the display panel mother board is cut according to the cutting lines, one display panel unit corresponds to one display panel.
In the process of manufacturing the display panel, in order to avoid the generation of a voltage difference between signals and the generation of a large amount of static electricity in the process of cutting, testing and the like of a mother board, the influence of the static electricity is generally eliminated by adopting a mode of connecting all signal wires in an equipotential manner. However, in order to realize the narrow frame design, various conductive pads are already arranged in the lower frame binding region of the display panel, and it is impossible to place an electrostatic short circuit ring (ESD short circuit ring), especially for the display panel arranged on the motherboard at a non-zero interval, if there is no electrostatic short circuit ring, the motherboard is very easy to generate a large amount of static electricity during the testing, cutting and other processes, which causes electrostatic damage to the display region of the display panel, further causes abnormal display, and affects the productivity and production quality of the product.
Disclosure of Invention
The application provides a display panel and display device, can solve among the prior art problem effect that can't place the static short circuit ring when display panel zero interval arranges.
In order to solve the technical problem, the application adopts a technical scheme that: the display panel mother board comprises a plurality of display panels arranged in an array mode, wherein a display area and a non-display area on the periphery of the display area are defined on the surface of each display panel, the non-display area is provided with a plurality of conductive gaskets and a plurality of short circuit connecting wires, and at least the non-display area of the display panel in a non-first row is provided with an electrostatic short circuit ring; one end of the short circuit connecting lines in the display panel in the at least non-first row in the same column is respectively connected to the conductive pads, and the other end of the short circuit connecting lines is electrically connected with the electrostatic short circuit rings of the adjacent display panel in the next row.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a display panel, wherein the display panel is defined with a display area and a non-display area at the periphery of the display area, and the non-display area is provided with a plurality of conductive gaskets, a plurality of short circuit connecting wires and an electrostatic short circuit ring; one end of each short circuit connecting wire is connected to the conductive gaskets, and the other end of each short circuit connecting wire extends to the edge of the display panel and is used for being electrically connected with another display panel in a display panel mother board in the manufacturing process.
In order to solve the above technical problem, the present application adopts another technical solution: providing a display panel, wherein the display panel is defined with a display area and a non-display area at the periphery of the display area, and the non-display area is provided with an electrostatic short circuit loop line and a short circuit connecting line; and one end of the short circuit connecting wire is connected to the electrostatic short circuit loop wire, and the other end of the short circuit connecting wire extends to the edge of the display substrate and is used for electrically connecting another display substrate connected to a mother substrate board in the manufacturing process.
The beneficial effect of this application is: the utility model provides a display panel and mother board, through set up the static short circuit ring in being connected to the adjacent display panel in next row with a plurality of electrically conductive pads of non-leading display panel in the mother board through the short circuit connecting wire, can make the equipotential of all signals in the display panel connect, eliminate the display panel mother board in the static that test or cutting in-process produced display panel, promote the static protection effect of panel.
Drawings
FIG. 1 is a schematic structural diagram of a first embodiment of a mother board of a display panel according to the present application;
FIG. 2 is a schematic cross-sectional view of one embodiment of region B-B' of FIG. 1 of the present application;
FIG. 3 is a schematic structural diagram of a second embodiment of a mother board of a display panel according to the present application;
FIG. 4 is a schematic structural diagram of a display panel mother board according to a third embodiment of the present application;
FIG. 5 is a schematic structural diagram of a display panel mother board according to a fourth embodiment of the present application;
FIG. 6 is a schematic structural diagram of a fifth embodiment of a mother board of a display panel according to the present application;
FIG. 7 is a schematic structural diagram of a display panel mother board according to a sixth embodiment of the present application;
FIG. 8 is a schematic structural diagram of a display panel according to a first embodiment of the present application;
fig. 9 is a schematic structural diagram of a second embodiment of the display panel of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a mother board of a display panel according to the present application. As shown in fig. 1, the display panel motherboard 100 provided in the present application includes a plurality of display panels 110 arranged in an array, and optionally, a distance between adjacent display panels 110 in the present embodiment is zero, that is, the display panels on the display panel motherboard 100 in the present application are arranged in a zero-distance manner.
A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. The arrangement of the display panels in the display panel motherboard 100 in this embodiment is specifically described by taking 1 times 2 (i.e. the number of the display panels 110 in the row direction is 1, and the number of the display panels 110 in the column direction is 2) as an example. As shown in fig. 1, the non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, and at least the non-display area 112 of the display panel 110 not in the first row is provided with an electrostatic short-circuit ring 113.
The conductive pads 1121 may be testing conductive pads, chip on Film conductive pads, i.e., COF pads (chip on Film), etc., and are not limited herein, wherein a plurality of signal leads (not shown) are disposed in the display region of each of the display panels 110, and the signal leads are electrically connected to the conductive pads 1121 through fan-out traces B disposed in the non-display region 112.
One end of each of the short-circuit connection lines 1122 in each of the display panels 100 in the same column is connected to the conductive pads 1121, and the other end is electrically connected to the electrostatic short-circuit ring 113 of the adjacent display panel 110 in the next row. Specifically, referring to fig. 1, in the present embodiment, the electrostatic short ring 113 is not disposed in the display panel 110 in the first row on the display panel motherboard 100, and the electrostatic short ring 113 is disposed in the non-display region 112 of the display panel 110 in the adjacent row. Of course, in other embodiments, the electrostatic short ring 113 may be disposed on the display panel 110 in the first row, which is not limited herein.
Specifically, the non-display area 112 of each display panel 110 includes at least a first non-display area 115 disposed adjacent to the display panel 110 in the previous row. It is understood that, in the same column of the display panel mother board 100, the adjacent place of two adjacent display panels 110 may be regarded as the lower frame of the display panel 110 in the upper row and the upper frame of the display panel 110 in the lower row being adjacent, that is, the first non-display area 115 is located at the upper frame of the display panel 110, and the electrostatic short ring 113 may be disposed in the first non-display area 115.
With further reference to FIG. 2, FIG. 2 is a schematic cross-sectional view of an embodiment of region B-B' of FIG. 1. Each display panel 110 includes an encapsulation layer 116 covering the display region 111 and the non-display region 112, and the electrostatic short ring 113 is disposed between the encapsulation layer 116 covering the first non-display region 115 defined in the non-display region 112 and the substrate base plate 101 of the display panel. Optionally, the package of each display panel 110 in this embodiment is Frit package, that is, the upper and lower substrates are bonded by Frit to form a package layer, which blocks external water and oxygen to protect the light emitting devices in the display panel. The encapsulation layer 116 may be made of a conventionally used glass frit, such as at least one of Al2O3, SnO, TeO2, MgO, CaO, ZnO, TiO2, WO3, Bi2O3, Fe2O3, and CuO, which is not limited herein. It is understood that in other embodiments of the present application, each display panel 110 may be encapsulated by other encapsulation methods, such as a film encapsulation, a UV glue encapsulation, and the like, which are not limited herein.
Alternatively, as shown in fig. 2, the electrostatic short ring 113 is disposed between the encapsulation layer 116 covering the first non-display region 115 and the substrate 101 of the display panel. In order to prevent the arrangement of the electrostatic short-circuit ring 113 from affecting the encapsulation of the panel by the encapsulation layer 116, in the embodiment, the thickness of the electrostatic short-circuit ring 113 is set to be very thin, which may be one tenth, one thirtieth, one fiftieth, etc. of the thickness of the encapsulation layer 116, and is not limited in detail here, and the encapsulation layer is not illustrated in fig. 1.
It is understood that the electrostatic shorting ring 113 may be a ring of electrostatic discharge shielding wires, and the material thereof may be Polysilicon (PSI). Of course, in other embodiments, the material of the electrostatic segment loop 113 degree may also be metal, and is not limited specifically herein. The impedance may be set to 50K Ω to 300K Ω, and specifically may be 50K Ω, 175K Ω, 300K Ω, and the like, which is not limited herein.
It can be understood that a large amount of static electricity is easily generated during the cutting of the display panel mother board 100 or the subsequent testing of the display panel 110 after the display panel 110 is manufactured, and the static electricity is easily introduced into the metal traces in the non-display area 112 of the display panel 110 and the display area 111 to cause electrostatic damage to the device, thereby causing display malfunction and affecting the production efficiency of the display panel. Therefore, in the same column, the plurality of conductive pads in the first row of display panels are connected to the adjacent display panels in the next row through the short circuit connecting lines and are arranged in the first non-display area to form the electrostatic short circuit ring 113, and the impedance of the electrostatic short circuit ring 113 is set in the range of 50-300K omega, so that the static electricity generated in the processes of testing, cutting and the like of the display panel mother board 100 can be well eliminated, the damage of the static electricity to the display panels is prevented, and the static protection effect of the panels is improved.
In the above embodiment, the plurality of conductive pads in the first row of display panels in the same column are connected to the electrostatic short-circuit ring disposed in the first non-display area in the adjacent display panel in the next row through the short-circuit connection line, so that all signals in the display panels are connected in an equipotential manner, static electricity generated by the display panel mother board to the first row of display panels in the testing or cutting process is eliminated, and the electrostatic protection effect of the panel is improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a second embodiment of a display panel mother board according to the present application, and as shown in fig. 3, the present embodiment is a further extension of the first embodiment of the display panel mother board, and is substantially the same as the first embodiment, except that in the present embodiment, electrostatic short rings disposed in non-display regions of adjacent display panels in a same row are connected in series, and the electrostatic short rings after being connected in series are electrically connected to a plurality of conductive pads through a plurality of short-circuit lines of a previous row of display panels, which is specifically described as follows:
referring to fig. 3, the display panel mother board 100 provided in the present embodiment includes a plurality of display panels 110 arranged in an array, and a distance between adjacent display panels 110 is zero.
A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. The arrangement of the display panels in the display panel motherboard 100 of the present embodiment is specifically described by taking 2 times 2 (i.e. the number of the display panels 110 in the row direction is 2, and the number of the display panels 110 in the column direction is 2) as an example. As shown in fig. 3, the non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, and at least the non-display area 112 of the display panel 110 not in the first row is provided with an electrostatic short-circuit ring 113.
In the display panel mother board 100 provided in this embodiment, the first non-display regions 115 defined on the upper border of the display panel 110 in the first row are not provided with the electrostatic short-circuit rings 113, the first non-display regions 115 defined on the upper border of the display panel 110 in the second row are provided with the electrostatic short-circuit rings 113, and each of the electrostatic short-circuit rings 113 in the second row are connected in series, and the serially connected electrostatic short-circuit rings 113 are electrically connected to the plurality of conductive pads 1121 through the plurality of short-circuit wires 1122 of the display panel 110 in the previous row. Optionally, the material selected and the specific position of the electrostatic short-circuit ring 113 and the selection of the impedance of the electrostatic short-circuit ring 113 in this embodiment are the same as those in the first embodiment, refer to the detailed description in the first embodiment, and are not repeated herein.
It can be understood that, in the embodiment, the electrostatic short-circuit rings disposed in the first non-display area 115 defined by the upper frame of the same row of display panels are connected in series, and are connected to the plurality of conductive pads 1121 of the previous row of display panels 110 through the short-circuit connection lines 1122 disposed in the previous row of display panels 110, so that all signals in all display panels in the first row are connected in an equipotential manner, static electricity generated by the display panel mother board to the display panel in the first row in the testing or cutting process is eliminated, and the electrostatic protection effect of the panel is improved.
In addition, the electrostatic short ring 113 may also be designed as shown in fig. 4, that is, the electrostatic short ring 113 is configured to include a plurality of electrostatic short traces 1131 arranged at intervals. Specifically, referring to fig. 4, the technical solution shown in this embodiment is similar to the second embodiment of the display panel mother board, and the same parts are not described again, where:
the display panel mother board 100 includes a plurality of display panels 110 arranged in an array, and a distance between adjacent display panels 110 is zero. A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. The non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, the first non-display area 115 defined by the upper frame of the second row of display panels 110 is provided with an electrostatic short-circuit ring 113, the electrostatic short-circuit ring 113 includes a plurality of electrostatic short-circuit traces 1131 arranged at intervals, each of the electrostatic short-circuit traces 1131 is connected to the plurality of conductive pads 1121 through the plurality of short-circuit connection lines 1122 in the first row of display panels 110, so that equipotential connection of all signals in the display panels 110 in the first row is achieved, static electricity generated by the display panels in the first row of display panels in the testing or cutting process is eliminated, and the electrostatic protection effect of the display panels is improved.
In the above embodiment, the plurality of conductive pads in the first row of display panels in the same column are respectively connected to the plurality of electrostatic short-circuit wires arranged in the first non-display area in the adjacent display panel in the next row through the short-circuit connecting lines, so that all signals in the display panel are connected in an equipotential manner, static electricity generated by the display panel mother board to the first row of display panels in the testing or cutting process is eliminated, and the electrostatic protection effect of the panel is improved.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of a mother board of a display panel according to the present application, which is a further extension of the third embodiment of the mother board of the display panel, and a difference is that equipotential traces connected to a display area are disposed on a surface of the display panel in each row, where the electrostatic short ring and the equipotential traces are connected as follows:
as shown in fig. 5, the display panel mother board 100 provided by the present application includes a plurality of display panels 110 arranged in an array, and a distance between adjacent display panels 110 is zero. A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. The arrangement of the display panels in the display panel motherboard 100 in this embodiment is specifically described by taking 2 times 2 as an example. As shown in fig. 5, the non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, and at least the non-display area 112 of the display panel 110 not in the first row is provided with an electrostatic short-circuit ring 113. One end of each of the short-circuit connection lines 1122 in each of the display panels 100 in the same column is connected to the conductive pads 1121, and the other end is electrically connected to the electrostatic short-circuit ring 113 of the adjacent display panel 110 in the next row.
It can be understood that details regarding the position arrangement relationship between the electrostatic short-circuit ring and the conductive pad in this embodiment are described in the first to third embodiments, and are not described herein again.
Referring to fig. 5, in the present embodiment, an equipotential trace 1111 is disposed on the surface of each display panel 110 and connected to the display region 111, and the electrostatic short ring 113 is electrically connected to the equipotential trace 1111. To specifically explain the implementation principle of the present embodiment with reference to fig. 5, no electrostatic short ring 113 is disposed in the first non-display area 115 defined by the bezel of the display panel 110 in the first row of the display panel motherboard 100 in fig. 5, an electrostatic short ring 113 is disposed in the first non-display area 115 defined by the bezel of all the display panels 110 in the second row, the electrostatic short ring 113 of the display panel 110 in the second row is connected to the plurality of conductive pads 1121 through the short connection line 1122 in the display panel 110 in the first row, and the electrostatic short ring 113 of each display panel 110 in the second row is electrically connected to the equipotential trace 1111.
Optionally, the number of the equipotential traces 1111 connected to each display panel 110 may be set to be multiple, the number of the electrostatic short ring 113 of each display panel may be one, and the electrostatic short ring 113 connects all the equipotential traces, so that all the display panels 110 in the same column may be equipotentially connected, static electricity generated during testing or cutting of the mother board of the display panel may be eliminated, and the electrostatic protection effect of the display panel may be improved.
Optionally, if the electric potentials of the equipotential traces in the display panels in the adjacent rows are set to be the same, all the display panels in the mother board of the whole display panel may also be equipotentially connected, so as to improve the electrostatic protection capability of the whole display panel. Of course, the electric potentials of the medium-potential wirings in adjacent columns may also be set to be different, and this is not particularly limited herein.
In the above embodiment, the plurality of conductive pads in the first row of display panels in the same column are connected to the electrostatic short-circuit ring disposed in the first non-display area in the adjacent display panel in the next row through the short-circuit connection line, and the equipotential wiring disposed on the surface of the display panel is combined, so that all the display panels in the whole column can be equipotentially connected, static electricity generated by the display panel mother board in the testing or cutting process is eliminated, and the electrostatic protection effect of the display panel is improved.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a fifth embodiment of the display panel mother board of the present application, and the present embodiment is a further extension of the display panel mother board in the fourth embodiment, except that in this embodiment, the electrostatic short rings disposed in the non-display areas of the adjacent display panels in the same row are connected in series, and the serially connected electrostatic short rings are electrically connected to the plurality of conductive pads through the plurality of short-circuit lines of the display panel in the previous row, which is described in detail as follows:
as shown in fig. 6, the display panel mother board 100 provided in this embodiment includes a plurality of display panels 110 arranged in an array. A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. In this embodiment, a display panel motherboard 100 having 2 display panels 110 in the row direction and 2 display panels 110 in the column direction is also used for specific description.
In fig. 6, the non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, at least the non-display area 112 of the display panel 110 in the first row is provided with an electrostatic short-circuit ring 113, the first non-display area 115 defined at the upper border of all the display panels 110 in the second row in fig. 6 is provided with an electrostatic short-circuit ring, and each electrostatic short-circuit ring 113 in the row is connected in series, and the serially connected electrostatic short-circuit rings 113 are electrically connected to the plurality of conductive pads 1121 through the plurality of short-circuit lines 1122 of the display panel 110 in the previous row. In this embodiment, the material used for the electrostatic short-circuit ring 113, the specific location of the electrostatic short-circuit ring, and the impedance of the electrostatic short-circuit ring 113 are selected as in the first embodiment, and reference is made to the detailed description in the first embodiment, which is not repeated herein.
Optionally, in the present embodiment, an equipotential trace 1111 is disposed on the surface of each display panel 110 and connected to the display area 111, and the electrostatic short ring 113 is electrically connected to the equipotential trace 1111. In fig. 6, the equipotential traces 1111 of all the display panels 110 in the second row are respectively connected to the electrostatic short rings 113 of all the display panels 110 in the second row. Optionally, the number of the equipotential traces 1111 connecting each display panel 110 may be set to be multiple, and the electrostatic short ring 113 connects all the equipotential traces 1111, so that all the display panels 110 in the same column can be equipotentially connected, and the electrostatic short rings of all the display panels 110 in the same row are connected in series, so that all the display panel signals of the display panel motherboard 100 can be equipotentially connected, thereby eliminating static electricity generated by the display panel motherboard to the display panel in the first row during testing or cutting, and improving the electrostatic protection effect of the panel.
In addition, the electrostatic short ring 113 may also be designed as shown in fig. 7, that is, the electrostatic short ring 113 is configured to include a plurality of electrostatic short traces 1131 arranged at intervals. Specifically, referring to fig. 7, the technical solution shown in this embodiment is similar to the fourth embodiment of the display panel mother board, and the same parts are not described again, and are described as follows:
the display panel mother board 100 includes a plurality of display panels 110 arranged in an array, and a distance between adjacent display panels 110 is zero. A display area 111 and a non-display area 112 surrounding the display area 111 are defined on the surface of each display panel 110. The non-display area 112 of each display panel 110 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122, the first non-display area 116 defined by the upper frame of the second row of display panels 110 is provided with an electrostatic short-circuit ring 113, the electrostatic short-circuit ring 113 includes a plurality of electrostatic short-circuit traces 1131 arranged at intervals, and each electrostatic short-circuit trace 1131 is connected to the plurality of conductive pads 1121 through the plurality of short-circuit connection lines 1122 in the first row of display panels 110.
It can be understood that details regarding the position arrangement relationship between the electrostatic short-circuit ring and the conductive pad in this embodiment are described in the first to third embodiments, and are not described herein again.
Referring to fig. 7, in the present embodiment, equipotential traces 1111 are disposed on the surface of each display panel 110 and connected to the display area 111, wherein the number of the equipotential traces 1111 is several, and each of the electrostatic short traces 1131 is connected to the equipotential traces 1111, so that all the display panels 110 in the same row can be equipotentially connected, thereby eliminating static electricity generated during testing or cutting of the display panel motherboard and improving the electrostatic protection effect of the display panel.
It can be understood that if the electric potentials of the equipotential traces in the display panels in the adjacent columns are set to be the same, all the display panels in the whole display panel motherboard can be connected in an equipotential manner, so that the electrostatic protection capability of the whole display panel is improved.
In the above embodiment, the plurality of conductive pads in the display panel are connected to the electrostatic short-circuit ring arranged in the first non-display area in the adjacent display panel in the next row through the short-circuit connection line, and the equipotential wiring arranged on the surface of the display panel is combined, so that all the display panels can be subjected to equipotential connection, static electricity generated by a mother board of the display panel in a testing or cutting process is eliminated, and the electrostatic protection effect of the display panel is improved.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a display panel according to a first embodiment of the present disclosure, in which, as shown in fig. 8, the display panel 110 provided in the present disclosure defines a display region 111 and a non-display region 112 around the display region 111, and the non-display region 112 is provided with a plurality of conductive pads 1121 and a plurality of short-circuit connection lines 1122. One end of each of the short-circuit connection lines 1122 is connected to one of the conductive pads 1121, and the other end extends to the edge of the display panel 110, where the cross section of the edge is a cut or fired cross section of the mother substrate of the display panel during cutting, and is used for electrically connecting with another display panel in the mother substrate of the display panel during manufacturing. In particular, the electrostatic short-circuit ring can be used for electrically connecting with another display panel in the display panel mother board in the manufacturing process.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel of the present application according to a second embodiment, in which, as shown in fig. 9, the display panel 110 provided in the present application defines a display region 111 and a non-display region 112 at the periphery of the display region 111, and the non-display region 112 is provided with an electrostatic short ring 113, a plurality of conductive pads 1121 and a plurality of short connection lines 1122. The short-circuit connection line 1122 has one end connected to the electrostatic short-circuit loop line 113 and the other end extending to the edge of the display panel 110, where the cross section of the edge is a cut or burned cross section of the mother board of the display panel during cutting, and is used for electrical connection of another display panel connected to the mother board of the display panel during the manufacturing process.
The non-display area 112 of the display panel 110 at least includes a first non-display area 115 disposed adjacent to the display panel in the previous row, and the electrostatic short ring 113 is disposed in the first non-display area 115.
The display panel 110 is obtained by cutting the display panel mother board in the first to sixth embodiments, so the description of the display panel 110 is described in detail in the first to sixth embodiments, and is not repeated herein.
In summary, it is easily understood by those skilled in the art that the present application provides a display panel and a motherboard, in which a plurality of conductive pads of a display panel in a non-first row in the motherboard are connected to an adjacent display panel in a next row through a short-circuit connection line, so as to enable equipotential connection of all signals in the display panel, eliminate static electricity generated by the motherboard of the display panel to the display panel during a testing or cutting process, and improve an electrostatic protection effect of the panel.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A display panel mother board is characterized by comprising a plurality of display panels arranged in an array mode, wherein the display panels are arranged at a zero interval, a display area and a non-display area on the periphery of the display area are defined on the surface of each display panel, the non-display area is provided with a plurality of conductive gaskets and a plurality of short circuit connecting wires, and at least the non-display area of the display panel which is not the first row is provided with an electrostatic short circuit ring;
one end of each short circuit connecting line in each display panel in the same column is respectively connected to the conductive pads, the other end of each short circuit connecting line is electrically connected with the electrostatic short circuit ring of the adjacent display panel in the next row, and the display panel in the non-first row comprises the electrostatic short circuit ring and the conductive pads which are respectively positioned at two sides of the display area.
2. The display panel mother board according to claim 1, wherein the non-display region in the display panel includes at least a first non-display region disposed adjacent to an adjacent upper row of display panels, and the electrostatic short ring is disposed in the first non-display region.
3. The display panel motherboard according to claim 2, wherein each of the display panels comprises an encapsulation layer covering the display region and the non-display region, and the electrostatic short ring is disposed between the encapsulation layer covering the first non-display region and a substrate base plate of the display panel.
4. The display panel mother board according to claim 2, wherein the electrostatic short rings of each of the display panels in a same row are connected in series, and the serially connected electrostatic short rings are electrically connected to the conductive pads through the short lines of the display panels in a previous row.
5. The mother panel of claim 2, wherein the surface of each display panel is provided with equipotential traces connected to the display area, and the electrostatic shorting ring is connected to the equipotential traces.
6. The display panel motherboard according to claim 5, wherein the number of the equipotential traces of each display panel is several, the number of the corresponding electrostatic short-circuit rings is one, and the corresponding electrostatic short-circuit rings are connected to all the corresponding equipotential traces.
7. The display panel motherboard according to claim 5, wherein the number of the equipotential traces is several, the electrostatic short ring comprises several spaced electrostatic short traces, and each of the electrostatic short traces connects with the equipotential trace.
8. A display panel, which is formed by cutting the display panel mother board according to any one of claims 1 to 7, wherein the display panel defines a display area and a non-display area at the periphery of the display area, the non-display area is provided with a plurality of conductive pads and a plurality of short circuit connecting lines, and the non-display area has no electrostatic short circuit loop;
one end of each short circuit connecting line is connected to the conductive pads, and the other end of each short circuit connecting line extends to the edge of the display panel.
9. A display panel, which is formed by cutting the display panel mother board according to any one of claims 1 to 7, wherein the display panel defines a display area and a non-display area at the periphery of the display area, the non-display area is provided with an electrostatic short circuit loop, a short circuit connection line and a conductive pad, and the conductive pad and the electrostatic short circuit loop are respectively located at two sides of the display area;
one end of the short circuit connecting wire is connected to the electrostatic short circuit loop wire, and the other end of the short circuit connecting wire extends to the edge of the display panel.
10. The display panel according to claim 9, wherein the non-display region in the display panel comprises at least a first non-display region disposed adjacent to an adjacent upper row of the display panel, and the electrostatic short ring is disposed in the first non-display region.
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| CN201811291804.6A CN109449140B (en) | 2018-10-31 | 2018-10-31 | Display panel and mother board |
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| CN201811291804.6A CN109449140B (en) | 2018-10-31 | 2018-10-31 | Display panel and mother board |
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| CN110187575B (en) | 2019-05-28 | 2020-12-18 | 昆山国显光电有限公司 | Array substrate and array substrate mother board |
| CN111066143B (en) | 2019-06-03 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | Packaging structure and packaging method |
| CN110320720A (en) * | 2019-06-28 | 2019-10-11 | 昆山国显光电有限公司 | Display panel and preparation method thereof |
| CN110346994B (en) * | 2019-07-23 | 2022-07-08 | 昆山国显光电有限公司 | Array substrate and display panel |
| CN110379796A (en) * | 2019-07-31 | 2019-10-25 | 昆山国显光电有限公司 | Display panel and display device |
| CN110827688A (en) * | 2019-11-22 | 2020-02-21 | 昆山国显光电有限公司 | Display panel, display panel mother board and display device |
| CN110827692B (en) * | 2019-11-28 | 2022-02-01 | 昆山国显光电有限公司 | Mother board for manufacturing display panel |
| CN114270251B (en) * | 2020-06-15 | 2023-10-24 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN111653548A (en) * | 2020-06-18 | 2020-09-11 | 京东方科技集团股份有限公司 | Display substrate, display panel and preparation method thereof |
| CN113077726B (en) * | 2021-03-23 | 2022-06-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN113539087B (en) * | 2021-06-24 | 2022-12-23 | 上海中航光电子有限公司 | First display panel, second display panel, manufacturing method of second display panel and display device |
| CN115332232A (en) * | 2022-08-17 | 2022-11-11 | 合肥京东方光电科技有限公司 | Display panel, display device, panel and manufacturing method of display panel |
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| KR20080078089A (en) * | 2007-02-22 | 2008-08-27 | 삼성전자주식회사 | Display substrate and method for manufacturing the same, display apparatus |
| CN103296021B (en) * | 2012-06-29 | 2016-12-07 | 上海天马微电子有限公司 | TFT array substrate |
| CN103943611B (en) * | 2013-02-22 | 2016-11-23 | 上海天马微电子有限公司 | Array substrate and panel |
| CN106200180A (en) * | 2016-09-09 | 2016-12-07 | 武汉华星光电技术有限公司 | A kind of array base palte Electro-static Driven Comb preventer and method |
| CN107290900B (en) * | 2017-08-07 | 2019-11-12 | 上海中航光电子有限公司 | A kind of motherboard |
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