CN111128965A - Array substrate and display panel - Google Patents
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- CN111128965A CN111128965A CN201911296746.0A CN201911296746A CN111128965A CN 111128965 A CN111128965 A CN 111128965A CN 201911296746 A CN201911296746 A CN 201911296746A CN 111128965 A CN111128965 A CN 111128965A
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- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 238000009413 insulation Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present disclosure provides an array substrate and a display panel. The array substrate comprises a first metal layer, a grid electrode insulating layer and a second metal layer which are stacked. And a grid insulating layer photomask designed with a digital mark is used for manufacturing the digital mark on the grid insulating layer and marking the signal line of the first metal layer. And part of signal wires of the second metal layer cover the digital marks, so that the numbers of the digital marks are displayed through the second metal layer. To alleviate the problem of limited design space for digital signage.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display panel.
Background
In the structure design of the array substrate of the existing display panel, the portions of the first metal layer and the second metal layer that need to be conducted are generally implemented by designing deep and shallow holes. However, the design of deep and shallow holes easily causes the problems of poor signal line bridging between the first metal layer and the second metal layer, undercut of deep holes, and the like. Therefore, in some product designs, a gate insulating layer mask is separately formed to achieve the conduction between the first metal layer and the second metal layer, so as to improve the problems of poor signal line bridging, undercut, and the like.
With the improvement of the requirements of the display panel, the existing display panel needs to meet the requirements of higher and higher resolution and faster refresh rate. However, the same size of display panel can satisfy the requirement of high resolution and high refresh rate, and the in-plane design wiring density is increased, which results in limitation of some required module designs, such as digital labels. As shown in fig. 1, the digital sign of the conventional design is formed of the first metal layer M1, but in order to prevent the digital sign from being short-circuited to the signal line of the first metal layer M1 (position 1) and from overlapping the signal line of the second metal layer M2 (especially when the metal film layer is thick) (positions 2 and 3), a sufficient space is left between the digital sign and the signal line. But such a design would result in some signal line widths of the second metal layer M2 being thinned (position 4) on the one hand, and impedance being increased; on the other hand, the digital sign design space is extremely limited (L1), because the signal line spacing L2 is constant. Under the normal condition, when the line width of the digital mark is larger than 2.2 micrometers, the digital mark can be normally exposed to identify numbers so as to be convenient for using at stations such as interior line (Inline) repair and the like, but along with the limitation of the design space of the digital mark, the line width of the digital mark is 1 micrometer, the normal exposure display cannot be performed at the moment, the use condition of an Inline process can be influenced, and the production yield of a panel is reduced.
Therefore, the problem that the design space of the existing digital identifier is limited needs to be solved.
Disclosure of Invention
The disclosure provides an array substrate and a display panel, which are used for relieving the technical problem that the design space of the existing digital mark is limited.
In order to solve the above problems, the technical solution provided by the present disclosure is as follows:
the embodiment of the disclosure provides an array substrate, which includes a first metal layer, a gate insulating layer and a second metal layer. The first metal layer is patterned to form a plurality of first signal lines arranged at intervals. The grid electrode insulating layer covers the first metal layer and comprises a patterned digital mark. The second metal layer is arranged on the grid insulation layer, and a plurality of groups of signal line groups arranged at intervals are formed in a patterning mode, wherein each group of signal line groups comprises at least one second signal line. Wherein, there is interval between the first signal line and the second signal line, the second signal line covers above the digital mark.
In the array substrate provided by the embodiment of the disclosure, each group of signal line groups further includes a third signal line and a fourth signal line, the second signal line, the third signal line and the fourth signal line are sequentially arranged and spaced from each other, and the first signal line is located below the third signal line and the fourth signal line in a spaced manner.
In the array substrate provided by the embodiment of the present disclosure, a width of the second signal line is smaller than a first interval between the third signal line in the same signal line group and the fourth signal line in a previous signal line group.
In the array substrate provided by the embodiment of the disclosure, the first interval is less than 30 micrometers.
In the array substrate provided by the embodiment of the disclosure, the gate insulating layer is patterned to form a convex shape, and the digital mark is composed of the convex shape.
In the array substrate provided by the embodiment of the disclosure, the gate insulating layer is patterned to form a groove shape, and the number mark is composed of the groove shape.
In the array substrate provided by the embodiment of the disclosure, the width of the second signal line is greater than or equal to the width of the digital mark.
In the array substrate provided by the embodiment of the disclosure, the length of the second signal line is greater than the length of the digital mark.
In the array substrate provided by the embodiment of the disclosure, the thickness of the second signal line is greater than that of the digital mark.
The embodiment of the present disclosure further provides a display panel, which includes the array substrate according to one of the foregoing embodiments of the present disclosure.
The beneficial effects of this revelation do: in the array substrate and the display panel provided by the disclosure, the array substrate comprises a first metal layer, a gate insulating layer and a second metal layer which are stacked. Wherein a protrusion shape or a groove shape is provided as a numeral mark on the gate insulating layer. And part of signal wires of the second metal layer cover the digital marks, so that the numbers of the digital marks are displayed through the second metal layer. The design space of the digital mark is enlarged, so that the digital mark is easier to be exposed and displayed, and the problem of limited design space of the digital mark is solved. Meanwhile, the line width of the signal line covered on the digital mark is increased, and the impedance of the signal line is reduced.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic bottom view of an array substrate in the prior art;
fig. 2 is a first bottom view of an array substrate according to an embodiment of the disclosure;
fig. 3 is a schematic view illustrating a first film layer structure of an array substrate according to an embodiment of the disclosure;
fig. 4 is a second bottom view of the array substrate according to the embodiment of the disclosure;
fig. 5 is a schematic view illustrating a second film layer structure of an array substrate according to an embodiment of the disclosure;
fig. 6 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the disclosure;
FIG. 7 is a first structural diagram of a display panel according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of a second structure of a display panel according to an embodiment of the disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure. In the drawings, elements having similar structures are denoted by the same reference numerals.
In one embodiment, as shown in fig. 2, an array substrate 100 is provided, which includes a first metal layer, a gate insulating layer and a second metal layer (only the patterned patterns of the layers are shown in the figure because fig. 2 is a bottom view of the array substrate). The first metal layer is patterned to form a plurality of first signal lines 11 arranged at intervals. The gate insulating layer covers the first metal layer, the gate insulating layer includes a patterned digital mark 21, and the digital mark 21 is used for marking the first signal line 11. The second metal layer is disposed on the gate insulating layer, and a plurality of groups of signal lines (such as G1 and G2 in fig. 2) are patterned, wherein each group of signal lines comprises at least one second signal line 31 (such as G2 and G1 in fig. 2 do not show the second signal line). Wherein, there is a space between the first signal line 11 and the second signal line 31, and the second signal line 31 is covered above the digital mark 21.
Specifically, each group of signal lines further includes a third signal line 32 and a fourth signal line 33, the second signal line 31, the third signal line 32, and the fourth signal line 33 are sequentially arranged and spaced from each other, and the first signal line 11 is located below the third signal line 32 and the fourth signal line 33.
Further, the width L3 of the first signal line 11 is equal to the interval S1 between the third signal line 32 and the fourth signal line 33 in the same signal line group.
Specifically, the number 21 of the present disclosure is illustrated by the number "538", but is not limited thereto. The number mark 21 is mainly used for marking the first signal line 11 of the first metal layer, and is arranged in sequence according to the arrangement order of the signal lines by using arabic numbers or other marks easy to distinguish, for example, "1, 2, 3.
Further, the corresponding relationship between the digital identifier 21 and the first signal line 11 is: each group of signal lines corresponds to one first signal line 11, and the digital mark 21 covered by the second signal line 31 in each group of signal lines is used to mark the first signal line 11 corresponding to the group of signal lines. The numeral 21 shown in fig. 2 identifies the first signal line 11 corresponding to the signal line group G2 in which the second signal line 31 is located.
In this embodiment, the digital mark is arranged on the gate insulating layer, the second signal line covers the digital mark, the digital mark is displayed through the second signal line, the digital mark is enlarged in a limited space, the digital mark is convenient to identify, the problem that the design space of the digital mark is limited is solved, and meanwhile, a gap is formed between the second signal line and the first signal line, so that short circuit is avoided.
In one embodiment, as shown in the array substrate 100 of fig. 2, the width L4 of the second signal line 31 is smaller than the first interval S2 between the third signal line 32 of the same signal line group (e.g., group G2 in fig. 2) and the fourth signal line 33 of the previous signal line group (e.g., group G1 in fig. 2). The last signal line group in this disclosure means that the signal line groups are arranged in sequence, and the signal line group before a certain signal line group, such as the group before the group G2 in fig. 2, is the group G1.
In particular, the first spacing S2 is less than 30 microns.
Further, the width L4 of the second signal line 31 is equal to the width L5 of the digital mark 21.
Further, the length of the second signal line 31 is greater than the length of the digital mark 21.
Further, the gate insulating layer is patterned to form a convex shape, and the digital mark 21 is composed of the convex shape.
Specifically, as shown in fig. 3, the schematic diagram of the film structure of the array substrate 100 shown in fig. 2 includes a first metal layer, a gate insulating layer, and a second metal layer stacked on a substrate 40. The first metal layer is patterned to form a first signal line 11, the gate insulating layer includes a patterned digital mark 21, and the second metal layer is patterned to form a second signal line 31, a third signal line 32, and a fourth signal line 33. Wherein the second signal line 31 is overlaid on the digital mark 21.
Specifically, the material of the first metal layer and the second metal layer may be a metal such as copper, molybdenum, or the like.
Further, the material of the gate insulating layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof.
Specifically, the gate insulating layer is patterned by using a gate insulating layer mask designed with a numerical identifier to form a convex shape, and the required numerical identifier 21 is composed of the convex shape.
It should be noted that the design of the gate insulating layer mask with the numerical identifier is a mask that is separately provided to make a part of the first metal layer and a part of the second metal layer conductive. That is, the required digital mark 21 is manufactured while the required via hole for conducting the first metal layer and the second metal layer is manufactured by using the photomask.
Specifically, a layer of photoresist is coated on the gate insulating layer where the digital mark region is to be formed, the coated photoresist layer is exposed through the shielding of a mask of the gate insulating layer to form an exposed region of the digital mark region, then the exposed region of the digital mark region is developed to obtain a raised pattern, and then the raised pattern is etched to form a raised shape, i.e., the required digital mark 21.
Further, a second metal layer is prepared on the gate insulating layer, the second metal layer is patterned, and a second signal line 31 is formed to cover the digital mark 21. Since the digital mark 21 is in a convex shape, the second signal line 31 also has an uneven shape after the second signal line 31 is covered on the digital mark 21. This rugged undulating shape is a digital word shape in which the digital mark 21 appears through the second signal line 31.
Further, the thickness of the second signal line 31 is larger than that of the digital mark 21.
Specifically, the thickness of the digital mark 21 is the height of a protrusion formed by patterning the gate insulating layer, and the height of the protrusion is the normal film thickness of the gate insulating layer. The thickness of the gate insulating layer is typically 400 to 520 nm. The thickness of the second signal line 31 is the normal film thickness of the second metal layer, and is generally 500 to 800 nm.
Furthermore, when the internal line detection and repair is performed on the display panel, the recognition device directly recognizes the shape of the digital word appearing on the second signal line 31, so as to recognize the digital mark 21, and further determine the first signal line 11 corresponding to the digital mark 21.
Specifically, the digital mark 21 is provided on the gate insulating layer, and the second signal line 31 is covered on the digital mark 21. The digital mark 21 and the second signal line 31 which are arranged side by side originally are arranged up and down, and limited space is fully utilized. The font of the digital mark 21 and the width of the second signal line 31 are increased, so that the identification device can identify the digital mark 21 more conveniently and accurately and the impedance of the second signal line 31 is reduced.
In one embodiment, unlike the above-described embodiments, the width L4 'of the second signal line 31' is greater than the width L5 of the digital sign 21. In the array substrate 101 shown in fig. 4, the length of the second signal line 31' is greater than the length of the digital mark 21.
Specifically, the width L4 'of the second signal line 31' is smaller than the first interval S2 between the third signal line 32 in the same signal line group and the fourth signal line 33 in the previous signal line group.
Further, the width L3 of the first signal line 11 is equal to the space S1 between the third signal line 32 and the fourth signal line 33 in the same signal group.
In another embodiment, the digital mark 21' is formed by a groove shape formed by patterning the gate insulating layer.
Specifically, as shown in fig. 5, the film structure of the array substrate 103 includes a first metal layer, a gate insulating layer and a second metal layer stacked on a substrate 40. The first metal layer is patterned to form a first signal line 11, the gate insulating layer includes a patterned digital mark 21', and the second metal layer is patterned to form a second signal line 31 ", a third signal line 32, and a fourth signal line 33.
Specifically, the gate insulating layer is patterned by a gate insulating layer mask designed with a numerical identifier, so that a groove shape is obtained.
Specifically, a layer of photoresist is coated on the gate insulating layer where the digital mark region is to be formed, the coated photoresist layer is exposed through the shielding of a mask of the gate insulating layer to form an exposed region of the digital mark region, the exposed region of the digital mark region is developed to obtain a groove pattern, and the groove pattern is etched to form a groove shape, i.e., the required digital mark 21'.
Further, a second metal layer is prepared on the gate insulating layer, the second metal layer is patterned, and a second signal line 31 ″ is formed to cover the digital mark 21'.
Specifically, the surface of the second signal line 31 ″ forms an uneven undulation shape to show the digital mark 21'.
It should be noted that the difference between the digital mark of the present disclosure and the convex shape or the concave shape is that the convex shape indicates the number of the digital mark, that is, after the gate insulating layer is exposed and developed, the gate insulating layer in the digital mark region is etched away except for the required number, and only the required number is left. The groove shape composition means that the number forming the number mark is empty, namely, after the gate insulation layer is exposed and developed, the needed number in the number mark area is etched away, and the gate insulation layer except the number is left. For other descriptions, please refer to the above embodiments, which are not repeated herein.
In an embodiment, a method for manufacturing an array substrate is provided, taking the array substrate shown in fig. 3 as an example, which includes the following steps, as shown in fig. 6:
step S1: preparing a first signal line, including providing a substrate, preparing a first metal layer on the substrate, and patterning to obtain a first signal line;
step S2: preparing a digital mark, wherein the preparation comprises the steps of preparing a grid electrode insulating layer on the first metal layer, patterning to obtain a convex shape, and forming the digital mark by the convex shape;
step S3: and preparing a second signal line, wherein the step of preparing the second metal layer on the grid insulating layer and patterning to obtain a second signal line, a third signal line and a fourth signal line, and the second signal line covers the digital mark.
Specifically, in step S2, a photoresist layer is coated on the gate insulating layer where the digital mark region is to be formed, the coated photoresist layer is exposed through the shielding of the mask designed with the digital mark for the gate insulating layer to form an exposed region of the digital mark region, the exposed region of the digital mark region is developed to obtain a raised pattern, and the raised pattern is etched to form a raised shape, i.e., the required digital mark.
Specifically, in step S3, a second metal layer is formed on the gate insulating layer, the second metal layer is patterned, and a second signal line is formed to cover the digital mark. Because the digital mark is in a convex shape, the second signal wire also presents an uneven undulation shape after the second signal wire covers the digital mark. The rugged up-and-down shape is the shape of the digital word displayed by the digital mark through the second signal wire.
Further, the width of the first signal line is equal to the interval between the third signal line and the fourth signal line of the same signal line group.
Further, the width of the second signal line is smaller than a first interval between the third signal line in the same signal line group and the fourth signal line in the previous signal line group.
In particular, the first spacing is less than 30 microns.
Further, the width of the second signal line is equal to the width of the digital mark.
Further, the thickness of the second signal line is larger than that of the digital mark.
Specifically, the thickness of the second signal line is 500 to 800 nanometers, and the thickness of the digital mark is 400 to 520 nanometers.
In an embodiment, as shown in fig. 7, a liquid crystal display panel 1000 is provided, which includes the array substrate 100 according to one of the foregoing embodiments, a color filter substrate 200 disposed opposite to the array substrate 100, and a plurality of liquid crystals 300 disposed between the array substrate 100 and the color filter substrate 200.
In another embodiment, an OLED display panel 1001 is provided, as shown in fig. 8, and includes the array substrate 100, the light emitting function layer 400 disposed on the array substrate 100, and the encapsulation layer 500 disposed on the light emitting function layer 400 according to one of the foregoing embodiments.
According to the above embodiments:
in the array substrate, the preparation method thereof and the display device provided by the disclosure, the array substrate comprises a first metal layer, a gate insulating layer and a second metal layer which are stacked. A grid insulating layer photomask with a digital mark is used for arranging a convex shape or a groove shape on the grid insulating layer to serve as the digital mark for marking the signal line of the first metal layer. And part of signal wires of the second metal layer cover the digital marks, so that the numbers of the digital marks are displayed through the second metal layer. The design space of the digital mark is enlarged, so that the digital mark is easier to be exposed and displayed, and the problem of limited design space of the digital mark is solved. Meanwhile, the line width of the signal line covered on the digital mark is increased, and the impedance of the signal line is reduced.
In summary, although the present disclosure has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so that the scope of the present disclosure is defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
the first metal layer is patterned to form a plurality of first signal lines arranged at intervals;
the grid insulation layer covers the first metal layer and comprises a patterned digital mark; and
the second metal layer is arranged on the grid insulation layer and is patterned to form a plurality of groups of signal line groups arranged at intervals, and each group of signal line groups comprises at least one second signal line;
wherein, there is interval between the first signal line and the second signal line, the second signal line covers above the digital mark.
2. The array substrate of claim 1, wherein each of the signal line groups further comprises a third signal line and a fourth signal line, the second signal line, the third signal line and the fourth signal line are sequentially arranged and spaced apart from each other, and the first signal line is located relatively below the space between the third signal line and the fourth signal line.
3. The array substrate of claim 2, wherein the width of the second signal line is smaller than a first interval between the third signal line in the same signal line group and the fourth signal line in a previous signal line group.
4. The array substrate of claim 3, wherein the first spacing is less than 30 microns.
5. The array substrate of claim 3, wherein the gate insulating layer is patterned to form a convex shape, and the digital mark is composed of the convex shape.
6. The array substrate of claim 3, wherein the gate insulating layer is patterned to form a groove shape, and the digital mark is composed of the groove shape.
7. The array substrate of claim 5 or 6, wherein the width of the second signal line is greater than or equal to the width of the digital mark.
8. The array substrate of claim 7, wherein the length of the second signal line is greater than the length of the digital mark.
9. The array substrate of claim 8, wherein the second signal line has a thickness greater than a thickness of the digital mark.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| CN201911296746.0A CN111128965B (en) | 2019-12-16 | 2019-12-16 | Array substrate and display panel |
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| CN201911296746.0A CN111128965B (en) | 2019-12-16 | 2019-12-16 | Array substrate and display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111799245A (en) * | 2020-06-18 | 2020-10-20 | 宁波芯健半导体有限公司 | Chip identification method and chip with identification |
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| CN111128965B (en) | 2022-05-31 |
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