CN113782545B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN113782545B CN113782545B CN202110972622.0A CN202110972622A CN113782545B CN 113782545 B CN113782545 B CN 113782545B CN 202110972622 A CN202110972622 A CN 202110972622A CN 113782545 B CN113782545 B CN 113782545B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133354—Arrangements for aligning or assembling substrates
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
The application discloses array substrate and display panel, the array substrate of this application include the metal level and with the counterpoint mark of metal level homostorey setting, the counterpoint mark includes the mark body and forms at least a segmentation clearance on the mark body, wherein the segmentation clearance will the mark body is split into a plurality of sub-divisions. The array substrate and the display panel can prevent the photoresist on the alignment mark from being stripped, and further can prevent the photoetching from affecting the etching of a channel region of a thin film transistor, so that a product is scrapped, and finally the yield of the product can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel which can improve the product yield and are simple in manufacturing process.
Background
At present, in the alignment process of manufacturing color resists such as a red resist (R), a green resist (G), and a blue resist (B), alignment marks (mark) need to be respectively disposed on a color film substrate or an array substrate, and then the color film substrate or the array substrate and a mask are aligned by the alignment marks, followed by exposure.
For the convenience of identification of the exposure machine and for the manufacture of the alignment mark, the area of the existing alignment mark is generally large. Referring to fig. 1 and 2, the conventional alignment mark 900 is generally a rectangular mark with a specification of 4 × 16um.
Currently, when the color resist layer is fabricated on the array substrate, the alignment mark pattern applied to the color resist layer is generally disposed on the same layer as the metal layer of the array substrate. For example, the alignment mark is generally disposed on the same layer as the gate. In the patterning process of the subsequent metal layer of the array substrate, the Photoresist (PR) 901 on a portion of the alignment mark 900 may be stripped or peeled off due to the large area of the conventional alignment mark 900. For example, in the conventional arrangement of sub-pixels, the photoresist on the alignment mark (G mark) of the green sub-pixel is easily stripped or peeled off.
The peeled photoresist 901 may affect the subsequent manufacturing process of the array substrate. For example, the removed photoresist 901 may affect the etching of the source and drain metal layers of the TFT in the channel region (e.g., cause AS residue in the channel region of the TFT), thereby resulting in product rejection.
If the size of the alignment mark is reduced, the manufacturing difficulty of the alignment mark is increased, and the position accuracy of the alignment mark is also reduced. In addition, the variation in the size of the alignment marks also limits the accuracy range of the exposure machine, so that the alignment marks may not be recognized by the exposure machine with partial accuracy.
Therefore, it is desirable to provide an array substrate and a display panel to solve the above technical problems.
Disclosure of Invention
In order to solve the above technical problem, the present application provides an array substrate and a display panel, which can prevent a photoresist on an alignment mark from being stripped, and further prevent the stripped photoresist from affecting a subsequent thin film transistor process, and finally improve a product yield.
In order to achieve the above purpose, the array substrate and the display panel according to the present application adopt the following technical solutions.
The application provides an array substrate, includes:
a metal layer; and
the alignment mark structure comprises a mark body and at least one dividing gap formed on the mark body, and the dividing gap divides the mark body into a plurality of sub-parts.
Optionally, in some embodiments, the dividing gap is located between two oppositely disposed sides of the marker body and extends from one of the two sides to the other of the two sides.
Optionally, in some embodiments, the segmentation gap comprises a first segmentation gap and a second segmentation gap that intersect perpendicularly;
wherein the first dividing gap is positioned between two side edges of the mark body which are oppositely arranged along the length direction; and the number of the first and second groups,
the second division gap is located between two opposite side edges of the mark body in the length direction.
Optionally, in some embodiments, the first separation gap has a gap width of 1 μm to 2 μm, and the second separation gap has a gap width of 1 μm to 4 μm.
Optionally, in some embodiments, a plurality of the sub-sections are independent of each other.
Optionally, in some embodiments, the areas of the plurality of sub-portions are the same or different.
Optionally, in some embodiments, the width of the subsection ranges from 1 μm to 2 μm and the length of the subsection ranges from 4 μm to 6 μm.
Correspondingly, this application still provides a display panel includes the array substrate of this application.
Optionally, in some embodiments, the display panel has a plurality of pixel units, each of the pixel units includes at least one sub-pixel, and the alignment mark is located in the sub-pixel.
Optionally, in some embodiments, each of the sub-pixel units includes a green sub-pixel, a red sub-pixel, and a blue sub-pixel, and the alignment mark is located in the green sub-pixel.
Compared with the prior art, this application array substrate and display panel divide the clearance through forming on the mark body, divide into a plurality of mutually spaced subportions with the mark body, and enable to keep the holistic scope of mark body is almost invariable, and then can overcome the film transistor's that the photoetching glue that exists owing to current counterpoint mark drops easily and leads to badly, can also prevent the problem that the preparation degree of difficulty of counterpoint mark that leads to diminishes and the position precision reduces because the area of counterpoint mark. The alignment mark manufacturing process in the application is simple and has high practicability. In addition, in the alignment mark of the present application, the plurality of sub-portions can be set to different areas, respectively, so that the recognition accuracy and the recognition speed of the exposure machine can be improved, and the limitation on the accuracy of the exposure machine can be overcome.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional alignment mark.
FIG. 2 is a schematic diagram of the alignment mark process shown in FIG. 1.
Fig. 3 is a schematic diagram of alignment marks according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present application, are given by way of illustration and explanation only, and are not intended to limit the present application. In this application, where the context requires otherwise, the words "upper" and "lower" used in relation to the device in use or operation will generally refer to the upper and lower extremities of the device, particularly as oriented in the drawing figures; while "inner" and "outer" are with respect to the outline of the device.
The application provides an array substrate and include array substrate's display panel to solve the photoresist on the counterpoint mark and peel off, and then can prevent that the photoresist that peels off from influencing subsequent thin film transistor processing procedure, can promote the product yield finally.
The array substrate comprises a metal layer and an alignment mark. The alignment mark and the metal layer are arranged on the same layer, the alignment mark structure comprises a mark body and at least one dividing gap formed on the mark body, and the dividing gap divides the mark body into a plurality of sub-parts.
Fig. 3 is a schematic diagram of the alignment mark 100 of the present application. As shown in fig. 3, the alignment mark 100 of the present application can be used to mark a sub-pixel, so as to solve the problem that the photoresist on the sub-pixel alignment mark 100 is easy to strip, and prevent the problems of increased difficulty in manufacturing the alignment mark 100 and reduced position accuracy.
As shown in fig. 3, the alignment mark 100 of the present application includes a mark body 10 and at least one dividing gap 20 formed on the mark body 10. The dividing gap 20 divides the marker body 10 into a plurality of sub-portions 11.
Specifically, the adjacent sub-sections 11 are separated by the dividing gap 20, and the dividing gap 20 is located between the adjacent two sub-sections 11. More preferably, a plurality of said sub-portions 11 are independent of each other.
Obviously, in the solution of the present application, the mark body 10 is divided into a plurality of independent sub-portions 11 by forming the dividing gaps 20 in the alignment mark 100. On the other hand, since the sub-portions 11 have a smaller area than the conventional alignment mark 100, the problem that Photoresist (PR) is easily stripped off due to an excessively large area of the PR on each sub-portion 11 is prevented. On the other hand, compared to the conventional alignment mark 100, the layout range of the entire mark body 10 of the present invention is not significantly reduced, and the problems of increased difficulty in manufacturing the alignment mark 100 and reduced positional accuracy due to the change in the area or position of the alignment mark 100 can be prevented.
Finally, the alignment mark 100 of the present application can be obtained by etching one or more dividing gaps 20 on the mark body 10, and has the advantages of strong feasibility and simple process.
An embodiment of the alignment mark 100 of the present application will be described in detail below with reference to fig. 3.
Referring to fig. 3, the alignment mark 100 includes a mark body 10 and a dividing gap 20 formed on the mark body 10.
Referring to fig. 3, the overall planar shape of the mark body 10 is rectangular. In other embodiments, the overall shape of the marker body 10 may also be circular or directional. In other embodiments, the tag body 10 may be irregularly shaped. Obviously, the present application does not limit the planar shape of the tag body 10.
In this embodiment, the length of the mark body 10 is 16um, and the width of the mark body 10 is 4um. It should be noted that the size of the marking body 10 is not limited in nature.
In a preferred embodiment, the material of the marker body 10 is a metal material. For example, in the present embodiment, the material of the alignment mark 100 is copper.
Referring to fig. 3, the dividing gaps 20 are formed on the alignment mark 100 to divide the alignment mark 100 into a plurality of sub-portions 11.
Specifically, the mark body 10 has a plurality of side edges, and the dividing gap 20 extends from one of the side edges to another different side edge. In this way, the dividing gap 20 can divide the marker main body 10 into a plurality of sub-portions 11.
Referring to fig. 3, in the present embodiment, the dividing gap 20 is located between two oppositely disposed side edges, and the dividing gap extends from one of the two side edges to the other of the two side edges.
In the present embodiment, the dividing gap 20 includes a first dividing gap 21 and a second dividing gap 22 perpendicular to each other, wherein the first dividing gap 21 is located between two side edges of the mark body 10 that are oppositely arranged in the vertical direction, and the second dividing gap 22 is located between two side edges of the mark body 10 that are oppositely arranged in the vertical direction.
Specifically, the slit width of the first division gap 21 is set to 1-2 μm and the slit width of the second division gap 22 is set to 1-4 μm in consideration of the level of the existing etching process and the specification of the marking body 10. In a preferred embodiment, the first division gap 21 has a gap width of 2 μm and the second division gap 22 has a gap width of 4 μm.
It should also be noted that the arrangement of the dividing gap 20 shown in fig. 3 is merely an exemplary embodiment, and the present application is not limited thereto. In a specific implementation, the alignment mark 100 may be divided into a plurality of sub-sections 11.
For example, in some embodiments, the alignment mark 100 may include only one or more first division gaps 21, and may also include only one or more second division gaps 22. In a specific implementation, a plurality of second dividing gaps 22 arranged in parallel at intervals may be formed on the alignment mark 100 to divide the alignment mark 100 into a plurality of sub-portions 11 arranged in parallel and at intervals.
In the present embodiment, the dividing gap 20 is arranged in a manner perpendicular to the two side edges of the mark body 10. However, it should be noted that the extending direction and the extending angle of the dividing gap 20 are not limited in the present application. For example, in some embodiments, the separation gap 20 is located between the two sides of the mark body 10.
Of course, the present application also does not limit the extending direction of the dividing gap 20.
Referring to fig. 3, the marking body 10 includes a plurality of independent sub-portions 11 except for a region where the dividing gap 20 is formed. Wherein any adjacent two of the sub-sections 11 are separated by the dividing gap 20.
Specifically, a plurality of the sub-sections 11 are arranged in a matrix form. Referring to fig. 3, in the present embodiment, the alignment mark 100 is divided into four sub-portions 11 by the first dividing gap 21 and the second dividing gap 22, and the four sub-portions 11 are arranged in two vertical rows and two vertical columns.
Specifically, in the positioning mark 100 of the present application, the planar shape and/or the area of the plurality of sub-portions 11 may be the same or different. Of course, the planar shape and area of the plurality of sub-sections 11 may be the same for the convenience of manufacturing the sub-sections 11. In other embodiments, a plurality of the sub-sections 11 may be provided in a plurality of different areas, so that different sub-sections 11 can be recognized by a plurality of exposure machines with different accuracies, respectively.
It is to be noted that the arrangement of the sub-portions 11 described in fig. 2 is only an exemplary embodiment of the present application. The number, shape, area or arrangement of the sub-portions 11 is not limited in this application. In the implementation, the number, shape, area or arrangement of the sub-portions 11 may be adjusted according to the etching process or the alignment requirement.
In practical implementation, the arrangement of the sub-portions 11 can be adjusted by adjusting the size, position or shape of the dividing gaps 20.
Specifically, the width of the sub-part 11 ranges from 1 μm to 2 μm, and the length of the sub-part 11 ranges from 4 μm to 6 μm. In a preferred embodiment, the width of the sub-portion 11 is 1 μm, and the length of the sub-portion 11 is 6 μm.
Based on the same inventive concept, the application also provides a display panel, which comprises a display area and a non-display area, wherein the display area is divided into a plurality of pixel units. Each pixel unit comprises at least one sub-pixel. The display panel of the present application further includes the alignment mark 100 of the present application, and the alignment mark 100 is located in the sub-pixel.
First, the alignment mark 100 is specifically used for alignment exposure in the manufacturing process of which film layer on the array substrate, and this is not limited. For example, the alignment mark 100 pattern may be used for making a red resist, the alignment mark 100 pattern may be used for making a green resist, and the alignment mark 100 pattern may be used for making a blue resist.
Second, the alignment marks 100 in the sub-pixels with different colors may be the same or different, and this application is not limited in this respect. Of course, the alignment marks 100 in the sub-pixels of different colors may be arranged in different structures for easy distinction.
Third, the material of the alignment mark 100 pattern is not limited, and may be the same as or different from the material of the film layer existing on the array substrate. In addition, the alignment mark 100 and the film layer on the array substrate may be fabricated simultaneously, or the alignment mark 100 may be fabricated separately.
Specifically, the pixel unit comprises a red sub-pixel, a green sub-pixel and a blue sub-pixel. The alignment mark 100 is located in the green sub-pixel.
The display panel is a liquid crystal display panel, and may include an array substrate, a color film substrate, and a liquid crystal layer sealed between the array substrate and the color film substrate.
Specifically, the alignment mark 100 is disposed in the array substrate.
The array substrate comprises a substrate, and a thin film transistor, a common electrode, a pixel electrode, a gate line, a data line and the like which are formed on the substrate, wherein the thin film transistor is used as a switching device of a sub-pixel in the display panel. The grid electrode of the thin film transistor is connected with the grid line of the display panel and is connected with the grid scanning circuit through the grid line, the source electrode of the thin film transistor is connected with the data line and is connected with an integrated circuit chip (IC) through the data line, the drain electrode of the thin film transistor is connected with the pixel electrode, voltage is loaded to the pixel electrode through the data line, an electric field is formed between the pixel electrode and the common electrode, and then liquid crystal molecules of the liquid crystal layer deflect in the electric field, so that whether light is emitted or not is controlled, and display of the display panel is achieved.
Specifically, the array substrate includes a plurality of thin film transistors as switching devices of pixel units, including a gate electrode, a source electrode, a drain electrode, and an active layer. Optionally, a gate insulating layer is disposed between the gate and the active layer, an interlayer insulating layer is disposed between the gate and the film layers where the source and the drain are located, and a passivation layer is further disposed on the source and the drain.
In a specific implementation, the thin film transistor may be a top-gate thin film transistor or a bottom-gate thin film transistor. The specific type of the thin film transistor is not particularly limited in the present application.
Specifically, the alignment mark 100 is disposed on the same layer as the gate of the thin film transistor. In the display panel provided by the embodiment, the alignment mark 100 located on the array substrate and the gate of the thin film transistor in the array substrate are arranged on the same layer, and are manufactured in the same etching process as the gate during manufacturing, so that the performance reliability of the display panel is ensured, and meanwhile, a new film structure is not added to meet the thinning requirement.
Specifically, a preset mark area is arranged in a sub-pixel of the array substrate. The predetermined mark area refers to a predetermined or reserved area for arranging or forming the alignment mark 100. Obviously, the alignment mark 100 of the present application is located in the preset mark area.
In a preferred embodiment, the outer edge of the alignment mark 100 overlaps with the outer edge of the predetermined mark region.
Obviously, the arrangement position and the area range of the mark body 10 of the present application are kept unchanged, so that the manufacturing difficulty and the precision of the alignment mark 100 are not affected, and thus, the problems of increased manufacturing difficulty of the alignment mark 100, lowered position precision of the alignment mark 100, and the like caused by the change of the structure and the size of the alignment mark 100 can be prevented to a great extent. Meanwhile, since the mark main body is divided into a plurality of sub-portions 11, PR on the mark main body is also divided into a plurality of independent regions, so that the PR area can be prevented from being excessively large.
In a preferred embodiment, the outer edge of the alignment mark 100 overlaps the outer edge of the predetermined mark region.
The alignment mark and the display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (9)
1. An array substrate, comprising:
a metal layer; and
the alignment mark structure comprises a mark body and at least one dividing gap formed on the mark body, and the dividing gap divides the mark body into a plurality of sub-parts;
the dividing gap is positioned between two oppositely arranged side edges of the mark body, and one of the two side edges extends to the other side edge;
wherein the dividing gaps include a second dividing gap having a gap width of 1 μm to 4 μm.
2. The array substrate of claim 1, wherein the dividing gap further comprises a first dividing gap intersecting the second dividing gap;
wherein the first dividing gap is positioned between two side edges of the mark body which are oppositely arranged along the length direction;
the second division gap is located between two opposite side edges of the mark body in the length direction.
3. The array substrate of claim 2, wherein the first division gap has a gap width of 1 μm to 2 μm.
4. The array substrate of claim 1, wherein the plurality of sub-portions are independent of each other.
5. The array substrate of claim 1, wherein the sub-portions have the same or different areas.
6. The array substrate of claim 1, wherein the sub-portion has a width in a range of 1 μ ι η to 2 μ ι η and a length in a range of 4 μ ι η to 6 μ ι η.
7. A display panel comprising the array substrate according to any one of claims 1 to 6.
8. The display panel of claim 7, wherein the display panel has a plurality of pixel units, each of the pixel units comprises at least one sub-pixel, and the alignment mark is located in the sub-pixel.
9. The display panel of claim 8, wherein each of the sub-pixel units comprises a green sub-pixel, a red sub-pixel and a blue sub-pixel, and the alignment mark is located in the green sub-pixel.
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