CN116661202A

CN116661202A - Array substrate and display device

Info

Publication number: CN116661202A
Application number: CN202210651762.2A
Authority: CN
Inventors: 龙春平; 马永达
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2022-02-18
Filing date: 2022-02-18
Publication date: 2023-08-29
Also published as: CN114236930A; CN116917801A; CN114236930B; WO2023155344A1

Abstract

An array substrate and a display device. The array substrate comprises a substrate, and grid lines, a metal layer, pixel electrodes and thin film transistors which are arranged on the substrate. The metal layer includes a data line, a first connection portion, and first and second poles of the thin film transistor, the first pole being electrically connected to the pixel electrode through the first connection portion. The grid line comprises a grid line pad, the grid line pad comprises a protruding part protruding into the pixel area relative to the position on the grid line except the grid line pad, and the metal layer positioned in the pixel area comprises a plurality of sections of wirings extending along at least part of the outline of the pixel area; the multi-section wiring comprises a plurality of sections of first wirings surrounding the protruding parts, the sections of first wirings are connected end to form a step structure, and the orthographic projection area ratio of the first connecting parts in different pixel areas on the substrate is 0.8-1.2. The first wiring surrounding the protruding part of the grid line pad is arranged to be of a step structure, so that consistency of capacitance generated by the metal layers and the pixel electrodes in different pixel areas is improved.

Description

Array substrate and display device

The application relates to a divisional application of a 'array substrate and a display device' of a Chinese patent application No. 202210148521.6 submitted by 2022, 2 and 18 days.

Technical Field

At least one embodiment of the present disclosure relates to an array substrate and a display device.

Background

Currently, liquid crystal display devices including thin film transistors have wide use, and more liquid crystal display devices are being developed toward a wide viewing angle and high image quality to provide users with better use experience.

Disclosure of Invention

The embodiment of the disclosure provides an array substrate and a display device.

At least one embodiment of the present disclosure provides an array substrate, including: a substrate base; a plurality of gate lines on the substrate; the metal layer is positioned on one side, far away from the substrate, of the plurality of gate lines, the metal layer comprises a plurality of data lines, the plurality of data lines extend along a first direction and are arranged along a second direction, the plurality of gate lines extend along the second direction and are arranged along the first direction, the first direction is intersected with the second direction, and the plurality of data lines are intersected with the plurality of gate lines to define a plurality of pixel areas. At least one gate line comprises a gate line pad, the gate line pad comprises a protruding part protruding into the pixel area relative to a position on the gate line except the gate line pad, and the metal layer positioned in the pixel area comprises a plurality of sections of wirings extending along at least part of the outline of the pixel area; the multi-section wire comprises a multi-section first wire surrounding at least part of the edge of the protruding part, each section of first wire extends along the first direction or the second direction, and the multi-section first wires are connected end to form a step structure. The array substrate further comprises a pixel electrode and a thin film transistor, wherein the thin film transistor comprises a first electrode, a grid electrode and a second electrode, the first electrode and the second electrode are overlapped with a film layer where the grid line is located, the first electrode is electrically connected with the pixel electrode through a first connecting part, and the second electrode is electrically connected with the data line; the first pole, the second pole and the first connecting part are all structures in the metal layer; the plurality of pixel areas comprise at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the grid line pad, and the second pixel area is a pixel area corresponding to a position on the grid line except for the grid line pad; the first connection part comprises at least part of the multi-section first wiring, and the area ratio of the orthographic projection of the first connection part in the first pixel area on the substrate to the orthographic projection of the first connection part in the second pixel area on the substrate is 0.8-1.2.

For example, according to an embodiment of the present disclosure, the first connection part overlaps the pixel electrode in a direction perpendicular to the substrate base plate.

For example, according to an embodiment of the present disclosure, the metal layer further includes a common electrode located at the pixel region; the common electrode overlaps the pixel electrode in a direction perpendicular to the substrate base plate, and the first and second electrodes of the thin film transistor are each disposed insulated from the common electrode.

For example, according to an embodiment of the present disclosure, the common electrode comprises at least part of the first trace of the multi-segment first trace.

For example, according to an embodiment of the present disclosure, a ratio of a length of the common electrode in the first pixel region to a length of the common electrode in the second pixel region is 0.8 to 1.2.

For example, according to an embodiment of the present disclosure, a ratio of a length of the first connection portion in the first pixel region to a length of the first connection portion in the second pixel region is 0.8 to 1.2.

For example, according to an embodiment of the present disclosure, the edge of the protruding portion includes a protruding portion edge having an extension direction that is not parallel to both the first direction and the second direction, the number of the plurality of segments of the first trace is 2 or more, and the length of each segment of the first trace is L _i The orthographic projection of each section of first wiring on the substrate is a first orthographic projection, the orthographic projection of the edge of the protruding part on the substrate is a second orthographic projection, the first orthographic projection comprises a long side which extends along the extending direction and is close to the second orthographic projection, and the minimum distance between the long side and the second orthographic projection is d _i The included angle between the long side and the second orthographic projection is theta _i A first parameter C in the capacitance between the first trace and the protrusion edge _pad Satisfy the following requirementsN is the number of the multi-section first wirings, i is a positive integer not less than 1, and N is a positive integer not less than 2.

For example, according to an embodiment of the present disclosure, the first parameter C _pad Satisfy C of 0.035 ∈C _pad ≤5。

For example, according to an embodiment of the present disclosure, the multi-segment wiring in the second pixel region includes a second wiring parallel to the second direction, and an edge of the gate line closest to the second wiring on a side close to the second wiring is an inclined edge not parallel to the second direction; the minimum distance between the orthographic projection of the second wire on the substrate and the orthographic projection of the inclined edge on the substrate is d _h The length of the second trace is L _h An included angle between the orthographic projection of the second wiring on the substrate and the orthographic projection of the inclined edge on the substrate is theta _h A second parameter C of the capacitance between the second trace and the inclined edge _tft Satisfy C _tft ＝ln[(L _h /d _h )×sinθ _h +1]。

For example, according to an embodiment of the present disclosure, the second parameter C _tft Satisfy C of 0.01-0 _tft ≤2.5。

For example, according to an embodiment of the present disclosure, the ratio of the first parameter to the second parameter satisfies 1C _pad /C _tft ≤7。

For example, according to an embodiment of the present disclosure, each of the multi-segment traces extends in the first direction or the second direction.

For example, according to an embodiment of the present disclosure, the gate line pad is configured to be disposed opposite to the support portion in a direction perpendicular to the substrate base plate.

For example, according to an embodiment of the present disclosure, the first connection part extends in the first direction to be electrically connected with the pixel electrode.

For example, according to an embodiment of the present disclosure, the gate line pad includes the gate electrode.

For example, according to an embodiment of the present disclosure, the multi-segment first trace includes two portions, one of which is the common electrode and the other of which is the first connection.

For example, according to an embodiment of the present disclosure, two gate lines located at both sides of at least one first pixel region each include the gate line pad protruding into the first pixel region, the common electrode includes the first trace surrounding a protrusion of the gate line pad on one of the two gate lines, and the first connection portion includes the first trace surrounding a protrusion of the gate line pad on the other of the two gate lines.

For example, according to embodiments of the present disclosure, the gate is located on the gate line at a position other than the gate line pad.

For example, according to an embodiment of the present disclosure, the first connection portion includes a sub-portion extending in the first direction and a sub-portion extending in the second direction.

For example, according to an embodiment of the present disclosure, the array substrate further includes: and the public electrode wire is arranged on the same layer as the plurality of gate wires, and the public electrode is electrically connected with the public electrode wire.

For example, according to an embodiment of the present disclosure, the common electrode line extends in the second direction, and the first connection part overlaps the common electrode line in a direction perpendicular to the substrate base.

For example, according to an embodiment of the present disclosure, an insulating layer is disposed between the pixel electrode and the metal layer, the first connection portion is electrically connected to the pixel electrode through a via hole in the insulating layer, and a straight line parallel to the first direction passes through the via hole and an orthographic projection of the gate line pad on the substrate.

For example, according to embodiments of the present disclosure, the edges of the protrusions include a fold line or curve.

For example, according to an embodiment of the present disclosure, the first connection portion is in an extremely integrated structure with the first electrode of the thin film transistor.

Another embodiment of the present disclosure provides a display device, including an array substrate provided in any one of the above embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

Fig. 1 is a schematic view of a partial planar structure of an array substrate provided according to an example of an embodiment of the present disclosure;

FIG. 2 is a schematic view of a partial planar structure of the array substrate shown in FIG. 1 with pixel electrodes disposed thereon;

FIG. 3 is a cross-sectional view of the metal layer, insulating layer and pixel electrode taken along line AA' of FIG. 2;

FIG. 4 is a schematic diagram of another pixel region on the array substrate shown in FIG. 1;

FIG. 5 is a schematic view of a portion of the protrusion of FIG. 1 and a first trace at an edge of the portion of the protrusion;

FIG. 6 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 7 is a schematic diagram of another pixel region on the array substrate shown in FIG. 6;

FIG. 8A is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 8B is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

fig. 9 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 10 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 11 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 12 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 13 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 14 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

fig. 15 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 16 is a schematic view of a partial planar structure of an array substrate provided according to another example of an implementation of the present disclosure;

FIG. 17 is a schematic view of a partial planar structure of an array substrate according to another embodiment of the disclosure;

fig. 18 is a schematic view of a partial planar structure of an array substrate according to another embodiment of the disclosure.

Reference numerals: 01-a support; 010-a first pixel region; 020-a second pixel region; 10-pixel region; 11-via holes; 12-via holes; 13-an insulating layer; 30-wiring; 31-a first trace; 32-a second trace; 33-wiring sub-sections; 100-a substrate base plate; 200-grid lines; 201-hollowed-out patterns; 210-gate line pad; 211-a protrusion; 2110—a tab edge; 300-a metal layer; 310-data lines; 320-a common electrode; 321-a first sub-common electrode; 322-a second sub-common electrode; 323-third sub-common electrode; 324-fourth sub-common electrode; 330-a first connection; 340-a second connection; 400-pixel electrodes; 500-thin film transistors; 510-a first pole; 520-second pole; 530-gate; 600-common electrode lines.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items.

The embodiment of the disclosure provides an array substrate and a display device. The array substrate includes a substrate, and a plurality of gate lines and metal layers on the substrate. The metal layer is positioned on one side of the plurality of gate lines far away from the substrate base plate, the metal layer comprises a plurality of data lines, the plurality of data lines extend along a first direction and are arranged along a second direction, the plurality of gate lines extend along the second direction and are arranged along the first direction, the first direction and the second direction are intersected, and the plurality of data lines are intersected with the plurality of gate lines to define a plurality of pixel areas. At least one gate line comprises a gate line pad, the gate line pad comprises a protruding part protruding into the pixel area relative to the position on the gate line except the gate line pad, and a metal layer positioned in the pixel area comprises a plurality of sections of wirings extending along at least part of the outline of the pixel area; the multi-section wire comprises a plurality of sections of first wires surrounding at least part of the edge of the protruding part, each section of first wire extends along the first direction or the second direction, and the sections of first wires are connected end to form a step structure. The array substrate further comprises a pixel electrode and a thin film transistor, wherein the thin film transistor comprises a first electrode, a grid electrode and a second electrode, the first electrode and the second electrode are overlapped with a film layer where the grid line is positioned, the first electrode is electrically connected with the pixel electrode through a first connecting part, and the second electrode is electrically connected with the data line; the first pole, the second pole and the first connecting part are all structures in the metal layer; the plurality of pixel areas comprise at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the grid line pad, and the second pixel area is a pixel area corresponding to the position, except the grid line pad, on the grid line; the first connecting part comprises at least part of the multi-section first wiring, and the area ratio of the orthographic projection of the first connecting part in the first pixel area on the substrate to the orthographic projection of the first connecting part in the second pixel area on the substrate is 0.8-1.2. According to the embodiment of the disclosure, the first wiring surrounding the protruding portion of the grid line pad is in the step structure, and the orthographic projection area ratio of the first connecting portion in the first pixel region and the second pixel region on the substrate is 0.8-1.2, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The array substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

Fig. 1 is a schematic view of a partial planar structure of an array substrate according to an example of an embodiment of the present disclosure. As shown in fig. 1, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 1 schematically shows a pixel region 10.

For example, as shown in fig. 1, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, fig. 1 schematically shows that the first direction is the X direction and the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the first direction and the second direction may not be perpendicular, and for example, an included angle between the first direction and the second direction may be 30-60 degrees. For example, the first direction and the second direction may be interchanged.

For example, fig. 1 schematically shows that the planar shape (e.g., the planar shape parallel to the XY plane) of each data line 310 is a linear strip extending along the first direction, but not limited thereto, the planar shape of the data line 310 may be a nonlinear strip extending along the first direction as a whole, for example, a folded line. For example, fig. 1 schematically shows that the planar shape of each data line 310 is a linear strip shape with uniform width throughout, but the planar shape of the data line 310 is not limited thereto, and may be a strip shape with non-uniform width, and the specific shape of the data line may be set according to the product requirement. For example, the overall extension direction of each gate line 200 is the second direction. For example, the planar shape of the gate line 200 may be a long bar shape having an uneven width, but is not limited thereto, and the specific shape of the gate line may be set according to the product requirement.

For example, as shown in fig. 1, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

For example, the shape of the pixel region 10 may be polygonal. For example, the shape of the pixel region 10 may be a quadrangle. For example, the shape of the pixel region 10 may be rectangular. The embodiments of the present disclosure are not limited thereto, and the shape of the pixel region 10 is related to the shape of the edges of the data line 310 and the edges of the gate line 200.

For example, each pixel region 10 includes a display region for display, and the display region may have an area smaller than the pixel region 10. For example, the shape of the display region may be the same as the shape of the pixel region 10, or the shape of the display region may be different from the shape of the pixel region 10.

For example, as shown in fig. 1, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material. Of course, the embodiments of the present disclosure are not limited thereto, and the common electrode may be provided in a different layer from the metal layer.

As shown in fig. 1, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 except for the gate line pad 210.

For example, as shown in fig. 1, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, as shown in fig. 1, the gate line pad 210 may include a protrusion 211 protruding with respect to one side of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding toward the same side of the gate line 200.

For example, the pixel region 10 does not include the protrusion 211.

For example, as shown in fig. 1, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, fig. 1 schematically shows that the support portion 01 has a circular shape in a plane parallel to the XY plane, but is not limited thereto, and may have a regular shape such as a polygon or an irregular shape.

The "direction perpendicular to the substrate 100" is a direction perpendicular to the main board surface of the substrate 100 for providing the structure such as the gate line, for example, a direction perpendicular to the XY plane.

For example, the array substrate may be an array substrate in a liquid crystal display panel, and the liquid crystal display panel further includes a counter substrate, a liquid crystal layer between the array substrate and the counter substrate, and a frame sealing adhesive for sealing the liquid crystal layer. For example, the opposite substrate may be a color film substrate. For example, the supporting part 01 (may also be referred to as a spacer) is located in the liquid crystal layer between the array substrate and the opposite substrate to maintain uniformity of the thickness of the display panel case. For example, the support portion 01 may be a photosensitive spacer, that is, a spacer having high positional accuracy is formed by photolithography of a photosensitive composition, and the support portion 01 includes a resin, a polymerizable compound, a photopolymerization initiator, and the like, and the embodiment of the present disclosure is not limited thereto.

For example, the liquid crystal display panel further includes a first polarizing layer disposed on a side of the array substrate away from the opposite substrate and a second polarizing layer disposed on a side of the opposite substrate away from the array substrate. For example, the non-display side of the display panel may be provided with a backlight configured to provide backlight to the display panel.

For example, the array substrate includes a support part 01 overlapping the gate line pad 210 in a direction perpendicular to the substrate 100. However, the present invention is not limited thereto, and the support portion may be provided on the opposite substrate, and the position of the support portion may be set according to the product demand.

For example, the position of the gate line pad 210 may be set according to the position of the support part 01. For example, the number of the supporting portions 01 is K, the number of the gate line pads 210 is also K, and the supporting portions 01 are arranged in one-to-one correspondence with the gate line pads 210.

As shown in fig. 1, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10" may refer to the multi-segment trace extending along the edge of the data line 310 and the edge of the gate line 200. The multi-segment wiring extending along at least part of the outline of the pixel region may be parallel to the extending direction of the edge of the data line or the gate line, but not limited thereto, and part of the wiring of the multi-segment wiring may be non-parallel to the edge of the gate line or some part of the data line, and whether the wiring is parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to the requirement of the product.

For example, as shown in fig. 1, the edges of the protrusions 211 of the gate line pad 210 include a fold line or a curve.

As shown in fig. 1, the multi-segment wire 30 includes a multi-segment first wire 31 surrounding at least a portion of the edge of the protrusion 211, each segment of the first wire 31 extends along a first direction or a second direction, and the multi-segment first wires 31 are connected end to form a step structure. The above-mentioned "the plurality of segments of the first wire 31 around at least part of the edge of the protrusion 211" may refer to an orthographic projection of the plurality of segments of the first wire 31 on the substrate 100 around at least part of the edge of the protrusion 211 on the substrate 100.

According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

For example, two first wires 31 of the multi-stage first wires 31 are electrically connected. For example, the multi-stage first wiring 31 may be an integrated structure. For example, the distance between the front projection of the multi-segment first trace 31 on the substrate 100 and the front projection of the edge of the surrounding protrusion 211 on the substrate is smaller than the distance between the front projection of the other trace on the substrate 100 and the edge of the protrusion 211. For example, the distances between the different first tracks 31 and the edges of the protrusions 211 around which they surround may be the same or different. For example, the extending direction of the first trace 31 may be parallel to the edge of the protrusion 211 surrounding the first trace; the extending direction of the first trace 31 may also intersect the edge of the protrusion 211 surrounding it.

For example, as shown in fig. 1, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 or the gate lines 200 adjacent thereto. For example, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 adjacent thereto or the edges of the gate lines 200 near the wirings 30.

For example, as shown in fig. 1, two segments of traces 30 located at both ends of the outermost edge of the multi-segment first trace 31 may extend in the second direction. For example, two segments of wires 30 located at both ends of the outermost edge of the multi-segment first wire 31 may be electrically connected to the first wire 31. For example, two sections of wires 30 positioned at both ends of the outermost edge of the multi-section first wire 31 may be configured integrally with the first wire 31. However, the present invention is not limited thereto, and one segment of the wires of the two segments of wires located at the two ends of the outermost edge of the multi-segment first wire may be spaced apart from the first wire.

For example, as shown in fig. 1, any one of the multi-segment traces 30 may extend in a first direction or in a second direction 31.

For example, as shown in fig. 1, the protruding portion 211 may have a trapezoid shape, an upper bottom of which protrudes into the pixel region 10 with respect to other portions of the gate line 200, and a lower bottom of which may be flush with an edge of at least part of the other portions of the gate line 200.

For example, as shown in fig. 1, only one side of the gate line 200 is provided with the protrusion 211, and an edge of the other side of the gate line 200 at a position opposite to the protrusion 211 extends in the Y direction, and at this time, the plurality of first wirings 31 of the plurality of wirings 30 within each pixel region are intensively distributed at one of the plurality of wirings 30 to surround one protrusion 211.

In the array substrate provided by the embodiment of the disclosure, whether the edge of the protruding portion is parallel to the first direction and the second direction or not, by setting the first wiring around the edge of the protruding portion to extend along the first direction or along the second direction, the influence of the multi-segment wiring on the aperture ratio of the pixel region can be minimized.

Fig. 2 is a schematic view of a partial planar structure of the array substrate shown in fig. 1, where pixel electrodes are disposed. For example, as shown in fig. 1 and 2, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. For example, the pixel electrode 400 overlaps the metal layer 300 in a direction perpendicular to the substrate base plate 100. For example, each pixel region 10 includes one pixel electrode 400, and each pixel region 10 may include a pixel electrode 400 that is a monolithic electrode, but is not limited thereto, and each pixel region may include a pixel electrode that is a plurality of stripe structures. For example, the pixel electrode 400 may be a transparent conductive material, and the pixel electrode 400 covers the light emitting region of the pixel region 10.

For example, as shown in fig. 1, the embodiment of the present disclosure schematically illustrates that the pixel electrode 400 is located at a side of the metal layer 300 away from the substrate 100, but is not limited thereto, and the pixel electrode may be located between the metal layer and the substrate, and the positions of the pixel electrode and the metal layer may be set according to product requirements.

For example, as shown in fig. 1 and 2, each pixel region 10 may include one thin film transistor 500, but is not limited thereto, and the number of thin film transistors included in each pixel region may be set according to the performance of a desired pixel circuit, for example, the number of thin film transistors in each pixel region may be two or more.

For example, as shown in fig. 1 and 2, each thin film transistor 500 includes a first pole 510, a gate electrode 530, and a second pole 520, where the first pole 510 and the second pole 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 further includes an active layer, each of the first and second electrodes 510 and 520 overlapping the active layer, and the gate electrode 530 overlapping the active layer.

For example, as shown in fig. 1 and 2, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connection portion 330, and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310.

Fig. 3 is a cross-sectional view of the metal layer, the insulating layer, and the pixel electrode taken along line AA' shown in fig. 2. For example, as shown in fig. 1 to 3, an insulating layer 13 is provided between the pixel electrode 400 and the metal layer 300, and the first connection portion 330 is electrically connected to the pixel electrode 400 through a via hole 12 in the insulating layer 13.

For example, as shown in fig. 1 and 2, the first pole 510 of the thin film transistor 500, the second pole 520 of the thin film transistor 500, and the first connection portion 330 are all structures in the metal layer 300. For example, the first pole 510 of the thin film transistor 500 and the second pole 520 of the thin film transistor 500 are each disposed insulated from the common electrode 320. For example, the first pole 510 of the thin film transistor 500 and the second pole 520 of the thin film transistor 500 are each disposed apart from the common electrode 320. For example, the first connection portion 330 is spaced apart from the common electrode 320.

For example, as shown in fig. 1 and 2, the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be integrated, but the present invention is not limited thereto, and the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be electrically connected in two parts. For example, the first electrode 510 of the thin film transistor 500 may be a portion where the metal layer 300 overlaps the active layer, and the first connection portion 330 may be a portion where the metal layer 300 does not overlap the active layer.

For example, as shown in fig. 1 and 2, the first connection portion 330 and the common electrode 320 each overlap the pixel electrode 400 in a direction perpendicular to the substrate base 100. For example, in a direction perpendicular to the substrate base plate 100, a portion of the first connection portion 330 overlaps the pixel electrode 400. For example, in a direction perpendicular to the substrate base plate 100, a portion of the common electrode 320 overlaps the pixel electrode 400.

For example, as shown in fig. 1, a straight line extending in the first direction passes through an orthographic projection of the first pole 510 of the thin film transistor 500 on the substrate 100 and an orthographic projection of the via 12 on the substrate 100. For example, the first connection portion 330 includes at least a sub-portion extending in the first direction. For example, the first connection part 330 includes only a sub-part extending in the first direction. For example, a sub-portion of the first connection portion 330 extending in the first direction is electrically connected to the pixel electrode 400.

For example, as shown in fig. 1, the metal layer 300 further includes a second connection portion 340 for connecting the data line 310 and the second pole 520 of the thin film transistor 500.

For example, as shown in fig. 1, the second connection part 340 overlaps the gate line 200 in a direction perpendicular to the substrate base 100. For example, the second connection portion 340 may be integrally formed with the second electrode 520 of the thin film transistor 500. For example, the second connection part 340 may be in an integrated structure with the data line 310. For example, the second electrode 520, the second connection portion 340, and the data line 310 of the thin film transistor 500 may be integrally formed. However, the present invention is not limited thereto, and the second connection portion and the second electrode of the thin film transistor may be electrically connected in two parts, or the second connection portion and the data line may be electrically connected in two parts.

For example, the second connection part 340 may extend in the second direction. For example, the second connection part 340 is spaced apart from the common electrode 320. For example, the second connection portion 340 is a portion where the metal layer 300 does not overlap with the active layer of the thin film transistor 500. For example, the second connection part 340 does not overlap the pixel electrode 400 in a direction perpendicular to the substrate base plate 100.

Fig. 4 is a schematic view of another pixel region on the array substrate shown in fig. 1. For example, as shown in fig. 1 to 4, the plurality of pixel regions 10 include at least one first pixel region 010 and at least one second pixel region 020, the first pixel region 010 being the pixel region 10 corresponding to the gate line pad 210, and the second pixel region 020 being the pixel region 10 corresponding to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 1 to 4, the first pixel region 010 and the second pixel region 020 are different pixel regions, i.e., the first pixel region 010 and the second pixel region 020 are regions defined by crossing different data lines 310 and different gate lines 200. For example, the number of the second pixel regions 020 may be greater than the number of the first pixel regions 010, but is not limited thereto, and the number of the second pixel regions 020 may be smaller than the number of the first pixel regions 010, or the number of the second pixel regions 020 may be equal to the number of the first pixel regions 010.

For example, as shown in fig. 4, the second pixel region 020 is opposite to the non-gate pad of the gate line 200, and the extending direction of each segment of the trace 30 located in the second pixel region 020 and extending along at least a part of the outline of the second pixel region 020 may be parallel to the extending direction of the signal line (gate line or data line) adjacent to the segment of the trace 30 near the edge of the second pixel region 020.

For example, as shown in fig. 1 and 4, the width of the gate line 200 corresponding to the second pixel region 020 may be the same as the width of the gate line 200 at both sides of the gate line pad 210 corresponding to the first pixel region 010. However, not limited thereto, for example, the width of the gate line 200 corresponding to the second pixel region 020 may be different from the width of the gate line 200 at both sides of the gate line pad 210 corresponding to the first pixel region 010. For example, the widths of the gate lines 200 corresponding to the second pixel regions 020 are the same at each position, but not limited thereto, and the widths of one portion of the gate lines 200 corresponding to the second pixel regions 020 may be different from the widths of another portion. For example, the width of the gate electrode of the thin film transistor in the gate line 200 corresponding to the second pixel region 020 may be greater than the width of the other positions. For example, the gate electrode of the thin film transistor may be a part of a gate line.

For example, as shown in fig. 1 to 4, the common electrode 320 includes at least part of the multi-segment traces, and the area ratio of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.8 to 1.2. For example, the area ratio of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100.

The pixel electrodes in each pixel region overlap with the common electrode, and the difference between the capacitances generated between the pixel electrodes in different pixel regions and the common electrode can be reduced by designing the orthographic projection area of the common electrode in the first pixel region corresponding to the gate line pad (i.e. the position where the supporting part is arranged) to be 0.8-1.2 as the orthographic projection area of the common electrode in the second pixel region corresponding to the non-gate line pad (i.e. the position where the supporting part is not arranged), so that the consistency of the capacitances of the different pixel regions is improved, and the display effect of the display device adopting the array substrate is further improved.

For example, the overlapping area of the common electrode 320 and the pixel electrode in the first pixel region 010 is a first overlapping area, the overlapping area of the common electrode 320 and the pixel electrode in the second pixel region 020 is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. For example, the ratio of the first overlapping area to the second overlapping area is 0.9 to 1.1. For example, the first overlapping area is substantially equal to the second overlapping area.

The difference between the capacitances generated between the pixel electrodes in different pixel areas can be reduced by designing the first overlapping area of the common electrode and the pixel electrode in the first pixel area corresponding to the gate line pad (i.e. the position where the supporting part is arranged) to be 0.8-1.2, and the consistency of the capacitances of the different pixel areas can be improved, so that the display effect of the display device adopting the array substrate can be improved.

For example, as shown in fig. 1 to 4, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.9 to 1.1. For example, the common electrode 320 in each pixel region 10 may be a metal wiring having a uniform width.

The common electrode includes a first wiring, and in an example of the embodiment of the disclosure, the position of the common electrode in the first pixel region corresponding to the gate line pad is set to be a folded line type, and each section of common electrode in the folded line type metal layer is set to extend along the first direction or the second direction, which is favorable for making the length of the common electrode in the first pixel region equal to the length of the common electrode in the second pixel region as much as possible, so that the difference between the capacitances generated between the pixel electrodes in different pixel regions and the common electrode can be reduced, the consistency of the capacitances of different pixel regions is improved, and further, the display effect of the display device adopting the array substrate is improved.

For example, as shown in fig. 1, the first trace 31 may be a common electrode 320. For example, the length of each segment of the first trace 31 may be less than the length of the segmented traces in the portion of the multi-segment trace 30 other than the first trace 31.

For example, as shown in fig. 4, the common electrode 320 in the second pixel region 020 includes a first sub-common electrode 321 extending in the second direction and a second sub-common electrode 322 extending in the first direction, the first sub-common electrode 321 is disposed at a position away from the first electrode 510 of the thin film transistor 500 corresponding to the pixel region where it is located, both ends of the first sub-common electrode 321 are electrically connected to the two second sub-common electrodes 322, respectively, and the two second sub-common electrodes 322 are adjacent to the two data lines 310, respectively. The "two second sub-common electrodes 322 are respectively adjacent to the two data lines 310" may mean that no other common electrode or other data line is disposed between the front projection of each second sub-common electrode 322 on the substrate 100 and the front projection of the corresponding data line 310 on the substrate 100.

For example, as shown in fig. 1 to 4, a distance between the first wiring 31 in the first pixel region 010 and the first pole 510 of the thin film transistor 500 corresponding to the first pixel region 010 is smaller than a distance between the first sub-common electrode 321 in the second pixel region 020 and the first pole 510 of the thin film transistor 500 corresponding to the second pixel region 020.

For example, as shown in fig. 1-4, the common electrode 320 includes traces 30 that are connected end-to-end.

For example, as shown in fig. 1 to 4, the multi-segment wires 30 are all common electrodes 320, the multi-segment wires 30 are connected end to form a ring shape with an opening, the opening of the ring shape is inserted into the first connection portion 330, and the ring shape is insulated from the first connection portion 330. For example, a space is provided between the first connection portion 330 and the annular opening edge.

For example, as shown in fig. 1-4, each of the multi-segment traces 30 extends in either the first direction or the second direction. Whether the gate line is close to the edge of the pixel region or the data line is close to the edge of the pixel region extends along the first direction and the second direction or not, the influence of the multi-section routing arranged on the metal layer on the aperture ratio of the pixel region can be minimized by arranging each section of routing in the multi-section routing to extend along the first direction or the second direction.

For example, as shown in fig. 1 to 4, the gate line pad 210 includes a gate electrode 530 of the thin film transistor 500. For example, in a direction perpendicular to the substrate base plate 100, the gate electrode 530 of the thin film transistor 500 is disposed overlapping the supporting portion 01. For example, the first pole 510 and the second pole 520 of the thin film transistor 500 may each be disposed to overlap the support 01.

For example, as shown in fig. 1 to 4, a straight line extending in the X direction passes through the orthographic projection of the gate electrode 530 of the thin film transistor 500 on the substrate 100 and the orthographic projection of the via hole 12 on the substrate 100. For example, a straight line parallel to the first direction passes through the orthographic projection of the via 12 and the gate line pad 210 on the substrate 100.

For example, as shown in fig. 1 to 4, the first connection part 330 extends in the first direction to be electrically connected with the pixel electrode 400. For example, the width of the first connection portion 330 opposite to the position of the via hole 12 is greater than the width of the other positions of the first connection portion 330, so as to facilitate the first connection portion 330 to be electrically connected to the pixel electrode 400 through the via hole 12.

For example, as shown in fig. 1 to 4, the array substrate further includes a common electrode line 600, and the common electrode line 600 is disposed in the same layer as the plurality of gate lines 200. For example, the common electrode 320 is electrically connected to the common electrode line 600.

For example, as shown in fig. 1 to 4, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600, and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

For example, as shown in fig. 1 to 4, the common electrode 320 in at least one pixel region 10 may be of an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. But is not limited thereto, the common electrode in at least one pixel region may be further provided in at least two structures separated from each other, each structure being electrically connected to the common electrode line.

For example, as shown in fig. 1 to 4, the common electrode line 600 extends in the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged in the first direction. For example, the common electrode line 600 is disposed to overlap the pixel electrode 400 in a direction perpendicular to the substrate base plate 100.

For example, as shown in fig. 1 to 4, the first connection part 330 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 1 and 2, the via hole 12 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 1 to 4, the common electrode 320 further includes a third sub-common electrode 323 extending in the first direction, and the third sub-common electrode 323 is aligned with at least a part of the first connection portion 330 extending in the first direction to divide one pixel region 10 into two sub-pixel regions. For example, the third sub-common electrode 323 and the first connection part 330 are configured to cooperate to divide one pixel region into two sub-pixel regions. Of course, the embodiment of the present disclosure is not limited thereto, and the third sub common electrode may be not positioned in the same extension direction as the first connection portion.

For example, as shown in fig. 1 to 4, one pixel region 10 includes two sub-pixel regions arranged in the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions may be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 may be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 may be the same or different.

For example, as shown in fig. 1 to 4, at least part of the first connection part 330 and the third sub common electrode 323 are located at both sides of the common electrode line 600, respectively. For example, the first connection part 330 includes a portion overlapping the common electrode line 600 and another portion not overlapping the common electrode line 600, and the portion of the first connection part 330 not overlapping the common electrode line 600 and the third sub-common electrode 323 are respectively located at both sides of the common electrode line 600. Of course, the embodiment of the present disclosure is not limited thereto, and the first connection part may further include two parts located at both sides of the common electrode line, in which case the third sub common electrode may not be provided; alternatively, the portion of the first connection portion on the same side of the common electrode line as the third sub-common electrode is provided with a shorter length to ensure a spacing with the third sub-common electrode. For example, when the first connection portion includes two portions provided on both sides of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection part includes two parts disposed at both sides of the common electrode line, the width of the part of the first connection part on the same side as the third sub common electrode line may have the same width as the third sub common electrode, but is not limited thereto, and the widths thereof may be different.

Fig. 5 is a schematic view of a portion of the protrusion shown in fig. 1 and a first trace located at an edge of the portion of the protrusion. For example, as shown in fig. 1 and 5, the edges of the protrusion 211 of the gate line pad 210 include protrusion edges 2110 extending in a direction non-parallel to both the first direction and the second direction. For example, the protrusion 211 may include a plurality of edges, and the plurality of edges may include edges parallel to the first direction or the second direction in addition to the protrusion edge 2110. The above-mentioned "the projection edge 2110 extending direction is not parallel to both the first direction and the second direction" means that the orthographic projection of the projection edge 2110 on the substrate 100 is not parallel to both the first direction and the second direction.

For example, as shown in fig. 1, the edges of the protrusion 211 may include a protrusion edge 2110 that is non-parallel to both the first direction and the second direction and an edge that is parallel to the second direction. But is not limited thereto, the edge of the protrusion 211 may further include an edge parallel to the first direction. For example, the protrusion 211 may include one, two, or more protrusion edges 2110. The number of the protruding part edges which are not parallel to the first direction and the second direction and are included in each protruding part is not limited, and the protruding part edges can be set according to product requirements. The "edge parallel to the second direction" mentioned above means that the orthographic projection of the edge of the protrusion 211 on the substrate 100 is parallel to the second direction; the above-mentioned "edge parallel to the first direction" means that the orthographic projection of the edge of the protrusion 211 on the substrate 100 is parallel to the first direction.

For example, where the protrusion 211 includes a plurality of protrusion edges 2110, the lengths of the plurality of protrusion edges 2110 may be the same or different; for example, the angle between the plurality of tab edges 2110 and the second direction may be the same or may be different. The number of the plurality of protruding part edges and the inclination angle with respect to the second direction may be set according to the product demand. The length of the protruding part edge may refer to the length of the orthographic projection of the protruding part edge on the substrate.

For example, as shown in fig. 1 and 5, the number of the plurality of the first wirings 31 is 2 or more. For example, the number of first wirings 31 corresponding to one protrusion edge 2110 of the protrusion 211 is not less than 2. For example, the plurality of segments of the first trace 31 corresponding to one of the protrusion edges 2110 may be connected to each other to form a stepped structure. For example, the number of first traces 31 corresponding to different protrusion edges 211 in the same protrusion 211 may be the same or different, which is not limited by the embodiment of the present disclosure. For example, the lengths of different segments of the first trace 31 corresponding to the same tab edge 2110 may be different. For example, the width of the orthographic projection of different segments of first trace 31 on substrate 100 corresponding to the same tab edge 2110 may be the same. For example, the thickness of different segments of the first trace 31 corresponding to the same tab edge 2110 may be the same in a direction perpendicular to the substrate 100.

For example, as shown in fig. 1 and 5, an edge parallel to the second direction may be included in an edge of the protruding portion 211, and a first trace 31 opposite to the edge parallel to the second direction in the protruding portion 211 in the multi-segment first trace 31 is parallel to the edge in the protruding portion 211, that is, an orthographic projection of the first trace 31 on the substrate 100 is parallel to an orthographic projection of the edge of the protruding portion 211 on the substrate 100.

For example, as shown in fig. 1 and 5, when an edge parallel to the first direction or the second direction and an edge non-parallel to both the first direction and the second direction are included in the edge of the protrusion 211, a first trace 31 parallel to a part of the edge of the protrusion 211 and a first trace 31 non-parallel to another part of the edge of the protrusion 211 may be included in the multi-stage first trace 31 around the edge of the protrusion 211.

For example, as shown in fig. 1 and 5, the front projection of each segment of the first trace 31 on the substrate 100 is a first front projection, the front projection of the protrusion edge 2110 on the substrate 100 is a second front projection, and the first front projection includes a long side LL extending along the extending direction thereof and being close to the second front projection, and a distance d is provided between the long side LL and the second front projection. For example, the distance between the second orthographic projection of the protrusion edge 2110 on the substrate 100 and the long side LL of the first orthographic projection of the first trace 31 on the substrate 100 may include a maximum distance dmax and a minimum distance dmin, in a non-parallel relationship with the first trace 31 opposite thereto. A plurality of connecting lines perpendicular to the second orthographic projection exist between the long sides LL of the second orthographic projection and the first orthographic projection, the length of the longest one of the connecting lines may be dmax, and the length of the shortest one of the connecting lines may be dmin.

For example, as shown in fig. 1 and 5, one protrusion edge 2110 of the protrusion 211, which is not parallel to both the first direction and the second direction, and a first trace 31 extending in the second direction opposite thereto are described as an example. The protrusion edge 2110 is angled at θ to the second direction. For example, an angle θ between a second orthographic projection of the protrusion edge 2110 on the substrate 100 and a long side LL of the first orthographic projection of the segment of the first trace 31 on the substrate 100; the length of the first wire 31 is l, and the line width of the first wire 31 is W; the distance between the second orthographic projection of the tab edge 2110 on the substrate 100 and the long side LL of the first orthographic projection of the first trace 31 on the substrate 100 comprises a minimum distance dmin; the fringe field capacitance between the first trace 31 and the protrusion edge 2110 satisfies the following relationship (1):

wherein ε _d Is the relative dielectric constant.

For example, the length of the first trace 31 is a length along the Y direction, and the line width of the first trace 31 may refer to a dimension along the X direction.

The fringe field capacitance integration can be given by the relation (2):

C＝ε _d ×W×ln[(l/dmin)×sinθ+1]。

for example, the length of the first trace 31 parallel to the second direction in the first trace 31 opposite to the protrusion edge 2110 shown in fig. 5 may be a first length Lh, the minimum distance between the segment of the first trace 31 and the protrusion edge 2110 may be a first minimum distance dminh, and then the capacitance between the segment of the first trace 31 and the protrusion edge 2110 may be Ch; the length of the first trace 31 parallel to the first direction in the first trace 31 opposite the protrusion edge 2110 shown in fig. 5 may be a second length Lv, the minimum distance between the segment of the first trace 31 and the protrusion edge 2110 may be a second minimum distance dminv, and then the capacitance between the segment of the first trace 31 and the protrusion edge 2110 may be Cv.

For example, the first length Lh may be 12.21 micrometers, the second length Lv may be 6.29 micrometers, the first minimum distance dminh may be 8.34 micrometers, the second minimum distance dminv may be 9.16 micrometers, the angle θ between the protrusion edge 2110 and the long side LL of the orthographic projection of the two first traces 31 may be 45 degrees, and the line width W of each first trace 31 may be 3.5 micrometers.

For example, assume ε _d 1, substituting the values of the first length Lh, the first minimum distance dminh, the line width W and the included angle theta into a relation ln [ (l/dmin) ×sin θ+1]The value of the capacitance Ch is 0.710606, and the value of the first length Lh, the first minimum distance dminh, the line width W and the included angle theta are substituted into the relation (2) to obtain the capacitance Ch of 2.487122F; substituting the values of the second length Lv, the second minimum distance dminv, the line width W and the included angle θ into a relation ln [ (l/dmin) ×sin θ+1]The value of the capacitance is 0.39579, and the values of the second length Lv, the second minimum distance dminv, the line width W, and the angle θ are substituted into the relation (2) to obtain the capacitance Cv of 1.385264F, where ch+cv= 3.872386.

Epsilon as described above _d For 1 is only a schematic illustration, epsilon in the actual product _d The value of (c) is related to the material of the insulating layer between the gate line layer and the metal layer, for example, the material of the insulating layer between the gate line layer and the metal layer may include an organic material or an inorganic material, for example, may be silicon oxide or silicon nitride, or the like.

For example, the values of the first length Lh, the second length Lv, the first minimum distance dminh, and the second minimum distance dminv may be set according to the size of the display device to which the array substrate is applied. For example, the size of one sub-pixel on the array substrate may be 25-95 μm, and the firstThe minimum value of the length Lh may be 2 micrometers, the minimum value of the second length Lv may be 2 micrometers, the minimum value of the first minimum distance dminh may be 2 micrometers, and the minimum value of the second minimum distance dminv may be 2 micrometers, the first length Lh, the second length Lv, the first minimum distance dminh, and the minimum value of the second minimum distance dminv are substituted into the relation ln [ (l/dmin) ×sin θ+1]Can obtain the first parameter C _pad Is 0.483114. Similarly, the maximum value of the first length Lh may be 30 micrometers, the maximum value of the second length Lv may be 30 micrometers, the maximum value of the first minimum distance dminh may be 20 micrometers, and the maximum value of the second minimum distance dminv may be 20 micrometers, and the maximum values of the first length Lh, the second length Lv, the first minimum distance dminh, and the second minimum distance dminv are substituted into the relation ln [ (l/dmin) ×sin θ+1 ]Can obtain the first parameter C _pad Is 4.903148.

For example, according to the above calculation process, the length of each first trace 31 is L _i The front projection of each section of the first wire 31 on the substrate 100 is a first front projection, the front projection of the protrusion edge 2110 on the substrate 100 is a second front projection, the first front projection comprises a long side LL extending along the extending direction and being close to the second front projection, and the minimum distance between the long side LL and the second front projection is d _i The included angle between the long side LL and the second orthographic projection is theta _i First parameter C in the capacitance between first trace 31 and protrusion edge 2110 _pad Satisfy the following requirementsN is the number of the multi-segment first wirings 31, i is a positive integer not less than 1, and N is a positive integer not less than 2. The first parameter C _pad And is the relative dielectric constant epsilon _d And the product of the line width W is the capacitance.

For example, the first parameter C _pad Satisfy C of 0.035 ∈C _pad And is less than or equal to 5. For example, the first parameter C _pad Satisfy C of 0.1-0 _pad And is less than or equal to 4.5. For example, the first parameter C _pad Satisfy the following requirements0.5≤C _pad And is less than or equal to 4. For example, the first parameter C _pad Satisfy C of 1 to less than or equal to _pad Less than or equal to 3.5. For example, the first parameter C _pad Satisfy C of 1.5 ∈ _pad And is less than or equal to 3. For example, the first parameter C _pad Satisfy C of 2-2 _pad ≤2.5。

For example, a plurality of pixel regions 10 are disposed on the array substrate, and the plurality of pixel regions 10 may be arrayed along the first direction and the second direction. For example, among the pixel regions 10 arranged in the first direction, three second pixel regions 020 are provided between two adjacent first pixel regions 010; and/or, in the pixel regions 10 arranged in the second direction, three second pixel regions 020 are provided between two adjacent first pixel regions 010. Of course, the embodiments of the present disclosure are not limited thereto, and four second pixel regions or more may be disposed between two adjacent first pixel regions.

For example, the gate line pad may serve as a gate electrode in a thin film transistor.

The embodiment of the disclosure provides an electrode line design, which is suitable for an array substrate of a liquid crystal display device, can keep consistency of storage capacitance of adjacent pixels or capacitance (Cpd) generated between a common electrode and a pixel electrode, simultaneously minimize influence of the electrode line on an aperture ratio, and finally can reduce parasitic capacitance of a grid line or a grid electrode.

For example, the first wirings are not parallel to the edge profile of the protruding portion at the edge of the protruding portion, the first wirings are in a step shape, each section of the first wirings is respectively parallel to the gate line and the data line, and the capacitance Cgd between the gate line and the drain electrode of the thin film transistor and the capacitance Cgc between the gate line and the common electrode are further reduced.

Fig. 6 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 6, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 6 schematically shows a pixel region 10.

For example, as shown in fig. 6, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. But is not limited thereto, the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchanged.

For example, as shown in fig. 6, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 6, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 6, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 except for the gate line pad 210.

For example, as shown in fig. 6, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, the example shown in fig. 6 is different from the example shown in fig. 1 in that the gate line pad 210 includes protrusions 211 protruding with respect to both sides of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding to both sides of the gate line 200.

For example, as shown in fig. 6, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, the supporting portion 01 in this example may have the same features as the supporting portion 01 in the example shown in fig. 1, and will not be described here. For example, fig. 6 schematically illustrates that the supporting part 01 is provided on the array substrate, but is not limited thereto, and the supporting part may be provided on the opposite substrate, and the position of the supporting part may be set according to the product demand.

As shown in fig. 6, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10" may refer to the multi-segment trace extending along the edge of the data line 310 and the edge of the gate line 200. The multi-segment wiring extending along at least part of the outline of the pixel region may be parallel to the extending direction of the edge of the data line or the gate line, but not limited thereto, and part of the wiring of the multi-segment wiring may be non-parallel to the edge of the gate line or some part of the data line, and whether the wiring is parallel to the edge of the signal line (including the gate line and the data line) adjacent thereto (in a plan view) may be set according to the requirement of the product.

For example, as shown in fig. 6, the edges of the protrusions 211 of the gate line pad 210 include a fold line or a curve.

As shown in fig. 6, the multi-segment wire 30 includes a multi-segment first wire 31 surrounding at least a portion of the edge of the protrusion 211, each segment of the first wire 31 extends along a first direction or a second direction, and the multi-segment first wires 31 are connected end to form a step structure. The above-mentioned "the plurality of segments of the first wire 31 around at least part of the edge of the protrusion 211" may refer to an orthographic projection of the plurality of segments of the first wire 31 on the substrate 100 around at least part of the edge of the protrusion 211 on the substrate 100.

For example, as shown in fig. 6, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 or the gate lines 200 adjacent thereto. For example, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 adjacent thereto or the edges of the gate lines 200 near the wirings 30.

For example, as shown in fig. 6, two segments of the traces 30 located at both ends of the outermost edge of the multi-segment first trace 31 may extend in the second direction. For example, two segments of wires 30 located at both ends of the outermost edge of the multi-segment first wire 31 may be electrically connected to the first wire 31. For example, two sections of wires 30 positioned at both ends of the outermost edge of the multi-section first wire 31 may be configured integrally with the first wire 31. However, the present invention is not limited thereto, and one segment of the wires of the two segments of wires located at the two ends of the outermost edge of the multi-segment first wire may be spaced apart from the first wire.

For example, as shown in fig. 6, any one of the tracks 31 of the multi-segment tracks 30 may extend in a first direction or in a second direction.

For example, as shown in fig. 6, the shape of the protruding portions 211 located at both sides of the center line of one gate line 200 extending in the Y direction may be the same or different. For example, the two protrusions 211 protruding from other positions of the gate line 200 included in the same gate line pad 210 may have the same shape or may be different. For example, the two protruding portions 211 included in the same gate line pad 210 may each have a trapezoid shape, an upper bottom of which protrudes into the pixel region 10 with respect to other portions of the gate line 200, and a lower bottom of which may be flush with an edge of at least part of the other portions of the gate line 200.

For example, as shown in fig. 6, protruding portions 211 are provided on both sides of the gate line 200 in the X direction, and at this time, in one pixel region 10, the plurality of first wirings 31 in the plurality of wirings 30 are intensively distributed at two positions in the plurality of wirings 30.

For example, the array substrate further includes a plurality of pixel electrodes 400 and a plurality of thin film transistors 500. The pixel electrodes included in the array substrate in this example may have the same features as the pixel electrodes shown in fig. 2, and will not be described herein.

For example, as shown in fig. 6, each pixel region 10 may include one thin film transistor 500, but is not limited thereto, and the number of thin film transistors included in each pixel region may be set according to the performance of a desired pixel circuit, for example, the number of thin film transistors in each pixel region may be two or more.

For example, as shown in fig. 6, each thin film transistor 500 includes a first pole 510, a gate electrode 530, and a second pole 520, where the first pole 510 and the second pole 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 further includes an active layer, each of the first and second electrodes 510 and 520 overlapping the active layer, and the gate electrode 530 overlapping the active layer. For example, the gate electrode 530 may be a partial structure of the gate line 200.

For example, as shown in fig. 6, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connection portion 330, and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310.

For example, as shown in fig. 6, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connection portion 330 are all configured in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are all disposed insulated from the common electrode 320. For example, the first pole 510 of the thin film transistor 500 and the second pole 520 of the thin film transistor 500 are each disposed apart from the common electrode 320. For example, the first connection portion 330 is spaced apart from the common electrode 320.

For example, as shown in fig. 6, the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be integrated, but the present invention is not limited thereto, and may be a two-part electrically connected structure. For example, the first electrode 510 of the thin film transistor 500 may be a portion where the metal layer 300 overlaps the active layer, and the first connection portion 330 may be a portion where the metal layer 300 does not overlap the active layer.

For example, in a direction perpendicular to the substrate base plate 100, the first connection part 330 and the common electrode 320 each overlap the pixel electrode 400. For example, in a direction perpendicular to the substrate base plate 100, a portion of the first connection portion 330 overlaps the pixel electrode 400. For example, in a direction perpendicular to the substrate base plate 100, a portion of the common electrode 320 overlaps the pixel electrode 400.

For example, as shown in fig. 6, the second connection part 340 overlaps the gate line 200 in a direction perpendicular to the substrate 100. For example, the second connection portion 340 may be integrally formed with the second electrode 520 of the thin film transistor 500. For example, the second connection part 340 may be in an integrated structure with the data line 310. For example, the second electrode 520, the second connection portion 340, and the data line 310 of the thin film transistor 500 may be integrally formed. For example, the second connection part 340 may extend in the second direction. For example, the second connection part 340 is spaced apart from the common electrode 320.

For example, the array substrate shown in fig. 6 is different from the array substrate shown in fig. 1 in that: the gate electrode 530 of the thin film transistor 500 on the array substrate shown in fig. 6 is located on the gate line 200 except for the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 may be located at one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the substrate base plate 100, the gate electrode 530 of the thin film transistor 500 does not overlap the supporting portion 01, which is advantageous for increasing the flatness of the supporting portion. For example, in a direction perpendicular to the substrate base plate 100, the first pole 510 and the second pole 520 of the thin film transistor 500 may each have no overlap with the support 01.

Fig. 7 is a schematic view of another pixel region on the array substrate shown in fig. 6. For example, as shown in fig. 6 and 7, the plurality of pixel regions 10 includes at least one first pixel region 010 and at least one second pixel region 020, the first pixel region 010 being the pixel region 10 corresponding to the gate line pad 210, and the second pixel region 020 being the pixel region 10 corresponding to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 6 and 7, the first pixel region 010 and the second pixel region 020 are different pixel regions, i.e., the first pixel region 010 and the second pixel region 020 are regions defined by crossing different data lines 310 and different gate lines 200. For example, the number of the second pixel regions 020 may be greater than the number of the first pixel regions 010, but is not limited thereto, and the number of the second pixel regions 020 may be smaller than the number of the first pixel regions 010, or the number of the second pixel regions 020 may be equal to the number of the first pixel regions 010.

For example, as shown in fig. 7, the extending direction of the portion of the trace 30 located in the second pixel region 020 and extending along at least a part of the outline of the second pixel region 020 may be parallel to the extending direction of the signal line (gate line or data line) adjacent to the portion of the trace 30 near the edge of the second pixel region 020, opposite to the location of the non-gate line pad.

For example, fig. 7 schematically illustrates that the width of the gate line 200 corresponding to the second pixel region 020 at the position where the gate electrode 530 of the thin film transistor 500 is disposed may be greater than the width of the gate electrode 530 at the position where the gate electrode 530 is not disposed, but the width of the gate line corresponding to the second pixel region may be the same at each position.

For example, as shown in fig. 6 and 7, the common electrode 320 includes a part of the wirings of the multi-stage wirings, and the area ratio of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.8 to 1.2. For example, the area ratio of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 to the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the common electrode 320 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the common electrode 320 in the second pixel region 020 on the substrate 100.

For example, the overlapping area of the common electrode 320 and the pixel electrode in the first pixel region 010 is a first overlapping area, the overlapping area of the common electrode 320 and the pixel electrode in the second pixel region 020 is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. For example, the ratio of the first overlapping area to the second overlapping area is 0.9 to 1.1. For example, the first overlapping area is substantially equal to the second overlapping area. The difference between the capacitances generated between the pixel electrodes in different pixel areas can be reduced by designing the first overlapping area of the common electrode and the pixel electrode in the first pixel area corresponding to the gate line pad (i.e. the position where the supporting part is arranged) to be 0.8-1.2, and the consistency of the capacitances of the different pixel areas can be improved, so that the display effect of the display device adopting the array substrate can be improved.

For example, as shown in fig. 6 and 7, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the common electrode 320 in the first pixel region 010 to the length of the common electrode 320 in the second pixel region 020 is 0.9 to 1.1. For example, the common electrode 320 in each pixel region 10 may be a metal wiring having a uniform width.

The common electrode in the first pixel region is arranged to be a folded line shape corresponding to the position of the grid line pad, and each section of common electrode in the folded line is arranged to extend along the first direction or the second direction, so that the length of the common electrode in the first pixel region is equal to that of the common electrode in the second pixel region as much as possible, the difference between the capacitances generated between the pixel electrodes in different pixel regions and the common electrode can be reduced, the consistency of the capacitances of different pixel regions is improved, and the display effect of a display device adopting the array substrate is further improved.

For example, as shown in fig. 6, the first connection portion 330 includes a portion of the traces 30 of the multi-segment traces 30, and the area ratio of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 to the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100 is 0.8-1.2. For example, the area ratio of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 to the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100 is 0.9 to 1.1. For example, the area of the orthographic projection of the first connection portion 330 in the first pixel region 010 on the substrate 100 is substantially equal to the area of the orthographic projection of the first connection portion 330 in the second pixel region 020 on the substrate 100.

The pixel electrodes in each pixel region overlap the first connection portions, and the difference between the capacitances generated between the pixel electrodes in different pixel regions and the first connection portions can be reduced by designing the orthographic projection area of the first connection portions in the first pixel region corresponding to the gate line pad (i.e., the position where the supporting portion is arranged) to be 0.8-1.2 as the orthographic projection area of the first connection portions in the second pixel region corresponding to the non-gate line pad (i.e., the position where the supporting portion is not arranged), so that the consistency of the capacitances of the different pixel regions is improved, and the display effect of the display device adopting the array substrate is further improved.

For example, the first connection portion 330 includes a portion of the wires 30 of the multi-segment wires 30, and the ratio of the overlapping area of the first connection portion 330 and the pixel electrode in the first pixel region 010 to the overlapping area of the first connection portion 330 and the pixel electrode in the second pixel region 020 is 0.8-1.2. For example, the overlapping area ratio of the first connection part 330 and the pixel electrode in the first pixel region 010 to the overlapping area ratio of the first connection part 330 and the pixel electrode in the second pixel region 020 is 0.9 to 1.1. For example, the overlapping area of the first connection part 330 and the pixel electrode in the first pixel region 010 is substantially equal to the overlapping area of the first connection part 330 and the pixel electrode in the second pixel region 020. By designing the overlapping area of the first connection part and the pixel electrode in the first pixel region corresponding to the grid line pad (i.e. the position where the supporting part is arranged) to be 0.8-1.2, the difference between the capacitance generated between the pixel electrode and the first connection part in different pixel regions can be reduced, the consistency of the capacitance in different pixel regions can be improved, and the display effect of the display device adopting the array substrate can be further improved.

For example, the ratio of the length of the first connection portion 330 in the first pixel region 010 to the length of the first connection portion 330 in the second pixel region 020 is 0.8 to 1.2. For example, the ratio of the length of the first connection portion in the first pixel region 010 to the length of the first connection portion in the second pixel region 020 is 0.9 to 1.1. For example, the length of the first connection portion in the first pixel region 010 is substantially equal to the length of the first connection portion in the second pixel region 020.

For example, as shown in fig. 6, the first connection portion 330 is electrically connected to the pixel electrode through the via hole 12 in the insulating layer between the first connection portion 330 and the pixel electrode, and the orthographic projection of the first electrode 510 of the thin film transistor 500 on the substrate 100 and the orthographic projection of the via hole 12 on the substrate 100 cannot be passed by a straight line in the X direction, whereby the first connection portion cannot be extended to the via hole only by extending in the first direction, and the first connection portion is provided in a line shape inclined with respect to the X direction or in a fold line shape in which each segment extends in the first direction or the second direction to be extended to the via hole, and is further electrically connected to the pixel electrode.

The first connecting parts in the first pixel areas are arranged to be folded lines corresponding to the positions of the grid line pads, and each section of first connecting part in the folded lines is arranged to extend along the first direction or the second direction, so that the length of the first connecting parts in the first pixel areas is equal to that of the first connecting parts in the second pixel areas as much as possible, the difference between the capacitance generated between the pixel electrodes in different pixel areas and the first connecting parts can be reduced, the consistency of the capacitance in different pixel areas is improved, and the display effect of the display device adopting the array substrate is further improved.

For example, as shown in fig. 6, at least one of the common electrode 320 and the first connection portion includes a plurality of segments of first wirings. For example, the array substrate shown in fig. 6 is different from the array substrate shown in fig. 1 in that: the multi-segment first trace 31 includes two portions, one of which is the common electrode 320, and the other of which is the first connection 330.

For example, as shown in fig. 6, two gate lines 200 located at both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, a common electrode 320 includes a first wire 31 surrounding a protrusion 211 of the gate line pad 210 on one of the two gate lines 200, and a first connection 330 includes a first wire 31 surrounding a protrusion 211 of the gate line pad 210 on the other of the two gate lines 200.

For example, as shown in fig. 6, the gate line pad 210 includes two protruding portions 211 protruding toward both sides of the gate line 200 in the X direction, that is, includes a first protruding portion and a second protruding portion, the first wirings 31 surrounding the first protruding portion 211 may each be a common electrode 320, and one portion of the first wirings 31 surrounding the second protruding portion is the common electrode 320, and the other portion is the first connection portion 330. For example, all the first wires 31 around the first protrusion 211 are wires 30 arranged continuously and end to end, and the first wires 31 around the second protrusion 212 include two parts of the first wires 31 arranged separately, and each part of the first wires 31 is arranged continuously and end to end.

For example, as shown in fig. 6, the first connection part 330 includes a sub-part extending in the first direction and a sub-part extending in the second direction. For example, the first connection part 330 may include at least one sub-part extending in the first direction and at least one sub-part extending in the second direction. For example, fig. 6 schematically illustrates that the first connection portion 330 includes three sub-portions extending in the first direction and two sub-portions extending in the second direction, but is not limited thereto, and the number of sub-portions extending in the first direction and the number of sub-portions extending in the second direction in the first connection portion may be set according to product requirements.

For example, as shown in fig. 6, a part of the sub-portion of the first connection portion 330 is the first trace 31 surrounding the gate pad 210.

For example, as shown in fig. 7, the common electrode 320 in the second pixel region 020 includes a first sub-common electrode 321 extending in the second direction and a second sub-common electrode 322 extending in the first direction, the first sub-common electrode 321 is disposed at a position away from the first electrode 510 of the thin film transistor 500 corresponding to the pixel region where it is located, both ends of the first sub-common electrode 321 are electrically connected to the two second sub-common electrodes 322, respectively, and the two second sub-common electrodes 322 are adjacent to the two data lines 310, respectively. The "two second sub-common electrodes 322 are respectively adjacent to the two data lines 310" may mean that no other common electrode or other data line is disposed between the front projection of each second sub-common electrode 322 on the substrate 100 and the front projection of the corresponding data line 310 on the substrate 100.

For example, as shown in fig. 6 and 7, a distance between the first wiring 31 in the first pixel region 010 and the first pole 510 of the thin film transistor 500 corresponding to the first pixel region 010 is smaller than a distance between the first sub-common electrode 321 in the second pixel region 020 and the first pole 510 of the thin film transistor 500 corresponding to the second pixel region 020.

For example, as shown in fig. 6 and 7, the common electrode 320 includes the traces 31 connected end to end, and the first connection portion 330 includes the traces 30 connected end to end.

For example, as shown in fig. 6 and 7, the common electrode 320 includes the traces 30 that are connected end to form a ring shape with an opening, where the first connection portion 330 is inserted, and the ring shape is insulated from the first connection portion 330. For example, a space is provided between the first connection portion 330 and the annular opening edge.

For example, as shown in fig. 6 and 7, each of the plurality of traces 30 extends in the first direction or the second direction. Whether the gate line is close to the edge of the pixel region or the data line is close to the edge of the pixel region extends along the first direction and the second direction or not, the influence of the multi-section routing arranged on the metal layer on the aperture ratio of the pixel region can be minimized by arranging each section of routing in the multi-section routing to extend along the first direction or the second direction.

For example, as shown in fig. 6 and 7, the width of the first connection portion 330 opposite to the position of the via hole 12 is greater than the width of the other positions of the first connection portion 330, so that the first connection portion 330 is electrically connected to the pixel electrode 400 through the via hole 12.

For example, as shown in fig. 6 and 7, the array substrate further includes a common electrode line 600, the common electrode line 600 being disposed in the same layer as the plurality of gate lines 200, and the common electrode 320 being electrically connected to the common electrode line 600.

For example, as shown in fig. 6 and 7, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600, and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

For example, as shown in fig. 6 and 7, the common electrode 320 in at least one pixel region 10 may be of an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. But is not limited thereto, the common electrode in at least one pixel region may be further provided in at least two structures separated from each other, each structure being electrically connected to the common electrode line.

For example, as shown in fig. 6 and 7, the common electrode line 600 extends in the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged in the first direction. For example, the common electrode line 600 is disposed to overlap the pixel electrode 400 in a direction perpendicular to the substrate base plate 100.

For example, as shown in fig. 6 and 7, the first connection part 330 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 6 and 7, the via hole 12 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 6 and 7, the common electrode 320 further includes a third sub-common electrode 323 extending in the first direction, and the third sub-common electrode 323 is aligned with at least a part of the first connection portion 330 extending in the first direction to divide the pixel region 10 into two sub-pixel regions. For example, the third sub-common electrode 323 and the first connection part 330 are configured to cooperate to divide one pixel region into two sub-pixel regions. Of course, the embodiment of the present disclosure is not limited thereto, and the third sub common electrode may be not positioned in the same extension direction as the first connection portion.

For example, as shown in fig. 6 and 7, one pixel region 10 includes two sub-pixel regions arranged in the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions may be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 may be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 may be the same or different.

For example, as shown in fig. 6 and 7, at least part of the first connection part 330 and the third sub common electrode 323 are located at both sides of the common electrode line 600, respectively. For example, the first connection part 330 includes a portion overlapping the common electrode line 600 and another portion not overlapping the common electrode line 600, and the portion of the first connection part 330 not overlapping the common electrode line 600 and the third sub-common electrode 323 are respectively located at both sides of the common electrode line 600. Of course, the embodiment of the present disclosure is not limited thereto, and the first connection part may further include two parts located at both sides of the common electrode line, in which case the third sub common electrode may not be provided; alternatively, the portion of the first connection portion on the same side of the common electrode line as the third sub-common electrode is provided with a shorter length to ensure a spacing with the third sub-common electrode. For example, when the first connection portion includes two portions provided on both sides of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection part includes two parts disposed at both sides of the common electrode line, the width of the part of the first connection part on the same side as the third sub common electrode line may have the same width as the third sub common electrode, but is not limited thereto, and the widths thereof may be different.

For example, as shown in fig. 6, the edges of the protrusion 211 of the gate line pad 210 include protrusion edges 2110 extending in a direction non-parallel to both the first direction and the second direction. For example, the protrusion 211 may include a plurality of edges, and the plurality of edges may include edges parallel to the first direction or the second direction in addition to the protrusion edge 2110. The above-mentioned "the projection edge 2110 extending direction is not parallel to both the first direction and the second direction" means that the orthographic projection of the projection edge 2110 on the substrate 100 is not parallel to both the first direction and the second direction.

For example, as shown in fig. 6, the plurality of edges of the protrusion 211 may include a protrusion edge 2110 that is non-parallel to both the first direction and the second direction and an edge that is parallel to the second direction. But is not limited thereto, the edge of the protrusion 211 may further include an edge parallel to the first direction. For example, the protrusion 211 may include one, two, or more protrusion edges 2110. The number of the protruding part edges which are not parallel to the first direction and the second direction and are included in each protruding part is not limited, and the protruding part edges can be set according to product requirements. The "edge parallel to the second direction" mentioned above means that the orthographic projection of the edge of the protrusion 211 on the substrate 100 is parallel to the second direction; the above-mentioned "edge parallel to the first direction" means that the orthographic projection of the edge of the protrusion 211 on the substrate 100 is parallel to the first direction.

For example, where the protrusion 211 includes a plurality of protrusion edges 2110, the lengths of the plurality of protrusion edges 2110 may be the same or different; for example, the angle between the plurality of tab edges 2110 and the second direction may be the same, and may be different, and the number of the plurality of tab edges and the inclination angle with respect to the second direction may be set according to the product requirement. The length of the protruding part edge may refer to the length of the orthographic projection of the protruding part edge on the substrate.

For example, as shown in fig. 6, the number of the plurality of first traces 31 is 2 or more. For example, the number of first wirings 31 corresponding to one protrusion edge 2110 of the protrusion 211 is not less than 2. For example, the plurality of segments of the first trace 31 corresponding to one of the protrusion edges 2110 may be connected to each other to form a stepped structure.

For example, the number of first traces 31 corresponding to different protrusion edges 2110 in the same protrusion 211 may be the same or different, which is not limited by the embodiments of the present disclosure. For example, the lengths of different segments of the first trace 31 corresponding to the same tab edge 2110 may be different. For example, the width of the orthographic projection of different segments of first trace 31 on substrate 100 corresponding to the same tab edge 2110 may be the same. For example, the dimensions of different segments of the first trace 31 corresponding to the same tab edge 2110 may be the same in a direction perpendicular to the substrate 100.

For example, as shown in fig. 6, an edge parallel to the second direction may be included in the edge of the protrusion 211, and a first trace 31 opposite to the edge parallel to the second direction in the protrusion 211 in the plurality of segments of first traces 31 may be parallel to the edge in the protrusion 211, that is, an orthographic projection of the first trace 31 on the substrate 100 may be parallel to an orthographic projection of the edge of the protrusion 211 on the substrate 100.

For example, as shown in fig. 6, when an edge parallel to the first direction or the second direction and an edge non-parallel to both the first direction and the second direction are included in the edge of the protrusion 211, a first trace 31 parallel to a part of the edge of the protrusion 211 and a first trace 31 non-parallel to a part of the edge of the protrusion 211 may be included in the multi-stage first trace 31 around the edge of the protrusion 211.

The capacitance formed between the first trace included in the common electrode and the protruding portion edge of the protruding portion in this example may have the same calculation manner as the capacitance formed between the first trace and the protruding portion edge in the example shown in fig. 1 and 5, and the capacitance formed between the first trace included in the first connection portion and the protruding portion edge of the protruding portion in this example may also have the same calculation manner as the capacitance formed between the first trace and the protruding portion edge in the example shown in fig. 1 and 5, which is not described here again.

For example, as in the example shown in FIG. 6, a first parameter C in the capacitance between the first trace and the tab edge of the tab _pad Satisfy C of 0.035 ∈C _pad ≤5。

For example, as shown in fig. 7, the multi-segment trace 30 in the second pixel region 020 includes a second trace 32 parallel to the second direction, and an edge of the gate line 200 closest to the second trace 32 near the second trace 32 is an inclined edge not parallel to the second direction. For example, the second wiring 32 may be configured in the first connection portion 330 or may be configured in the common electrode 320.

For example, the method of calculating the capacitance between the second wire 32 and the inclined edge of the gate line 200 adjacent thereto shown in fig. 7 may refer to the method of calculating the capacitance formed between the first wire and the protrusion edge in the example shown in fig. 1 and 5, as shown in fig. 7, the second parameter C in the capacitance between the second wire 32 and the inclined edge of the gate line 200 adjacent thereto _tft Can meet C _tft ＝ln[(L _h /d _h )×sinθ _h +1]. Wherein, the orthographic projection of the second trace 32 on the substrate 100 and the inclined edge of the gate line 200 are on the substrate100 is d _h The angle between the orthographic projection of the second trace 32 on the substrate 100 and the orthographic projection of the inclined edge of the gate line 200 on the substrate 100 is θ _h The second trace 32 has a length L _h . The second parameter C _tft And relative dielectric constant epsilon _d And the product of the line width W of the second trace 32 is the capacitance generated between the second trace and the slanted edge of the gate line.

For example, the minimum distance d between the second trace 32 and the gate line 200 _h May be 8.955259 micrometers, the length L of the second trace 32 _h May be 13.48103 micrometers, for example, the line width W of the second trace 32 may be 11.17 micrometers.

For example, assume ε _d 1, the minimum distance d between the second trace 32 and the gate line 200 is set to _h Length L of the second trace 32 _h Substitution of the relation ln [ (L) _h /d _h )×sinθ _h +1]Obtaining a second parameter C _tft A numerical value of 0.72487; substituting the above value and the line width W of the second trace 32 into W×ln [ (L) _h /d _h )×sinθ _h +1]The capacitance between the second trace 32 and the gate line 200 may be 2.537044F. Referring to fig. 1 and 5, the capacitance ch+cv= 3.872386 formed by the first trace 31 and the edge of the protruding portion, the ratio of the capacitance at two positions may be 1.526338.

For example, the length L of the second trace 32 _h May be 2 μm, and the minimum distance d between the second trace 32 and the gate line 200 is the minimum distance d _h If the minimum value of (2) is 2 μm, the minimum value is substituted into the relation ln [ (L) _h /d _h )×sinθ _h +1]Obtaining a second parameter C _tft Is 0.068323. For example, the length L of the second trace 32 _h The maximum value of (2) may be 30 μm, and the minimum distance d between the second trace 32 and the gate line 200 is the minimum distance d _h If the maximum value of (2) is 20 μm, the maximum value is substituted into the relation ln [ (L) _h /d _h )×sinθ _h +1]Obtaining a second parameter C _tft Is 2.451574. Reference is made to the first parameter C in the examples shown in FIGS. 1 and 5 _pad Is of the order of (2)Large value 4.903148 and first parameter C _pad Can obtain the first parameter C by the minimum value 0.483114 of (2) _pad Maximum value of (2) and second parameter C _tft The ratio of the maximum values of (2), the first parameter C _pad Minimum value of (2) and second parameter C _tft The ratio of the minima was 7.071068.

For example, the second parameter C _tft Satisfy C of 0.01-0 _tft Less than or equal to 2.5. For example, the second parameter C _tft Meet C of 0.05 to less than or equal to _tft And is less than or equal to 2. For example, the second parameter C _tft Satisfy C of 0.1-0 _tft Less than or equal to 2.2. For example, the second parameter C _tft Meet C of 0.5-0 _tft And is less than or equal to 2. For example, the second parameter C _tft Satisfy C of 1 to less than or equal to _tft Less than or equal to 1.5. For example, the second parameter C _tft Satisfy C of 1.5 ∈ _tft ≤2。

For example, the first parameter C _pad And a second parameter C _tft The ratio of (2) satisfies 1.ltoreq.C _pad /C _tft And is less than or equal to 7. For example, the first parameter C _pad And a second parameter C _tft The ratio of (2) to (2) is less than or equal to C _pad /C _tft And is less than or equal to 6. For example, the first parameter C _pad And a second parameter C _tft The ratio of (2) satisfies 3.ltoreq.C _pad /C _tft ≤5。

According to the embodiment of the disclosure, the first wiring of each section in the first pixel region corresponding to the grid line pad is arranged to extend along the first direction or the second direction, so that the ratio between the first parameter of the first pixel region and the second parameter of the second pixel region can be reduced, the capacitance consistency of different pixel regions is improved, and the parasitic capacitance of the grid line is reduced.

Fig. 8A is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 8A, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 8A schematically illustrates one pixel region 10. For example, as shown in fig. 8A, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. But is not limited thereto, the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchanged. For example, as shown in fig. 8A, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 8A, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 8A, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment wiring 30 extending along the outline of the pixel region 10" may mean that the multi-segment wiring extends along the edge of the data line 310 and the edge of the gate line 200. The multi-segment lines extending along the outline of the pixel region may be parallel to the extending direction of the edges of the data lines or the gate lines, but not limited thereto, and part of the lines of the multi-segment lines may be non-parallel to the edges of the gate lines or some part of the data lines, and whether the lines are parallel to the edges of the signal lines (including the gate lines and the data lines) adjacent thereto (in a plan view) may be set according to the requirements of the product.

As shown in fig. 8A, the multi-segment wire 30 includes a multi-segment first wire 31 surrounding at least a portion of the edge of the protrusion 211, each segment of the first wire 31 extends along a first direction or a second direction, and the multi-segment first wires 31 are connected end to form a step structure. The above-mentioned "the plurality of segments of the first wire 31 around at least part of the edge of the protrusion 211" may refer to an orthographic projection of the plurality of segments of the first wire 31 on the substrate 100 around at least part of the edge of the protrusion 211 on the substrate 100.

For example, as shown in fig. 8A, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, the example shown in fig. 8A is different from the example shown in fig. 1 in that the gate line pad 210 includes protruding portions 211 protruding with respect to both sides of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding to both sides of the gate line 200. Of course, the present example is not limited thereto, and the gate line pad in the present example may include only a protrusion protruding with respect to one side of the gate line.

For example, the positional relationship between the gate line pad and the supporting portion in the array substrate shown in fig. 8A may be the same as the positional relationship between the gate line pad and the supporting portion in the array substrate shown in fig. 1, and will not be described herein.

For example, as shown in fig. 8A, the edges of the protrusions 211 of the gate line pad 210 include a fold line or a curve.

For example, as shown in fig. 8A, each pixel region 10 may include one thin film transistor 500, but is not limited thereto, and the number of thin film transistors included in each pixel region may be set according to the performance of a desired pixel circuit, for example, the number of thin film transistors in each pixel region may be two or more.

For example, as shown in fig. 8A, each thin film transistor 500 includes a first pole 510, a gate electrode 530, and a second pole 520, where the first pole 510 and the second pole 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 further includes an active layer, each of the first and second electrodes 510 and 520 overlapping the active layer, and the gate electrode 530 overlapping the active layer. For example, the gate electrode 530 may be a partial structure of the gate line 200.

For example, as shown in fig. 8A, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connection portion 330, and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310.

For example, as shown in fig. 8A, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connection portion 330 are all structures in the metal layer 300.

For example, as shown in fig. 8A, the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be integrated, but the present invention is not limited thereto, and may be a two-part electrically connected structure. For example, the first electrode 510 of the thin film transistor 500 may be a portion where the metal layer 300 overlaps the active layer, and the first connection portion 330 may be a portion where the metal layer 300 does not overlap the active layer.

For example, the first connection portion 330 overlaps the pixel electrode 400 in a direction perpendicular to the substrate base plate 100. For example, in a direction perpendicular to the substrate base plate 100, a portion of the first connection portion 330 overlaps the pixel electrode 400.

For example, as shown in fig. 8A, the second connection part 340 overlaps the gate line 200 in a direction perpendicular to the substrate base 100. For example, the second connection portion 340 may be integrally formed with the second electrode 520 of the thin film transistor 500. For example, the second connection part 340 may be in an integrated structure with the data line 310. For example, the second electrode 520, the second connection portion 340, and the data line 310 of the thin film transistor 500 may be integrally formed. For example, the second connection part 340 may extend in the second direction. For example, the second connection part 340 is spaced apart from the common electrode 320.

For example, the array substrate shown in fig. 8A is different from the array substrate shown in fig. 1 in that it further includes: the gate electrode 530 of the thin film transistor 500 on the array substrate shown in fig. 8A is located on the gate line 200 except for the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 may be located at one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the substrate base plate 100, the gate electrode 530 of the thin film transistor 500 does not overlap the supporting portion 01, which is advantageous for increasing the flatness of the supporting portion. For example, in a direction perpendicular to the substrate base plate 100, the first pole 510 and the second pole 520 of the thin film transistor 500 may each have no overlap with the support 01.

The array substrate shown in fig. 8A is different from the array substrate shown in fig. 6 in that the metal layer does not include a common electrode, and the wirings are all structures in the first connection portion.

For example, as shown in fig. 8A, all of the traces 30 may be the first trace 31.

For example, as shown in fig. 8A, the first connection portion 330 includes the first trace 31. For example, the first wires 31 may have the structure of the first connection portion 330.

For example, as shown in fig. 8A, any one of the tracks 31 of the multi-segment tracks 30 may extend in a first direction or in a second direction.

The relationship between the first wires included in the first connection portion and the edges of the protruding portions of the gate line pads in this example has the same features as the relationship between the first wires included in the first connection portion and the edges of the protruding portions of the gate line pads in the array substrate shown in fig. 6, and will not be described here. The capacitance formed between the first trace included in the first connection portion and the protruding portion edge of the protruding portion in this example may be calculated in the same manner as the capacitance formed between the first trace and the protruding portion edge in the example shown in fig. 1 and 5.

For example, the second pixel region included in the array substrate shown in fig. 8A may have the same characteristics as the second pixel region shown in fig. 7, and the length ratio of the first connection portion and the area ratio of the first connection portion in the first pixel region and the second pixel region in the array substrate shown in fig. 8A may have the same characteristics as the length ratio of the first connection portion and the area ratio of the first connection portion in the first pixel region and the second pixel region in the array substrate shown in fig. 6 and 7, respectively, and are not described herein.

For example, the array substrate shown in fig. 8A further includes a common electrode line 600, and the common electrode line 600 may have the same features as the common electrode line shown in fig. 6, and will not be described herein.

Fig. 8B is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 8B, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 8B schematically illustrates one pixel region 10.

For example, as shown in fig. 8B, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. But is not limited thereto, the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchanged.

For example, as shown in fig. 8B, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 8B, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 8B, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 8B, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, the example shown in fig. 8B is different from the example shown in fig. 1 in that the gate line pad 210 includes protruding portions 211 protruding with respect to both sides of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding to both sides of the gate line 200.

For example, as shown in fig. 8B, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, the supporting portion 01 in this example may have the same features as the supporting portion 01 in the example shown in fig. 1, and will not be described here. For example, fig. 8B schematically illustrates that the supporting part 01 is provided on the array substrate, but is not limited thereto, and the supporting part may be provided on the opposite substrate, and the position of the supporting part may be set according to the product demand.

As shown in fig. 8B, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment wiring 30 extending along the outline of the pixel region 10" may mean that the multi-segment wiring extends along the edge of the data line 310 and the edge of the gate line 200. The multi-segment lines extending along the outline of the pixel region may be parallel to the extending direction of the edges of the data lines or the gate lines, but not limited thereto, and part of the lines of the multi-segment lines may be non-parallel to the edges of the gate lines or some part of the data lines, and whether the lines are parallel to the edges of the signal lines (including the gate lines and the data lines) adjacent thereto (in a plan view) may be set according to the requirements of the product.

For example, as shown in fig. 8B, the edges of the protrusions 211 of the gate line pad 210 include a fold line or a curve.

As shown in fig. 8B, the multi-segment wire 30 includes a multi-segment first wire 31 surrounding at least a portion of the edge of the protrusion 211, each segment of the first wire 31 extends along the first direction or the second direction, and the multi-segment first wires 31 are connected end to form a step structure. The above-mentioned "the plurality of segments of the first wire 31 around at least part of the edge of the protrusion 211" may refer to an orthographic projection of the plurality of segments of the first wire 31 on the substrate 100 around at least part of the edge of the protrusion 211 on the substrate 100.

For example, as shown in fig. 8B, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 or the gate lines 200 adjacent thereto. For example, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 adjacent thereto or the edges of the gate lines 200 near the wirings 30.

For example, as shown in fig. 8B, two segments of the traces 30 located at both ends of the outermost edge of the multi-segment first trace 31 may extend in the second direction. For example, two segments of wires 30 located at both ends of the outermost edge of the multi-segment first wire 31 may be electrically connected to the first wire 31. For example, two sections of wires 30 positioned at both ends of the outermost edge of the multi-section first wire 31 may be configured integrally with the first wire 31. However, the present invention is not limited thereto, and one segment of the wires of the two segments of wires located at the two ends of the outermost edge of the multi-segment first wire may be spaced apart from the first wire.

For example, as shown in fig. 8B, any one of the tracks 31 of the multi-segment tracks 30 may extend in a first direction or in a second direction.

For example, as shown in fig. 8B, the shape of the protruding portions 211 located at both sides of the center line of one gate line 200 extending in the Y direction may be the same or different. For example, the two protrusions 211 protruding from other positions of the gate line 200 included in the same gate line pad 210 may have the same shape or may be different. For example, the two protruding portions 211 included in the same gate line pad 210 may each have a trapezoid shape, an upper bottom of which protrudes into the pixel region 10 with respect to other portions of the gate line 200, and a lower bottom of which may be flush with an edge of at least part of the other portions of the gate line 200.

For example, as shown in fig. 8B, each pixel region 10 may include one thin film transistor 500, but is not limited thereto, and the number of thin film transistors included in each pixel region may be set according to the performance of a desired pixel circuit, for example, the number of thin film transistors in each pixel region may be two or more.

For example, as shown in fig. 8B, each thin film transistor 500 includes a first pole 510, a gate electrode 530, and a second pole 520, where the first pole 510 and the second pole 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 further includes an active layer, each of the first and second electrodes 510 and 520 overlapping the active layer, and the gate electrode 530 overlapping the active layer. For example, the gate electrode 530 may be a partial structure of the gate line 200.

For example, as shown in fig. 8B, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connection portion 330, and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310.

For example, as shown in fig. 8B, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connection portion 330 are all structures in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are all disposed insulated from the common electrode 320. For example, the first pole 510 of the thin film transistor 500 and the second pole 520 of the thin film transistor 500 are each disposed apart from the common electrode 320. For example, the first connection portion 330 is spaced apart from the common electrode 320.

For example, as shown in fig. 8B, the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be integrated, but the present invention is not limited thereto, and may be a two-part electrically connected structure. For example, the first electrode 510 of the thin film transistor 500 may be a portion where the metal layer 300 overlaps the active layer, and the first connection portion 330 may be a portion where the metal layer 300 does not overlap the active layer.

For example, as shown in fig. 8B, the second connection part 340 overlaps the gate line 200 in a direction perpendicular to the substrate base 100. For example, the second connection portion 340 may be integrally formed with the second electrode 520 of the thin film transistor 500. For example, the second connection part 340 may be in an integrated structure with the data line 310. For example, the second electrode 520, the second connection portion 340, and the data line 310 of the thin film transistor 500 may be integrally formed. For example, the second connection part 340 may extend in the second direction. For example, the second connection part 340 is spaced apart from the common electrode 320.

For example, the array substrate shown in fig. 8B is different from the array substrate shown in fig. 1 in that it further includes: the gate electrode 530 of the thin film transistor 500 on the array substrate shown in fig. 8B is located on the gate line 200 except for the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 may be located at one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the substrate base plate 100, the gate electrode 530 of the thin film transistor 500 does not overlap the supporting portion 01, which is advantageous for increasing the flatness of the supporting portion. For example, in a direction perpendicular to the substrate base plate 100, the first pole 510 and the second pole 520 of the thin film transistor 500 may each have no overlap with the support 01.

For example, the second pixel region included in the array substrate shown in fig. 8B may have the same characteristics as the second pixel region shown in fig. 7, and the length ratio of the common electrode and the area ratio of the common electrode in the first pixel region and the second pixel region in the array substrate shown in fig. 8B may have the same characteristics as the length ratio of the common electrode and the area ratio of the common electrode in the first pixel region and the second pixel region in the array substrate shown in fig. 6 and 7, respectively, and are not described herein.

For example, the array substrate shown in fig. 8B is different from the array substrate shown in fig. 6 in that only the common electrode 320 includes multiple segments of the first wires 31, and the first connection portion 330 does not include the first wires 31. For example, as shown in fig. 8B, the gate line pad 210 includes at least one edge of the protrusion 211 that is not parallel to both the first direction and the second direction.

For example, as shown in fig. 8B, two gate lines 200 located at both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, the common electrode 320 includes a first trace 31 surrounding a protrusion 211 of the gate line pad 210 on one of the two gate lines 200, the first connection 330 surrounds at least part of an edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200, and the first connection 330 surrounding at least part of the edge of the protrusion 211 includes a plurality of third traces each parallel to an edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each third trace on the substrate 100 is parallel to the orthographic projection of the edge of the projection 211 immediately adjacent thereto on the substrate 100. For example, at least one section of the third trace is not parallel to both the first direction and the second direction.

For example, as shown in fig. 8B, the gate line pad 210 includes two protruding portions 211 protruding toward both sides of the gate line 200 in the X direction, that is, includes a first protruding portion and a second protruding portion, the first wirings 31 surrounding the first protruding portion may be both common electrodes 320, the wirings 30 surrounding the second protruding portion are third wirings, a portion of the third wirings is the common electrodes 320, and another portion of the third wirings is the first connection portions 330. For example, all the first wires 31 around the first protrusion are wires 30 arranged continuously and end to end, and the third wires around the second protrusion comprise two parts of third wires arranged separately, at least one part of the third wires being arranged continuously and end to end. For example, the third traces included around the first connection portion 330 of the second protrusion are disposed continuously and end to end.

The relationship between the edges of the protruding portions of the gate line pads and the first wirings included in the common electrode in this example has the same features as the relationship between the edges of the protruding portions of the gate line pads and the first wirings included in the common electrode in the array substrate shown in fig. 6, and will not be described again here. The capacitance formed between the first trace included in the common electrode and the protrusion edge of the protrusion in this example may be calculated in the same manner as the capacitance formed between the first trace and the protrusion edge in the examples shown in fig. 1 and 5.

For example, as shown in fig. 8B, the capacitance between the third wiring parallel to the edge of the protrusion 211 and the edge of the protrusion 211 satisfies c=ε _d X W x L/d. Wherein ε _d For the relative dielectric constant, W is the line width of the third trace, L is the length of each segment of the third trace, and d is the distance between the third trace and the edge of the protrusion 211. For example, when the third trace is parallel to the edge of the protrusion 211, the capacitance C therebetween may have a value of 6.68.

For example, as shown in fig. 8B, the first connection part 330 includes a plurality of segments of third wires, and the plurality of segments of third wires may include third wires parallel to the first direction, third wires parallel to the second direction, and third wires non-parallel to both the first direction and the second direction.

For example, as shown in fig. 8B, the array substrate further includes a common electrode line 600, the common electrode line 600 being disposed in the same layer as the plurality of gate lines 200, and the common electrode 320 being electrically connected to the common electrode line 600.

For example, as shown in fig. 8B, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600, and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

For example, as shown in fig. 8B, the common electrode 320 in at least one pixel region 10 may be of an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. But is not limited thereto, the common electrode in at least one pixel region may be further provided in at least two structures separated from each other, each structure being electrically connected to the common electrode line.

For example, as shown in fig. 8B, the common electrode line 600 extends in the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged in the first direction. For example, the common electrode line 600 is disposed to overlap the pixel electrode 400 in a direction perpendicular to the substrate base plate 100.

For example, as shown in fig. 8B, the first connection part 330 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 8B, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction, and the third sub-common electrode 323 is aligned with at least a part of the sub-portions of the first connection portion 330 extending along the first direction to divide the pixel region 10 into two sub-pixel regions. For example, the third sub-common electrode 323 and the first connection part 330 are configured to cooperate to divide one pixel region into two sub-pixel regions. Of course, the embodiment of the present disclosure is not limited thereto, and the third sub common electrode may be not positioned in the same extension direction as the first connection portion.

For example, as shown in fig. 8B, two sub-pixel regions included in one pixel region 10 are arranged in the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions may be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 may be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 may be the same or different.

For example, as shown in fig. 8B, at least part of the first connection part 330 and the third sub common electrode 323 are located at both sides of the common electrode line 600, respectively. For example, the first connection part 330 includes a portion overlapping the common electrode line 600 and another portion not overlapping the common electrode line 600, and the portion of the first connection part 330 not overlapping the common electrode line 600 and the third sub-common electrode 323 are respectively located at both sides of the common electrode line 600. Of course, the embodiment of the present disclosure is not limited thereto, and the first connection part may further include two parts located at both sides of the common electrode line, in which case the third sub common electrode may not be provided; alternatively, the portion of the first connection portion on the same side of the common electrode line as the third sub-common electrode is provided with a shorter length to ensure a spacing with the third sub-common electrode. For example, when the first connection portion includes two portions provided on both sides of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection part includes two parts disposed at both sides of the common electrode line, the width of the part of the first connection part on the same side as the third sub common electrode line may have the same width as the third sub common electrode, but is not limited thereto, and the widths thereof may be different.

Fig. 9 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 9, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 9 schematically illustrates one pixel region 10.

For example, as shown in fig. 9, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction. But is not limited thereto, the first direction and the second direction may not be perpendicular. For example, the first direction and the second direction may be interchanged.

For example, as shown in fig. 9, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 9, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 9, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 9, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, the example shown in fig. 9 is different from the example shown in fig. 1 in that the gate line pad 210 includes protrusions 211 protruding with respect to both sides of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding to both sides of the gate line 200.

For example, as shown in fig. 9, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, the supporting portion 01 in this example may have the same features as the supporting portion 01 in the example shown in fig. 1, and will not be described here. For example, fig. 9 schematically illustrates that the supporting part 01 is provided on the array substrate, but is not limited thereto, and the supporting part may be provided on the opposite substrate, and the position of the supporting part may be set according to the product demand.

As shown in fig. 9, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment wiring 30 extending along the outline of the pixel region 10" may mean that the multi-segment wiring extends along the edge of the data line 310 and the edge of the gate line 200. The multi-segment lines extending along the outline of the pixel region may be parallel to the extending direction of the edges of the data lines or the gate lines, but not limited thereto, and part of the lines of the multi-segment lines may be non-parallel to the edges of the gate lines or some part of the data lines, and whether the lines are parallel to the edges of the signal lines (including the gate lines and the data lines) adjacent thereto (in a plan view) may be set according to the requirements of the product.

For example, as shown in fig. 9, the edges of the protrusions 211 of the gate line pad 210 include a fold line or a curve.

As shown in fig. 9, the multi-segment wire 30 includes a multi-segment first wire 31 surrounding at least a portion of the edge of the protrusion 211, each segment of the first wire 31 extends along a first direction or a second direction, and the multi-segment first wires 31 are connected end to form a step structure. The above-mentioned "the plurality of segments of the first wire 31 around at least part of the edge of the protrusion 211" may refer to an orthographic projection of the plurality of segments of the first wire 31 on the substrate 100 around at least part of the edge of the protrusion 211 on the substrate 100.

For example, as shown in fig. 9, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 or the gate lines 200 adjacent thereto. For example, the extending direction of the wirings 30 other than the first wirings 31 among the multi-stage wirings 30 may be parallel to the extending direction of the data lines 310 adjacent thereto or the edges of the gate lines 200 near the wirings 30.

For example, as shown in fig. 9, two segments of the traces 30 located at both ends of the outermost edge of the multi-segment first trace 31 may extend in the second direction. For example, two segments of wires 30 located at both ends of the outermost edge of the multi-segment first wire 31 may be electrically connected to the first wire 31. For example, two sections of wires 30 positioned at both ends of the outermost edge of the multi-section first wire 31 may be configured integrally with the first wire 31. However, the present invention is not limited thereto, and one segment of the wires of the two segments of wires located at the two ends of the outermost edge of the multi-segment first wire may be spaced apart from the first wire.

For example, as shown in fig. 9, any one of the multi-segment traces 30 may extend in a first direction or in a second direction.

For example, as shown in fig. 9, the shape of the protruding portions 211 located at both sides of the center line of one gate line 200 extending in the Y direction may be the same or different. For example, the two protrusions 211 protruding from other positions of the gate line 200 included in the same gate line pad 210 may have the same shape or may be different. For example, the two protruding portions 211 included in the same gate line pad 210 may each have a trapezoid shape, an upper bottom of which protrudes into the pixel region 10 with respect to other portions of the gate line 200, and a lower bottom of which may be flush with an edge of at least part of the other portions of the gate line 200.

For example, as shown in fig. 9, protruding portions 211 are provided on both sides of the gate line 200 in the X direction, and at this time, in one pixel region 10, the plurality of first wirings 31 in the plurality of wirings 30 are intensively distributed at two positions in the plurality of wirings 30.

For example, as shown in fig. 9, each pixel region 10 may include one thin film transistor 500, but is not limited thereto, and the number of thin film transistors included in each pixel region may be set according to the performance of a desired pixel circuit, for example, the number of thin film transistors in each pixel region may be two or more.

For example, as shown in fig. 9, each thin film transistor 500 includes a first pole 510, a gate electrode 530, and a second pole 520, where the first pole 510 and the second pole 520 overlap with the film layer where the gate line 200 is located. For example, the thin film transistor 500 further includes an active layer, each of the first and second electrodes 510 and 520 overlapping the active layer, and the gate electrode 530 overlapping the active layer. For example, the gate electrode 530 may be a partial structure of the gate line 200.

For example, as shown in fig. 9, the first electrode 510 of the thin film transistor 500 is electrically connected to the pixel electrode 400 through the first connection portion 330, and the second electrode 520 of the thin film transistor 500 is electrically connected to the data line 310.

For example, as shown in fig. 9, the first electrode 510 of the thin film transistor 500, the second electrode 520 of the thin film transistor 500, and the first connection portion 330 are all configured in the metal layer 300, and the first electrode 510 of the thin film transistor 500 and the second electrode 520 of the thin film transistor 500 are all disposed insulated from the common electrode 320. For example, the first pole 510 of the thin film transistor 500 and the second pole 520 of the thin film transistor 500 are each disposed apart from the common electrode 320. For example, the first connection portion 330 is spaced apart from the common electrode 320.

For example, as shown in fig. 9, the first electrode 510 of the thin film transistor 500 and the first connection portion 330 may be integrated, but the present invention is not limited thereto, and may be a two-part electrically connected structure. For example, the first electrode 510 of the thin film transistor 500 may be a portion where the metal layer 300 overlaps the active layer, and the first connection portion 330 may be a portion where the metal layer 300 does not overlap the active layer.

For example, as shown in fig. 9, the second connection part 340 overlaps the gate line 200 in a direction perpendicular to the substrate 100. For example, the second connection portion 340 may be integrally formed with the second electrode 520 of the thin film transistor 500. For example, the second connection part 340 may be in an integrated structure with the data line 310. For example, the second electrode 520, the second connection portion 340, and the data line 310 of the thin film transistor 500 may be integrally formed. For example, the second connection part 340 may extend in the second direction. For example, the second connection part 340 is spaced apart from the common electrode 320.

For example, the array substrate shown in fig. 9 is different from the array substrate shown in fig. 1 in that: the gate electrode 530 of the thin film transistor 500 on the array substrate shown in fig. 9 is located on the gate line 200 except for the gate line pad 210. For example, the gate electrode 530 of the thin film transistor 500 may be located at one side of the gate line pad 210 in the Y direction. For example, in a direction perpendicular to the substrate base plate 100, the gate electrode 530 of the thin film transistor 500 does not overlap the supporting portion 01, which is advantageous for increasing the flatness of the supporting portion. For example, in a direction perpendicular to the substrate base plate 100, the first pole 510 and the second pole 520 of the thin film transistor 500 may each have no overlap with the support 01.

For example, the second pixel region included in the array substrate shown in fig. 9 may have the same characteristics as the second pixel region shown in fig. 7, and the length ratio of the common electrode and the area ratio of the common electrode in the first pixel region and the second pixel region in the array substrate shown in fig. 9 may have the same characteristics as the length ratio of the common electrode and the area ratio of the common electrode in the first pixel region and the second pixel region in the array substrate shown in fig. 6 and 7, respectively, and are not described herein.

For example, the array substrate shown in fig. 9 is different from the array substrate shown in fig. 8B in that the first connection portion 330 and the common electrode 320 each include the first trace 31. For example, as shown in fig. 9, the gate line pad 210 includes at least one edge of the protrusion 211 that is not parallel to both the first direction and the second direction.

For example, as shown in fig. 9, two gate lines 200 located at both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, a first connection part 330 includes a first trace 31 surrounding a part of an edge of a protrusion 211 of the gate line pad 210 on one of the two gate lines 200, a common electrode 320 includes a first trace 31 surrounding another part of the edge of the protrusion 211 of the gate line pad 210, the common electrode 320 further includes a trace 30 surrounding an edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200, and the common electrode 320 surrounding the edge of the protrusion 211 includes a plurality of third traces, each of the third traces being parallel to an edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each third trace on the substrate 100 is parallel to the orthographic projection of the edge of the projection 211 immediately adjacent thereto on the substrate 100. For example, at least one section of the third trace is not parallel to both the first direction and the second direction.

For example, as shown in fig. 9, the gate line pad 210 includes two protruding portions 211 protruding to both sides of the gate line 200 in the X direction, that is, includes a first protruding portion and a second protruding portion, a part of the first wirings 31 surrounding the first protruding portion is a first connection portion 330, another part of the first wirings 31 surrounding the first protruding portion is a common electrode 320, the wirings 30 surrounding the second protruding portion are third wirings, and the third wirings are all common electrodes 320. For example, all third wires around the second protrusion are wires 30 arranged continuously and connected end to end, and the first wires 31 around the first protrusion include two parts of the first wires 31 arranged separately, at least one part of the first wires 31 being arranged continuously and connected end to end. For example, the first connection portion 330 surrounding the first protruding portion includes the first traces 31 that are continuously disposed and end-to-end. For example, the first wirings 31 included around the common electrode 320 of the first protrusion are continuously disposed and end to end.

The relationship between the edges of the protruding portions of the gate line pads and the first wirings included in the common electrode in this example has the same features as the relationship between the edges of the protruding portions of the gate line pads and the first wirings included in the common electrode in the array substrate shown in fig. 6, and will not be described again here.

The capacitance formed between the first trace included in the common electrode and the protrusion edge of the protrusion in this example may be calculated in the same manner as the capacitance formed between the first trace and the protrusion edge in the examples shown in fig. 1 and 5. The calculation manner of the capacitance between the third trace and the edge of the protruding portion in this example may be the same as that of the capacitance between the third trace and the edge of the protruding portion shown in fig. 8B, and will not be described herein.

For example, as shown in fig. 9, the array substrate further includes a common electrode line 600, the common electrode line 600 being disposed in the same layer as the plurality of gate lines 200, and the common electrode 320 being electrically connected to the common electrode line 600.

For example, as shown in fig. 9, an insulating layer (not shown) is provided between the common electrode 320 and the common electrode line 600, and the common electrode 320 is electrically connected to the common electrode line 600 through a via hole 11 in the insulating layer.

For example, as shown in fig. 9, the common electrode 320 in at least one pixel region 10 may be of an integrated structure, and the common electrode 320 in the pixel region 10 may be electrically connected to the common electrode line 600 through at least one via hole 11. But is not limited thereto, the common electrode in at least one pixel region may be further provided in at least two structures separated from each other, each structure being electrically connected to the common electrode line.

For example, as shown in fig. 9, the common electrode line 600 extends in the second direction. For example, the gate lines 200 and the common electrode lines 600 may be alternately arranged in the first direction. For example, the common electrode line 600 is disposed to overlap the pixel electrode 400 in a direction perpendicular to the substrate base plate 100.

For example, as shown in fig. 9, the first connection part 330 overlaps the common electrode line 600 in a direction perpendicular to the substrate base 100.

For example, as shown in fig. 9, the common electrode 320 further includes a third sub-common electrode 323 extending along the first direction, and the third sub-common electrode 323 is aligned with at least a part of the sub-portions of the first connection portion 330 extending along the first direction to divide the pixel region 10 into two sub-pixel regions. For example, the third sub-common electrode 323 and the first connection part 330 are configured to cooperate to divide one pixel region into two sub-pixel regions. Of course, the embodiment of the present disclosure is not limited thereto, and the third sub common electrode may be not positioned in the same extension direction as the first connection portion.

For example, as shown in fig. 9, one pixel region 10 includes two sub-pixel regions arranged in the Y direction. For example, the shapes of the pixel electrodes in different sub-pixel regions may be the same or different. For example, the shapes of different sub-pixel regions in the same pixel region 10 may be the same or different. For example, the areas of different sub-pixel regions in the same pixel region 10 may be the same or different.

For example, as shown in fig. 9, at least part of the first connection part 330 and the third sub common electrode 323 are located at both sides of the common electrode line 600, respectively. For example, the first connection part 330 includes a portion overlapping the common electrode line 600 and another portion not overlapping the common electrode line 600, and the portion of the first connection part 330 not overlapping the common electrode line 600 and the third sub-common electrode 323 are respectively located at both sides of the common electrode line 600. Of course, the embodiment of the present disclosure is not limited thereto, and the first connection part may further include two parts located at both sides of the common electrode line, in which case the third sub common electrode may not be provided; alternatively, the portion of the first connection portion on the same side of the common electrode line as the third sub-common electrode is provided with a shorter length to ensure a spacing with the third sub-common electrode. For example, when the first connection portion includes two portions provided on both sides of the common electrode line, the widths of the two portions may be equal or unequal. For example, when the first connection part includes two parts disposed at both sides of the common electrode line, the width of the part of the first connection part on the same side as the third sub common electrode line may have the same width as the third sub common electrode, but is not limited thereto, and the widths thereof may be different.

Fig. 10 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 10, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10.

As shown in fig. 10, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 10, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 10, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. The multi-segment trace 30 includes a multi-segment first trace 31 surrounding at least a portion of an edge of the protrusion 211, each segment of the first trace 31 extending in a first direction or a second direction, the multi-segment first trace 31 being connected end-to-end to form a step structure. According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The array substrate provided in this example is different from the array substrate shown in fig. 6 in the shape of the gate line pad 210. For example, as shown in fig. 10, the shape of the gate line pad 210 may be polygonal. For example, the shape of the protrusion 211 may be polygonal. For example, the shape of the protrusion 211 may be an irregular shape.

For example, the distribution of the first traces 31 around at least a portion of the edges of the protruding portions 211 of the gate line pad 210 in the array substrate provided in this example may be the same as the distribution of the first traces shown in fig. 6, or may be the same as the distribution of the first traces shown in fig. 8B or 9, which is not limited in this embodiment of the disclosure.

The structures of the substrate, the data line, the common electrode line, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate provided in this example may have the same features as the structures of the substrate, the data line, the common electrode line, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate shown in fig. 1 to 9, which are not described herein.

Fig. 11 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 11, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10.

As shown in fig. 11, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 11, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 11, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. The multi-segment trace 30 includes a multi-segment first trace 31 surrounding at least a portion of an edge of the protrusion 211, each segment of the first trace 31 extending in a first direction or a second direction, the multi-segment first trace 31 being connected end-to-end to form a step structure. According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The array substrate provided in this example is different from the array substrate shown in fig. 6 in the shape of the gate line pad 210. For example, as shown in fig. 11, the shape of the gate line pad 210 may be polygonal. For example, the shape of the protrusion 211 may be polygonal. For example, the shape of the protrusion 211 may be an irregular shape.

Fig. 12 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 12, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10.

As shown in fig. 12, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 12, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 12, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. The multi-segment trace 30 includes a multi-segment first trace 31 surrounding at least a portion of an edge of the protrusion 211, each segment of the first trace 31 extending in a first direction or a second direction, the multi-segment first trace 31 being connected end-to-end to form a step structure. According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The structures of the substrate, the data line, the gate line, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate provided in this example may have the same features as the structures of the substrate, the data line, the gate line, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate shown in fig. 1 to 11, which are not described herein.

The array substrate provided in this example is different from the array substrate shown in fig. 1 in that the common electrode 320 further includes a third sub-common electrode 323 extending in the first direction and two fourth sub-common electrodes 324 extending in the second direction, the two fourth sub-common electrodes 324 being located at both sides of the first connection portion 330 in the second direction, and the third sub-common electrode 323 being located on the same line as at least a part of the sub-portions of the first connection portion 330. For example, the common electrode 320 including the third sub-common electrode 323 and the fourth sub-common electrode 324 may divide one pixel region 10 into four sub-pixel regions. For example, four sub-pixel regions may be arranged in an array of 2×2.

The third sub common electrode 323 in this example may have the same features as the third sub common electrode 323 shown in fig. 1, and will not be described again here.

For example, as shown in fig. 12, the orthographic projection of the fourth sub-common electrode 324 on the substrate base plate 100 overlaps with the orthographic projection of the common electrode line 600 on the substrate base plate 100.

For example, the distribution of the first traces 31 around at least a portion of the edges of the protruding portions 211 of the gate line pad 210 in the array substrate provided by the present example may not be limited to the distribution shown in fig. 1, for example, the distribution of the first traces 31 in the array substrate provided by the present example may be the same as the distribution rule of the first traces shown in fig. 6, or may be the same as the distribution rule of the first traces shown in fig. 8B or 9, which is not limited in the embodiments of the present disclosure.

Fig. 13 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 13, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10.

As shown in fig. 13, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 13, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 13, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. The multi-segment trace 30 includes a multi-segment first trace 31 surrounding at least a portion of an edge of the protrusion 211, each segment of the first trace 31 extending in a first direction or a second direction, the multi-segment first trace 31 being connected end-to-end to form a step structure. According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The structures of the substrate, the data line, the common electrode, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate provided in this example may have the same features as the structures of the substrate, the data line, the common electrode, the thin film transistor, the first connection portion, the second connection portion, and the pixel electrode in the array substrate shown in fig. 1 to 11, which are not described herein.

The array substrate provided in this example is different from the array substrate shown in fig. 1 in that the gate line 200 includes a hollowed pattern 201, and the data line 310 overlaps the hollowed pattern 201. For example, the hollowed-out pattern 201 includes an opening. For example, the hollowed-out pattern 201 may include a plurality of openings. In the array substrate provided by the example, the hollowed-out patterns are arranged in the grid lines, and the hollowed-out patterns of the grid lines are overlapped with the data lines, so that the overlapping area of the data lines and the grid lines can be reduced, and the capacitance generated when the data lines and the grid lines are overlapped is further reduced.

Fig. 14 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. As shown in fig. 14, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10.

As shown in fig. 14, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 14, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

As shown in fig. 14, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. The multi-segment trace 30 includes a multi-segment first trace 31 surrounding at least a portion of an edge of the protrusion 211, each segment of the first trace 31 extending in a first direction or a second direction, the multi-segment first trace 31 being connected end-to-end to form a step structure. According to the embodiment of the disclosure, the first wiring surrounding the protruding part of the grid line pad is in the step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

The array substrate provided in this example is different from the array substrate shown in fig. 13 in that the second connection portion 340 and the data line 310 overlap the hollowed pattern 201. For example, the hollowed-out pattern 201 includes an opening. For example, the hollowed-out pattern 201 may include a plurality of openings. In the array substrate provided by the example, the hollowed-out pattern is arranged in the grid line, and the hollowed-out pattern of the grid line is overlapped with the data line and the second connecting part, so that the overlapping area of the data line and the second connecting part with the grid line can be reduced, and the capacitance generated when the metal layer is overlapped with the grid line is further reduced.

For example, as shown in fig. 14, the first end of the second connection portion 340 is electrically connected to the second pole 520 of the thin film transistor 500, the second end of the second connection portion 340 is electrically connected to the data line 310, and the width of the hollowed pattern 201 gradually increases along the direction in which the first end points to the second end. This example is favorable to reducing the overlapping area of data line and second connecting portion and gate line while preventing the hollowed pattern from influencing the performance of thin film transistor, such as reducing the abrupt change of parasitic capacitance of the source electrode of Thin Film Transistor (TFT), by setting the shape of hollowed pattern to point to the direction of the second end along the first end, the width increases gradually, and the stability of TFT performance is maintained.

For example, as shown in fig. 14, the shape of the hollowed-out pattern 201 may include a trapezoid. For example, the upper bottom of the trapezoid is close to the thin film transistor 500, and the lower bottom of the trapezoid is close to the data line 310.

Fig. 15 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. The array substrate shown in fig. 15 is different from the array substrate shown in fig. 14 only in the shape of the hollowed pattern 201 disposed in the gate line 200. For example, as shown in fig. 15, the hollowed-out pattern 201 is triangular in shape.

Fig. 16 is a schematic view of a partial planar structure of an array substrate according to another example of an implementation of the present disclosure. The array substrate shown in fig. 16 is different from the array substrate shown in fig. 14 only in the shape of the hollowed pattern 201 disposed in the gate line 200. For example, as shown in fig. 16, the hollowed pattern 201 is in the shape of a drop.

Fig. 17 is a schematic view of a partial planar structure of an array substrate according to another embodiment of the disclosure. As shown in fig. 17, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 17 schematically illustrates one pixel region 10.

For example, as shown in fig. 17, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, fig. 17 schematically shows that the first direction is the X direction and the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the first direction and the second direction may not be perpendicular, and for example, an included angle between the first direction and the second direction may be 30-60 degrees. For example, the first direction and the second direction may be interchanged.

For example, as shown in fig. 17, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 17, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 17, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 17, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, as shown in fig. 17, the gate line pad 210 may include a protrusion 211 protruding with respect to one side of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding toward the same side of the gate line 200.

For example, the pixel region 10 does not include the protrusion 211.

For example, as shown in fig. 17, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, fig. 17 schematically shows that the support portion 01 has a circular shape in a plane shape parallel to the XY plane, but is not limited thereto, and may have a regular shape such as a polygon or an irregular shape.

As shown in fig. 17, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment wiring 30 extending along the outline of the pixel region 10" may mean that the multi-segment wiring extends along the edge of the data line 310 and the edge of the gate line 200. The multi-segment lines extending along the outline of the pixel region may be parallel to the extending direction of the edges of the data lines or the gate lines, but not limited thereto, and part of the lines of the multi-segment lines may be non-parallel to the edges of the gate lines or some part of the data lines, and whether the lines are parallel to the edges of the signal lines (including the gate lines and the data lines) adjacent thereto (in a plan view) may be set according to the requirements of the product.

For example, as shown in fig. 17, the edge of the protrusion 211 of the gate line pad 210 includes a folding line.

As shown in fig. 17, the multi-segment trace 30 includes multi-segment trace sub-portions 33 surrounding at least a portion of the edge of the protrusion 211, each segment trace sub-portion 33 being parallel to the edge of the protrusion 211 immediately adjacent thereto. For example, the orthographic projection of each segment of trace sub-portion 33 on the substrate 100 is parallel to the orthographic projection of the edge of the projection 211 immediately adjacent thereto on the substrate 100. For example, at least one of the trace sub-portions 33 is not parallel to both the first direction and the second direction.

The embodiment of the disclosure is beneficial to maximizing the aperture ratio of the pixel region by setting the wiring sub-part surrounding the protruding part of the grid line pad to be parallel to the extending direction of the edge of the protruding part.

For example, two wire sub-sections 33 connected end to end among the multi-stage wire sub-sections 33 are electrically connected. For example, the multi-stage trace sub-portion 33 may be an integrated structure. For example, the distance between the orthographic projection of the multi-segment trace sub-portion 33 on the substrate 100 and the orthographic projection of the edge of the surrounding protrusion 211 on the substrate is smaller than the distance between the orthographic projection of the other trace on the substrate 100 and the edge of the protrusion 211. For example, the distances between the different routing sub-portions 33 and the edges of the protrusions 211 around them are all the same.

For example, as shown in fig. 17, each of the plurality of segment wirings 30 extends in a direction parallel to the extending direction of the data line 310 or the gate line 200 adjacent thereto.

For example, as shown in fig. 17, two segments of wires 30 positioned at both ends of the outermost edge of the multi-segment wire sub-section 33 may be electrically connected to the wire sub-section 33. For example, two wires 30 positioned at both ends of the outermost edge of the multi-stage wire sub-section 33 may be configured integrally with the wire sub-section 33. However, the present invention is not limited thereto, and one section of the trace of the two sections of traces located at the two ends of the extreme edge of the multi-section first trace may be spaced apart from the trace sub-section.

For example, as shown in fig. 17, the wirings 30 other than the wiring sub-portion 33 in the multi-stage wirings 30 may extend in the first direction or in the second direction.

The shape and distribution of the protrusions in the example shown in fig. 17 may be the same as those in any of the examples shown in fig. 1 to 16, and will not be described again.

The structures of the substrate 100, the data line 310, the thin film transistor 500, the second connection portion 340, and the pixel electrode in the array substrate in the example shown in fig. 17 may have the same features as the structures of the substrate 100, the data line 310, the thin film transistor 500, the second connection portion 340, and the pixel electrode 400 in the array substrate in any one of the examples shown in fig. 1 to 16, and are not described here again.

For example, the distribution of the multi-segment traces 30 shown in fig. 17 may be similar to the distribution of the multi-segment traces 30 shown in fig. 1, and all are common electrodes, but not limited thereto; for example, the multi-segment wiring 30 shown in fig. 17 may be distributed as the multi-segment wiring 30 shown in fig. 9, wherein a part of the multi-segment wiring 30 is the common electrode 320 and the other part is the first connection portion 330. For example, the multi-segment wires 30 shown in fig. 17 may be distributed as the multi-segment wires 30 shown in fig. 8A, and the multi-segment wires 30 are all the first connection portions 330.

For example, as shown in fig. 17, when the trace sub-portion 33 in the multi-segment trace 30 is a part of the first connection portion 330, the distribution of the first connection portion 330 may be the same as the distribution of the first connection portion 330 shown in fig. 8B, and will not be described herein.

For example, the capacitance between the trace sub-portion 33 and the edge of the protrusion 211 shown in fig. 17 may be calculated in a manner similar to the capacitance c=ε between the third trace parallel to the edge of the protrusion 211 and the edge of the protrusion 211 shown in fig. 8B _d The calculation mode of xW x L/d is the same and will not be described in detail here.

Fig. 18 is a schematic view of a partial planar structure of an array substrate according to another embodiment of the disclosure. As shown in fig. 18, the array substrate includes a substrate 100, and a plurality of gate lines 200 and metal layers 300 on the substrate 100. The metal layer 300 is located at a side of the plurality of gate lines 200 remote from the substrate 100, the metal layer 300 includes a plurality of data lines 310, the plurality of data lines 310 extend in a first direction and are arranged in a second direction, the plurality of gate lines 200 extend in the second direction and are arranged in the first direction, the first direction and the second direction intersect, and the plurality of data lines 310 intersect the plurality of gate lines 200 to define a plurality of pixel regions 10. Fig. 18 schematically illustrates one pixel region 10.

For example, as shown in fig. 18, a plurality of data lines 310 extend in the X direction and are arranged in the Y direction; the plurality of gate lines 200 extend in the Y direction and are aligned in the X direction. For example, fig. 18 schematically shows that the first direction is the X direction and the second direction is the Y direction, and the first direction is perpendicular to the second direction. However, the first direction and the second direction may not be perpendicular, and for example, an included angle between the first direction and the second direction may be 30-60 degrees. For example, the first direction and the second direction may be interchanged.

For example, as shown in fig. 18, two adjacent data lines 310 and two adjacent gate lines 200 are disposed to cross each other to define one pixel region 10. For example, one pixel region 10 is one sub-pixel. For example, the array substrate includes a plurality of sub-pixels (a plurality of pixel regions 10) including sub-pixels configured to display different colors of light. For example, the plurality of subpixels may include a red subpixel configured to display red light, a green subpixel configured to display green light, and a blue subpixel configured to display blue light. For example, two adjacent sub-pixels arranged in the direction of at least one of the first direction and the second direction are sub-pixels configured to display different colors of light, respectively.

As shown in fig. 18, the metal layer 300 further includes a common electrode 320 located in the pixel region 10. For example, the common electrode 320 may be a film layer disposed at the same layer as the data line 310 and made of the same material.

As shown in fig. 18, at least one gate line 200 includes a gate line pad 210, and the gate line pad 210 includes a protrusion 211 protruding into the pixel region 10 with respect to a position on the gate line 200 other than the gate line pad 210.

For example, as shown in fig. 18, the gate line pad 210 is a part of the structure of the gate line 200. For example, in the X direction, the width of the gate line pad 210 is greater than the width of the gate line 200 at a position other than the gate line pad 210. For example, in the width direction, the position of the gate line pad 210 protruding with respect to the gate line 200 at a position other than the gate line pad 210 is the protruding portion 211.

For example, as shown in fig. 18, the gate line pad 210 may include a protrusion 211 protruding with respect to one side of the gate line 200. For example, a plurality of gate line pads 210 may be disposed on one gate line 200, and each of the plurality of gate line pads 210 includes a protrusion 211 protruding toward the same side of the gate line 200.

For example, the pixel region 10 does not include the protrusion 211.

For example, as shown in fig. 18, the gate line pad 210 is configured to be disposed opposite to the supporting portion 01. For example, the gate line pad 210 overlaps the support part 01 in a direction perpendicular to the substrate base 100. For example, the orthographic projection of the gate line pad 210 on the substrate base plate 100 may overlap with the orthographic projection of the supporting portion 01 on the substrate base plate 100. For example, the orthographic projection of the support portion 01 on the substrate 100 may fall entirely within the orthographic projection of the gate line pad 210 on the substrate 100. For example, fig. 17 schematically shows that the support portion 01 has a circular shape in a plane shape parallel to the XY plane, but is not limited thereto, and may have a regular shape such as a polygon or an irregular shape.

As shown in fig. 18, the metal layer 300 located in the pixel region 10 includes a multi-segment trace 30 extending along at least a portion of the outline of the pixel region 10. For example, at least some of the multi-segment traces 30 are electrically connected traces. For example, among the plurality of wirings 30, the wirings electrically connected to each other are integrally provided. The above-mentioned "integrally provided wirings" may refer to wirings formed by performing the patterning process on the same metal material layer at the same step. The above-described "multi-segment wiring 30 extending along the outline of the pixel region 10" may mean that the multi-segment wiring extends along the edge of the data line 310 and the edge of the gate line 200. The multi-segment lines extending along the outline of the pixel region may be parallel to the extending direction of the edges of the data lines or the gate lines, but not limited thereto, and part of the lines of the multi-segment lines may be non-parallel to the edges of the gate lines or some part of the data lines, and whether the lines are parallel to the edges of the signal lines (including the gate lines and the data lines) adjacent thereto (in a plan view) may be set according to the requirements of the product.

For example, as shown in fig. 18, the edge of the protrusion 211 of the gate line pad 210 includes a curve. For example, the edge of the protrusion 211 of the gate line pad 210 may have a circular arc shape. For example, the shape of the protrusion 211 may be semicircular.

As shown in fig. 18, the multi-segment trace 30 includes multi-segment trace sub-portions 33 surrounding at least part of the edges of the protruding portion 211, each segment trace sub-portion 33 being parallel to the edge of the protruding portion 211 immediately adjacent thereto. For example, the orthographic projection of each segment of trace sub-portion 33 on the substrate 100 is parallel to the orthographic projection of the edge of the projection 211 immediately adjacent thereto on the substrate 100. For example, at least one of the trace sub-portions 33 is not parallel to both the first direction and the second direction. For example, the trace sub-portion 33 surrounding the edge of one protrusion 211 may be arc-shaped, and the trace sub-portion 33 surrounding the edge of one protrusion 211 may be a whole length of the trace 30. For example, the edge profile of the trace sub-portion 33 is infinityWhen the polygon is in a shape similar to a circular arc, the radius r of the circular arc is designed to be r=2l ₀ /π，l ₀ The equivalent length of the trace L' when no gate pad is provided for the corresponding gate line at the position of the trace sub-section 33.

For example, the capacitance between the trace sub-portion 33 and the edge of the protrusion 211 shown in fig. 18 may be calculated in a manner similar to the capacitance c=ε between the third trace parallel to the edge of the protrusion 211 and the edge of the protrusion 211 shown in fig. 8B _d The calculation mode of xW x L/d is the same and will not be described in detail here.

The array substrate shown in fig. 18 is different from the array substrate shown in fig. 17 in that the shape of the gate pad and the shape of the protruding portion of the trace sub-portion surrounding the gate pad are different.

For example, the structures of the substrate 100, the data line 310, the thin film transistor 500, the second connection portion 340, and the pixel electrode in the array substrate in the example shown in fig. 18 may have the same features as the structures of the substrate 100, the data line 310, the thin film transistor 500, the second connection portion 340, and the pixel electrode 400 in the array substrate in any one of the examples shown in fig. 1 to 17, and are not described here again.

For example, as shown in fig. 18, when the gate line pad 210 has the protrusion 211 at both sides in the Y direction with respect to the gate line 200, the routing sub-portion 33 surrounding the protrusion 211 may be at least one of the common electrode 320 and the first connection portion 330.

For example, as shown in fig. 18, two gate lines 200 located at both sides of at least one first pixel region 010 each include a gate line pad 210 protruding into the first pixel region 010, the common electrode 320 includes a trace sub-portion 33 surrounding a protrusion 211 of the gate line pad 210 on one of the two gate lines 200, the first connection portion 330 surrounds at least part of an edge of the protrusion 211 of the gate line pad 210 on the other of the two gate lines 200, the first connection portion 330 surrounding at least part of the edge of the protrusion 211 includes the trace sub-portion 33, and each segment of the trace sub-portion 33 is parallel to an edge of the protrusion 211 adjacent thereto. For example, the orthographic projection of each segment of trace sub-portion 33 on the substrate 100 is parallel to the orthographic projection of the edge of the projection 211 immediately adjacent thereto on the substrate 100. For example, at least one of the trace sub-portions 33 is not parallel to both the first direction and the second direction.

For example, as shown in fig. 18, the gate line pad 210 includes two protruding portions 211 protruding to both sides of the gate line 200 in the X direction, that is, includes a first protruding portion and a second protruding portion, the first wirings 31 surrounding the first protruding portion may be both common electrodes 320, a portion of the wiring sub-portions 33 surrounding the second protruding portion is the common electrode 320, and another portion of the wiring sub-portions 33 is the first connection portion 330.

The example shown in fig. 18 schematically shows that the gate electrode of the thin film transistor does not overlap the supporting portion, but is not limited thereto, and the gate electrode of the thin film transistor may be disposed to overlap the supporting portion.

The example shown in fig. 18 provides an array substrate, and other structures in the array substrate shown in fig. 18 may have the same features as any of the above embodiments except that the shapes of the gate line pads and the shapes of the traces around the edges of the gate line pads are different from those of the above embodiments, and will not be described herein.

For example, another embodiment of the present disclosure provides a display device, which includes the array substrate provided in any one of the above embodiments. In the display device provided by the embodiment of the disclosure, the first wiring of the protruding portion surrounding the gate line pad on the array substrate is set to be of a step structure, so that the influence of the metal layer on the aperture ratio in the pixel region is reduced while the consistency of the capacitance generated by the metal layer and the pixel electrode in different pixel regions is improved.

For example, the display device may further include a color film substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.

For example, the display device may be a liquid crystal display device, or any product or part having a display function including a television, a digital camera, a mobile phone, a wristwatch, a tablet computer, a notebook computer, a navigator, or the like, to which the embodiment is not limited.

The following points need to be described:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to the general design.

(2) Features of the same and different embodiments of the disclosure may be combined with each other without conflict.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.

Claims

1. An array substrate, comprising:

a substrate base;

a plurality of gate lines on the substrate;

a metal layer located at a side of the plurality of gate lines away from the substrate base plate, the metal layer including a plurality of data lines extending in a first direction and arranged in a second direction, the plurality of gate lines extending in the second direction and arranged in the first direction, the first direction intersecting the second direction, the plurality of data lines intersecting the plurality of gate lines to define a plurality of pixel regions;

Wherein at least one gate line comprises a gate line pad, the gate line pad comprises a protrusion protruding into the pixel region relative to a position on the gate line except for the gate line pad, and the metal layer positioned in the pixel region comprises a plurality of sections of wirings extending along at least part of the outline of the pixel region;

the multi-section wire comprises a multi-section first wire surrounding at least part of the edge of the protruding part, each section of first wire extends along the first direction or the second direction, and the multi-section first wires are connected end to form a step structure;

the array substrate further comprises a pixel electrode and a thin film transistor, wherein the thin film transistor comprises a first electrode, a grid electrode and a second electrode, the first electrode and the second electrode are overlapped with a film layer where the grid line is located, the first electrode is electrically connected with the pixel electrode through a first connecting part, and the second electrode is electrically connected with the data line; the first pole, the second pole and the first connecting part are all structures in the metal layer;

the plurality of pixel areas comprise at least one first pixel area and at least one second pixel area, the first pixel area is a pixel area corresponding to the grid line pad, and the second pixel area is a pixel area corresponding to a position on the grid line except for the grid line pad; the first connection part comprises at least part of the multi-section first wiring, and the area ratio of the orthographic projection of the first connection part in the first pixel area on the substrate to the orthographic projection of the first connection part in the second pixel area on the substrate is 0.8-1.2.

2. The array substrate of claim 1, wherein the first connection part overlaps the pixel electrode in a direction perpendicular to the substrate.

3. The array substrate of claim 1, wherein the metal layer further comprises a common electrode located at the pixel region;

the common electrode overlaps the pixel electrode in a direction perpendicular to the substrate base plate, and the first and second electrodes of the thin film transistor are each disposed insulated from the common electrode.

4. The array substrate of claim 3, wherein the common electrode comprises at least a portion of the first traces of the multi-segment first trace.

5. The array substrate of claim 4, wherein a ratio of a length of the common electrode in the first pixel region to a length of the common electrode in the second pixel region is 0.8 to 1.2.

6. The array substrate of claim 1, wherein a ratio of a length of the first connection portion in the first pixel region to a length of the first connection portion in the second pixel region is 0.8 to 1.2.

7. The array substrate of claim 1, wherein the edge of the protruding portion includes a protruding portion edge having an extension direction not parallel to the first direction and the second direction, the number of the plurality of segments of first traces is 2 or more, and the length of each segment of first trace is L _i The orthographic projection of each section of first wiring on the substrate is a first orthographic projection, the orthographic projection of the edge of the protruding part on the substrate is a second orthographic projection, the first orthographic projection comprises a long side which extends along the extending direction and is close to the second orthographic projection, and the minimum distance between the long side and the second orthographic projection is d _i The included angle between the long side and the second orthographic projection is theta _i A first parameter C in the capacitance between the first trace and the protrusion edge _pad Satisfy the following requirementsN is the number of the multi-section first wirings, i is a positive integer not less than 1, and N is a positive integer not less than 2.

8. The array substrate of claim 7, wherein the first parameter C _pad Satisfy C of 0.035 ∈C _pad ≤5。

9. The array substrate of claim 7, wherein the multi-segment lines in the second pixel region include a second line parallel to the second direction, and an edge of the gate line closest to the second line near the second line is an inclined edge not parallel to the second direction;

the minimum distance between the orthographic projection of the second wire on the substrate and the orthographic projection of the inclined edge on the substrate is d _h The length of the second trace is L _h The second wire is arranged on theThe angle between the orthographic projection on the substrate and the orthographic projection of the inclined edge on the substrate is theta _h A second parameter C of the capacitance between the second trace and the inclined edge _tft Satisfy C _tft ＝ln[(L _h /d _h )×sinθ _h +1]。

10. The array substrate of claim 9, wherein the second parameter C _tft Satisfy C of 0.01-0 _tft ≤2.5。

11. The array substrate of claim 9, wherein a ratio of the first parameter to the second parameter satisfies 1C _pad /C _tft ≤7。

12. The array substrate of any one of claims 1-11, wherein each of the multi-segment traces extends in the first direction or the second direction.

13. The array substrate according to any one of claims 1 to 11, wherein the gate line pad is configured to be disposed opposite to the support portion in a direction perpendicular to the substrate.

14. The array substrate of any one of claims 1 to 11, wherein the first connection portion extends along the first direction to be electrically connected with the pixel electrode.

15. The array substrate of claim 14, wherein the gate line pad comprises the gate electrode.

16. The array substrate of any one of claims 3-5, wherein the multi-segment first trace comprises two portions, one of the two portions being the common electrode and the other of the two portions being the first connection.

17. The array substrate of claim 16, wherein two gate lines located at both sides of at least one first pixel region each include the gate line pad protruding into the first pixel region, the common electrode includes the first trace surrounding a protrusion of the gate line pad on one of the two gate lines, and the first connection portion includes the first trace surrounding a protrusion of the gate line pad on the other of the two gate lines.

18. The array substrate of claim 16, wherein the gate electrode is located on the gate line at a position other than the gate line pad.

19. The array substrate of claim 18, wherein the first connection portion includes a sub-portion extending in the first direction and a sub-portion extending in the second direction.

20. The array substrate of claim 3 or 4, further comprising: and the public electrode wire is arranged on the same layer as the plurality of gate wires, and the public electrode is electrically connected with the public electrode wire.

21. The array substrate of claim 20, wherein the common electrode line extends in the second direction, and the first connection part overlaps the common electrode line in a direction perpendicular to the substrate.

22. The array substrate of claim 20, wherein an insulating layer is disposed between the pixel electrode and the metal layer, the first connection portion is electrically connected to the pixel electrode through a via hole in the insulating layer, and a straight line parallel to the first direction passes through the via hole and an orthographic projection of the gate line pad on the substrate.

23. The array substrate of any one of claims 1-11, wherein an edge of the protrusion comprises a fold line or a curve.

24. The array substrate of any one of claims 1-11, wherein the first connection portion is of a very integrated structure with the first electrode of the thin film transistor.

25. A display device comprising the array substrate of any one of claims 1-24.