CN104503164B - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN104503164B CN104503164B CN201410836490.9A CN201410836490A CN104503164B CN 104503164 B CN104503164 B CN 104503164B CN 201410836490 A CN201410836490 A CN 201410836490A CN 104503164 B CN104503164 B CN 104503164B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses a kind of array base palte and preparation method thereof, display device.The embodiment of the present invention provides a kind of array base palte, has multiple dot structures on the substrate of the array base palte；Bucking electrode, bottom crown and the scan line of storage capacitance are located at the bottom crown multiplexing part bucking electrode of same layer storage capacitance；Layer where first insulating barrier covering storage capacitance bottom crown；The top crown of storage capacitance is arranged on first insulating barrier, and at least has the part overlapping with the bottom crown of the storage capacitance in same layer, the top crown of storage capacitance with data line bit, and dot structure is divided at least two transparent areas by the overlapping part.The embodiment of the present invention is by the shape of storage capacitance is changed, being divided at least two transparent areas by transparent area, having disperseed light tight area, so as to effectively prevent the grid sense problem caused by the light tight area of large area.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display device.
Background technology
In the dot structure of general liquid crystal display, it is necessary to configure storage capacitance to store pixel data to next update
Time.As shown in Figure 1 for dot structure schematic diagram, the dot structure include transmission region 101 and lightproof area in the prior art
102, lightproof area 102 is the zone of opacity formed by cabling and storage capacitance pole plate etc..Because storage capacitance pole plate is usual
It is two layers of lighttight metal level, therefore the configuration of the storage capacitance causes the area of transmission region 101 in dot structure to subtract
It is small, and then cause the aperture opening ratio of panel to reduce.
For a kind of existing total reflection display unit, when as electronic tag, due to generally carrying out static state display, it is not required to
To refresh at a high speed, therefore, generally require using relatively low driving frequency, such as 20Hz, 1Hz, meanwhile, in order to ensure pixel potential
It is maintained on set voltage, typically takes the method for the storage capacitance in increase dot structure to keep current potential.Usual feelings
Under condition, the area of two metal levels will be increased for increase storage capacitance, and then cause the area increase in light tight area, cause panel
Aperture opening ratio it is lower, have a strong impact on the display effect of product.In addition, it is illustrated in figure 2 the display shape of viewing area in the prior art
State schematic diagram, black region are lightproof area, and white portion is transmission region, because the area of storage capacitance pole plate is larger, are made
More concentrated into light tight region so that there is obvious grid sense viewing area, reduces the visual experience of user.
The content of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, to solve in the prior art
Viewing area has the technical problem of obvious grid sense.
A kind of array base palte provided in an embodiment of the present invention, including：
A kind of array base palte provided in an embodiment of the present invention, including：
Substrate, multi-strip scanning line and data wire are provided with the substrate；The a plurality of scan line and data wire intersect limit
Fixed multiple dot structures；
Bucking electrode, positioned at the dot structure an at least lateral edges and be located at same layer with the scan line；
The bottom crown of storage capacitance, the bottom crown of the storage capacitance and the scan line are located at same layer, and described deposit
Bucking electrode described in the bottom crown at least multiplexing part that storing up electricity is held；
First insulating barrier, cover the layer where the storage capacitance bottom crown；
The top crown of storage capacitance, it is arranged on first insulating barrier, and with the data line bit in same layer；
The top crown of the storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance；
The dot structure is divided in the top crown of the storage capacitance part overlapping with the bottom crown of the storage capacitance
It is cut at least two transparent areas.
The embodiment of the present invention provides a kind of display device, including the array base palte described in the claims, and with institute
State the opposite substrate that array base palte is oppositely arranged.
The embodiment of the present invention provides a kind of preparation method of array base palte, including：
One substrate is provided；
The bottom crown of scan line, bucking electrode and storage capacitance, the lower pole of the storage capacitance are formed over the substrate
Plate, bucking electrode and scan line are located at same layer, and electricity is shielded described in the bottom crown of the storage capacitance at least multiplexing part
Pole；
The first insulating barrier is formed, covers the layer where the bottom crown of the storage capacitance；
The top crown and data wire of storage capacitance, the top crown of the storage capacitance are formed on first insulating barrier
With the data line bit in same layer；
The scan line is intersected with the data wire limits multiple dot structures；
The top crown of the storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance；The storage
The dot structure is divided at least two printing opacities by the top crown of the electric capacity part overlapping with the bottom crown of the storage capacitance
Area.
The embodiment of the present invention provides a kind of array base palte, has multiple dot structures on the substrate of the array base palte；Shielding electricity
Pole, bottom crown and the scan line of storage capacitance are located at the bottom crown multiplexing part bucking electrode of same layer storage capacitance；First is exhausted
Layer where edge layer covering storage capacitance bottom crown；The top crown of storage capacitance is arranged on first insulating barrier, and with number
It is located at same layer according to line, the top crown of storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance, and this is heavy
Dot structure is divided at least two transparent areas by folded part.The embodiment of the present invention passes through to the shape of storage capacitance is carried out
Change, transparent area is divided at least two transparent areas, has disperseed light tight area, so as to effectively prevent due to large area not
Grid sense problem caused by transparent area.
Brief description of the drawings
Fig. 1 is dot structure schematic diagram in the prior art；
Fig. 2 is the dispaly state schematic diagram of viewing area in the prior art；
Fig. 3 is a dot structure schematic diagram on array base palte provided in an embodiment of the present invention；
Fig. 4 is along the cross section structure diagram in AA ' sections in Fig. 3；
Fig. 5 is the dispaly state schematic diagram of array base palte viewing area provided in an embodiment of the present invention；
Fig. 6 is a kind of display device schematic diagram provided in an embodiment of the present invention；
Fig. 7 is a kind of schematic flow sheet of the preparation method of array base palte provided in an embodiment of the present invention；
Fig. 8 is the preparation method particular flow sheet of array base palte provided in an embodiment of the present invention；
Fig. 9 is the first patterned metal layer schematic diagram of the embodiment of the present invention；
Figure 10 is the dot structure schematic diagram that the embodiment of the present invention forms the second patterned metal layer；
Figure 11 is the second patterned metal layer schematic diagram of the embodiment of the present invention.
Embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, the present invention is made below in conjunction with accompanying drawing into
One step it is described in detail, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole implementation
Example.Based on the embodiment in the present invention, what those of ordinary skill in the art were obtained under the premise of creative work is not made
All other embodiment, belongs to the scope of protection of the invention.
Include multiple dot structures on the array base palte that the embodiment of the present invention is provided, for ease of becoming apparent from specifically understanding
The present invention, mainly illustrated below by taking a dot structure on array base palte as an example.
Fig. 3 is a dot structure schematic diagram on array base palte provided in an embodiment of the present invention, and Fig. 4 is along AA ' in Fig. 3
The cross section structure diagram in section.Below in conjunction with embodiments of the invention are illustrated shown in Fig. 3 and 4, because Fig. 4 is AA ' sections
Cross section structure diagram, therefore the part-structure on array base palte not figure 4 illustrates.
Array base palte provided in an embodiment of the present invention includes：
Substrate 301, multi-strip scanning line 302a and data wire 305b are provided with substrate 301；Multi-strip scanning line 302a sums
Intersect according to line 305b and limit multiple dot structures；
Bucking electrode 302b, positioned at dot structure an at least lateral edges and be located at same layer with scan line 302a；
The bottom crown 302c of storage capacitance, it is located at same layer with scan line 302a, and the bottom crown 302c of storage capacitance is extremely
Few multiplexing part bucking electrode 302b；
First insulating barrier 303, cover the layer where the storage capacitance bottom crown；
The top crown 305a of storage capacitance, it is arranged on first insulating barrier 303, and is located at the data wire 305b
Same layer；
The top crown 305a of the storage capacitance at least has the part overlapping with the bottom crown 302c of the storage capacitance；
Part overlapping with the bottom crown of the storage capacitance top crown 305a of the storage capacitance is by the pixel knot
Structure is divided at least two transparent areas.
With reference to reference to figure 3 and Fig. 4, specifically, array base palte provided in an embodiment of the present invention is made up of different Rotating fields,
Specifically it may include：Substrate 301, the first patterned metal layer 302 is provided with substrate 301, the first patterned metal layer 302 wraps
Include：Scan line 302a, bucking electrode 302b, the bottom crown 302c of storage capacitance；Bucking electrode 302b is located at the four of dot structure
Circumferential edges in the present embodiment, show that bucking electrode is located at edge situation, it is necessary to explanation, but in the present invention
Other embodiments in, can not regard this as a limit, for example, bucking electrode can also be any at least positioned at dot structure
One lateral edges.The bottom crown 302c of storage capacitance is included positioned at the part at dot structure edge and among dot structure
The part in region, wherein, the fractional reuse partly shielding effect electrode 302b positioned at dot structure edge, i.e. part are located at dot structure
First patterned metal layer 302 at edge, both as bucking electrode, while also serves as the bottom crown of storage capacitance；First pattern
Change and be provided with the first insulating barrier 303 on metal level 302, semiconductor layer 304, semiconductor layer 304 are provided with the first insulating barrier 303
On be provided with the second patterned metal layer 305, the second patterned metal layer 305 includes：The top crown 305a sums of storage capacitance
According to line 305b；The top crown 305a of storage capacitance at least has the part overlapping with the bottom crown 302c of the storage capacitance, should
Dot structure is divided into transparent area p1 and transparent area p2 by overlapping part；Second is provided with second patterned metal layer 305
Insulating barrier 306, transparency conducting layer 307 is provided with the second insulating barrier 306, the transparency conducting layer 307 includes pixel electrode 307a,
The pixel electrode 307a and top crown 305a of storage capacitance is electrically connected with.
As shown in figure 3, the top crown 305a of the storage capacitance and bottom crown 302c of storage capacitance weights in the embodiment of the present invention
Folded part is I-shaped pattern；The I-shaped pattern is set in the same direction with data wire 305b, i.e., in I-shaped pattern
Two horizontal lines up and down be arranged in parallel with scan line 302a, middle vertical line be arranged in parallel with data wire 305b.Due to depositing
The top crown 305a that storing up electricity is held and data wire 305b is located at same layer, using such I-shaped design, may be such that and deposits
Appropriately distance is maintained between top crown 305a and data wire 305b that storing up electricity is held, so as to avoid the phenomenon of short circuit.
In the embodiment of the present invention, the part that the top crown 305a of storage capacitance is overlapping with the bottom crown 302c of storage capacitance is
I-shaped pattern, so as to which the transparent area of dot structure is divided into transparent area p1 and transparent area p2, with only having in the prior art
One transparent area is compared, and light tight area has been disperseed in the embodiment of the present invention, light tight due to large area so as to effectively prevent
Grid sense problem caused by area.Also, in the embodiment of the present invention, due to being multiplexed bucking electrode 302b and pole under storage capacitance
Plate 302c, it is not necessary to bucking electrode and storage capacitance bottom crown is fabricated separately, it is possible to reduce the first patterned metal layer on substrate
Area shared by 302, reduces light tight region, increases the aperture opening ratio of pixel.As shown in figure 5, black region is shading region
Domain, white portion are transmission region, because the upper bottom crown of storage capacitance is into I-shaped pattern, has disperseed lightproof area, have adopted
During display, grid sense substantially makes moderate progress the array base palte provided with the embodiment of the present invention, and reduces not
The area of transmission region, add substrate transmitance.
In the embodiment of the present invention, it is not specifically limited for transparent area p1 and transparent area p2 size, the two can be with
Equal or unequal, i.e. area, transparent area p1 area of the transparent area p1 area equal to transparent area p2 is slightly larger than transparent area p2
Area or transparent area p2 area all may be used slightly larger than transparent area p1 area.Preferably, transparent area p1 area and transparent area
Transparent area, is so just evenly distributed by p2 area equation, can further improve user while grid sense is eliminated
Visual experience.
In the embodiment of the present invention, portion overlapping with the bottom crown 302c of storage capacitance the top crown 305a for storage capacitance
Divide and be divided into the number of transparent area to be not specifically limited the transparent area of dot structure.Only specifically listed in above-described embodiment
Part overlapping with the bottom crown 302c of storage capacitance the top crown 305a of storage capacitance is into I-shaped pattern, and by pixel knot
The transparent area of structure is divided into the situation of two transparent areas.Alternatively, the lower pole of the top crown 305a of storage capacitance and storage capacitance
Part overlapping plate 302c also can be intoNow, the transparent area of dot structure is divided into three transparent areas；Or storage
Part overlapping with the bottom crown 302c of storage capacitance the top crown 305a of electric capacity also can be intoNow, dot structure is saturating
Light area is divided into four transparent areas.
It is preferred that the dot structure in the embodiment of the present invention also includes at least one grid being connected with the scan line,
And electrically connected with source electrode of the data line bit in same layer and drain electrode, storage capacitance top crown with drain electrode.As shown in Figure 3 and Figure 4,
First patterned metal layer 302 also includes：Two grids, respectively first grid g1 and second grid g2, the first insulating barrier 303
Upper and first grid g1 and second grid g2 is correspondingly arranged on two semiconductor layers being separated from each other 304.Second pattern metal
Layer 305 also includes：First source electrode s1, the second source electrode s2, the first drain electrode d1, the second drain electrode d2, wherein the first source electrode s1 and data
Line 305b is electrically connected, and the first drain electrode d1 is electrically connected with the second source electrode s1, and the second drain electrode is connected with pixel electrode point.Using the double grid
Configuration thin film transistor, the breadth length ratio of thin film transistor (TFT) can be reduced, reduce leakage current.The present invention does not limit gate data,
I.e. in some embodiments of the invention, single grid structure can be individually used, can also use multi-gate structure.
The embodiment of the present invention provides a kind of array base palte, and multi-strip scanning line and data are provided with the substrate of the array base palte
Line；Multi-strip scanning line and data line, which is intersected, limits multiple dot structures；Bucking electrode, the bottom crown of storage capacitance and scan line position
In same layer, and bucking electrode is located at an at least lateral edges for dot structure, and the bottom crown of storage capacitance is located at dot structure side
The part intermediate region of edge and dot structure, the bottom crown multiplexing part positioned at the storage capacitance at dot structure edge shield electricity
Pole；Layer where first insulating barrier covering storage capacitance bottom crown；The top crown of storage capacitance is arranged on first insulating barrier
On, and with data line bit in same layer, the top crown of storage capacitance is at least with overlapping with the bottom crown of the storage capacitance
Dot structure is divided at least two transparent areas by part, the overlapping part.The embodiment of the present invention passes through to by storage capacitance
Shape be changed, transparent area is divided at least two transparent areas, has disperseed light tight area, so as to effectively prevent due to
Grid sense problem caused by the light tight area of large area, also, in the embodiment of the present invention, due to being multiplexed bucking electrode with depositing
Storing up electricity holds pole plate, it is not necessary to bucking electrode and storage capacitance bottom crown is fabricated separately, it is possible to reduce the first patterning on substrate
Area shared by metal level, reduces light tight region, increases the aperture opening ratio of pixel..
Fig. 6 is a kind of display device schematic diagram provided in an embodiment of the present invention, including the array base described in above-described embodiment
Plate 601, and the opposite substrate 602 being oppositely arranged with the array base palte.
Further, the display device also includes being arranged at the reflection that the array base palte deviates from the opposite substrate side
Piece 603.
Array base palte described in the embodiment of the present invention can be thin film transistor (TFT) (Thin Film Transistor, TFT)
Array base palte, the opposite substrate being oppositely arranged with the array base palte can be colored filter substrate (Color filter,
CF), liquid crystal layer, alignment film etc. are provided between colored filter substrate and thin-film transistor array base-plate.
Schematic flow sheets of the Fig. 7 corresponding to a kind of preparation method of array base palte provided in an embodiment of the present invention, the party
Method comprises the following steps 701 to step 704：
Step 701 a, there is provided substrate；
Step 702, the bottom crown of scan line, bucking electrode and storage capacitance, the storage electricity are formed over the substrate
Bottom crown, bucking electrode and the scan line of appearance are located at same layer, and the bottom crown of the storage capacitance at least multiplexing part institute
State bucking electrode；
Step 703, the first insulating barrier is formed, covers the layer where the bottom crown of the storage capacitance；
Step 704, the top crown and data wire of storage capacitance, the storage capacitance are formed on first insulating barrier
Top crown and the data line bit in same layer；The scan line is intersected with the data wire limits multiple dot structures；
The top crown of the storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance；The storage
The dot structure is divided at least two printing opacities by the top crown of the electric capacity part overlapping with the bottom crown of the storage capacitance
Area.
The preparation method for the array base palte that the embodiment of the present invention is provided can also be used for the making of other kinds of display
In, in manufacturing process, by the bottom crown multiplexing part bucking electrode of storage capacitance, and cause the top crown of storage capacitance with depositing
Dot structure is divided at least two transparent areas by the part that the bottom crown of storing up electricity appearance is overlapping, the battle array for making to obtain by this method
Row substrate effectively prevent grid sense problem caused by the light tight area of large area storage capacitance, also, the embodiment of the present invention
In, due to being multiplexed bucking electrode and storage capacitance bottom crown, it is not necessary to bucking electrode and storage capacitance bottom crown is fabricated separately,
The area shared by the first patterned metal layer on substrate can be reduced, reduces light tight region, increases the aperture opening ratio of pixel.
To further understand the embodiment of the present invention, the preparation method described in the embodiment of the present invention is carried out with reference to Fig. 8
Illustrate.
Step 801 a, there is provided substrate 301, the first metal layer is formed on the substrate 301；The first metal layer is by grid
Pole metallic film is prepared using the method for magnetron sputtering, and electrode material can enter according to different device architecture and technological requirement
Row selection, usual adopted grid line metal have a Mo, Mo-Al-Mo alloys, Mo/Al-Nd/Mo build up the electrode of structure, Cu and
Titanium and its alloy etc..
Step 802, technique is patterned to the first metal layer by way of wet etching, forms the first pattern metal
Layer 302, as shown in figure 9, being the schematic diagram of the first patterned metal layer 302, first patterned metal layer 302 includes：Scan line
302a, bucking electrode 302b and storage capacitance bottom crown 302c；The bottom crown 302c at least multiplexing parts of the storage capacitance
The bucking electrode 302b；
Step 803, the first insulating barrier 303 is formed on the first patterned metal layer 302, cleans, passes through before technique film forming
Plasma reinforced chemical vapor deposition (PECVD) method, insulating barrier is prepared on the first patterned metal layer, its materials application ratio
It is wide, such as silica (SiO2) film, silicon nitride film (SiNx), silicon oxynitride film (SiOxNy), aluminum oxide
(Al2O3) film of film, TiOx films and compound sandwich construction.Then the first insulating barrier 303 is surface-treated.
Step 804, two semiconductor layers 304 being separated from each other are formed on the first insulating barrier 303, as shown in figure 9, two
The semiconductor layer 304 being separated from each other is formed in the position corresponding with two grids.
Step 805, second metal layer is formed by magnetron sputtering on semiconductor layer 304, and second metal layer is carried out
Wet etching patterning processes, the second patterned metal layer 305 is formed, as shown in Figure 10, to form the picture of the second patterned metal layer 305
Plain structural representation.To be more clearly understood that the shape and structure of the second patterned metal layer 305, reference can be made to Figure 11, Tu11Wei
The schematic diagram of second patterned metal layer 305, the top crown 305a of second patterned metal layer 305 including storage capacitance and
Data wire 305b.
On array base palte in the embodiment of the present invention, multi-strip scanning line 302a and data wire 305b, which intersects, limits multiple pixels
Structure；The top crown 305a of storage capacitance at least has the part overlapping with the bottom crown 302c of the storage capacitance；Storage electricity
The dot structure is divided at least two by the part that the top crown 305a of appearance is overlapping with the bottom crown 302c of the storage capacitance
Individual transparent area.
Further, the preparation method of array base palte also includes：
Step 806, the second insulating barrier 306 is formed in second metal layer, and carries out the etching technics of via, the via of formation
V1, as shown in figure 3, being the dot structure schematic diagram of array base palte of the embodiment of the present invention, via v1 is used for the picture that will be formed afterwards
Plain electrode 307a is electrically connected with drain electrode d2.
Step 807, pixel electrode layer 908 is formed over the second dielectric, and it is carried out by the method for wet etching
Patterning processes, the indium tin oxide that the material of pixel electrode layer 908 widely uses now, ultimately form a complete pixel knot
Structure, as shown in Figure 3 above.
It should be noted that the embodiment of the present invention exemplified by a kind of array base palte of typical bottom-gate type configuration only by having
Body illustrates the manufacturing process of array base palte, and the array base palte of other structures can also pass through the method for embodiment of the embodiment of the present invention
Made.The embodiment of the present invention is in manufacturing process, by the bottom crown multiplexing part bucking electrode of storage capacitance, and to deposit
Dot structure is divided at least two transparent areas by the part that the top crown of storing up electricity appearance is overlapping with the bottom crown of storage capacitance, is passed through
The array base palte that this method makes to obtain effectively prevent grid sense problem caused by the light tight area of large area storage capacitance,
Also, in the embodiment of the present invention, due to being multiplexed bucking electrode and storage capacitance bottom crown, it is not necessary to bucking electrode is fabricated separately
With storage capacitance bottom crown, it is possible to reduce the area on substrate shared by the first patterned metal layer, reduce light tight region, increase
The big aperture opening ratio of pixel.
It can be seen from the above：The embodiment of the present invention provides a kind of array base palte, is set on the substrate of the array base palte
It is equipped with multi-strip scanning line and data wire；Multi-strip scanning line and data line, which is intersected, limits multiple dot structures；Bucking electrode, storage electricity
The bottom crown of appearance is located at same layer with scan line, and bucking electrode is located at an at least lateral edges for dot structure, storage capacitance
Bottom crown is located at the part intermediate region of dot structure edge and dot structure, the storage capacitance positioned at dot structure edge
Bottom crown multiplexing part bucking electrode；Layer where first insulating barrier covering storage capacitance bottom crown；The top crown of storage capacitance
It is arranged on first insulating barrier, and with data line bit in same layer, the top crown of storage capacitance at least has to be deposited with described
The overlapping part of bottom crown that storing up electricity is held, dot structure is divided at least two transparent areas by the overlapping part.It is of the invention real
Example is applied by the shape of storage capacitance being changed, transparent area being divided into at least two transparent areas, disperseed light tight
Area, so as to effectively prevent the grid sense problem caused by the light tight area of large area.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into having altered and changing for the scope of the invention.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
1. a kind of array base palte, including：
Substrate, multi-strip scanning line and data wire are provided with the substrate；It is more that a plurality of scan line and data wire intersect restriction
Individual dot structure；
Bucking electrode, positioned at the dot structure an at least lateral edges and be located at same layer with the scan line；
The bottom crown of storage capacitance, the bottom crown of the storage capacitance are located at same layer, and the storage electricity with the scan line
Bucking electrode described in the bottom crown of appearance at least multiplexing part；
First insulating barrier, cover the layer where the storage capacitance bottom crown；
The top crown of storage capacitance, it is arranged on first insulating barrier, and with the data line bit in same layer；
The top crown of the storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance；
The dot structure is divided into by the top crown of the storage capacitance part overlapping with the bottom crown of the storage capacitance
At least two transparent areas；
Wherein, the dot structure is the dot structure being controlled by a thin film transistor (TFT).
2. array base palte as claimed in claim 1, it is characterised in that the top crown of the storage capacitance and the storage capacitance
Bottom crown overlapping part the dot structure is divided into two transparent areas.
3. array base palte as claimed in claim 2, it is characterised in that the area equation of described two transparent areas.
4. array base palte as claimed in claim 1, it is characterised in that the top crown of the storage capacitance and the storage capacitance
The overlapping part of bottom crown be I-shaped pattern；The I-shaped pattern is set in the same direction with the data wire.
5. array base palte as claimed in claim 1, it is characterised in that also include：
Second insulating barrier, cover the top crown of the storage capacitance；
Pixel electrode, cover second insulating barrier；The pixel electrode and the top crown of the storage capacitance are electrically connected with.
6. such as the array base palte any one of claim 1-5, it is characterised in that the dot structure also includes at least one
The individual grid being connected with the scan line, and with source electrode of the data line bit in same layer and drain electrode, the storage capacitance
Top crown electrically connects with the drain electrode.
7. array base palte as claimed in claim 6, it is characterised in that the number of the grid is two, first insulation
On layer two semiconductor layers being separated from each other are correspondingly arranged on described two grids.
A kind of 8. display device, it is characterised in that including the array base palte any one of the claims 1-7, and with
The opposite substrate that the array base palte is oppositely arranged.
9. display device as claimed in claim 8, it is characterised in that also include being arranged at the array base palte away from described right
To the reflector plate of substrate side.
A kind of 10. preparation method of array base palte, it is characterised in that including：
One substrate is provided；
The bottom crown of scan line, bucking electrode and storage capacitance, bottom crown, the screen of the storage capacitance are formed over the substrate
Cover electrode and scan line is located at same layer, and bucking electrode described in the bottom crown of the storage capacitance at least multiplexing part；
The first insulating barrier is formed, covers the layer where the bottom crown of the storage capacitance；
The top crown and data wire of storage capacitance, the top crown of the storage capacitance and institute are formed on first insulating barrier
Data line bit is stated in same layer；
The scan line is intersected with the data wire limits multiple dot structures；
The top crown of the storage capacitance at least has the part overlapping with the bottom crown of the storage capacitance；The storage capacitance
The top crown part overlapping with the bottom crown of the storage capacitance dot structure is divided at least two transparent areas；
Wherein, the dot structure is the dot structure being controlled by a thin film transistor (TFT).
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| CN201410836490.9A CN104503164B (en) | 2014-12-23 | 2014-12-23 | A kind of array base palte and preparation method thereof, display device |
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| CN105977262B (en) * | 2016-05-27 | 2019-09-20 | 深圳市华星光电技术有限公司 | A kind of display device, array substrate and its manufacturing method |
| US10191345B2 (en) * | 2016-11-01 | 2019-01-29 | Innolux Corporation | Display device |
| CN111338142B (en) * | 2020-04-10 | 2022-09-06 | 成都京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
| CN112992931B (en) * | 2021-02-04 | 2022-11-15 | 厦门天马微电子有限公司 | Array substrate mother board, array substrate, display panel and display device |
| CN116661202A (en) * | 2022-02-18 | 2023-08-29 | 成都中电熊猫显示科技有限公司 | Array substrate and display device |
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|---|---|---|---|---|
| TW483173B (en) * | 2001-02-19 | 2002-04-11 | Au Optronics Corp | Thin film transistor array structure |
| CN101493619A (en) * | 2008-01-25 | 2009-07-29 | 三星电子株式会社 | Display substrate, method of manufacturing the same and display panel having the display substrate |
| CN102109718A (en) * | 2009-12-29 | 2011-06-29 | 上海天马微电子有限公司 | Pixel structure and thin film transistor array substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8665192B2 (en) * | 2009-07-08 | 2014-03-04 | Hitachi Displays, Ltd. | Liquid crystal display device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW483173B (en) * | 2001-02-19 | 2002-04-11 | Au Optronics Corp | Thin film transistor array structure |
| CN101493619A (en) * | 2008-01-25 | 2009-07-29 | 三星电子株式会社 | Display substrate, method of manufacturing the same and display panel having the display substrate |
| CN102109718A (en) * | 2009-12-29 | 2011-06-29 | 上海天马微电子有限公司 | Pixel structure and thin film transistor array substrate |
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