JP2000356858A - Array substrate for display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to improve the accuracy and reliability of the alignment of mask patterns and patterns already formed on an array substrate and to prevent the degradation in a production yield and product defect by the failure and error of the alignment of the mask patterns. SOLUTION: Dot marks 21 of an upper layer are so formed as to be stacked on the dot marks 11 of a lower layer formed simultaneously with gate electrodes 11a via a gate insulating film 15, etc. The dot marks 21 of the upper layer are formed in a self-alignment manner with the dot marks 11 of the lower layer by a rear surface exposure technique with the dot marks 11 of the lower layer as a mask at the time of formation of a channel protective film 22 of TFTs(thin-film transistors) 45. The interference of light and the negation of the light in the multilayered films are prevented at the time of position detection of the alignment marks 1 using a laser beam by the presence of the dot marks 11 of the upper layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a display device used for a flat display device such as a liquid crystal display device, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, flat display devices replacing CRT displays have been actively developed. Among them, liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thinness, and low power consumption.

[0003] For example, a light-transmitting active-matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. The active matrix type liquid crystal display device has a configuration in which a liquid crystal layer is held between an array substrate and a counter substrate via an alignment film. In the array substrate, a plurality of signal lines and scanning lines are arranged in a grid on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) is provided at each intersection. (Hereinafter abbreviated as TFT) using a semiconductor thin film of the above. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to a transparent conductive material constituting the pixel electrode, for example, ITO (Indium-Tin-Oxide). Have been.

[0004] The opposing substrate is configured such that an opposing electrode made of ITO is disposed on a transparent insulating substrate such as glass, and a color filter layer is disposed for realizing color display.

An example of a conventional method for manufacturing an array substrate for a display device will be described with reference to FIGS.

(1) First Step (Formation of Gate Electrode 11a and Dot Mark 11) A metal thin film is deposited on an insulating substrate 14 such as glass by sputtering or the like, and a predetermined wiring is formed using a first mask pattern. Is patterned. As a result, the gate electrode 11a and the scanning line are formed in the pixel region, and the dot mark 11 is formed on the periphery of the substrate (FIG. 12).

(2) Second Step (Continuous Deposition of Gate Insulating Film 15 and the Like) After the first step, a gate insulating film (SiON) composed of a silicon oxide film, a silicon nitride film, or a lamination thereof is formed by plasma CVD or the like. Film 15 and amorphous silicon (a-
An Si: H) film 16 and a silicon nitride film 17 are continuously formed.

(3) Third Step (Formation of Channel Protective Film 22) Using a second mask pattern, a silicon nitride film (SiN
By patterning the (x film) 17, an island-shaped channel protective film 22 is formed above the gate electrode 11a (FIG. 13). At this time, the second mask pattern and the pattern such as the gate electrode 11a on the array substrate are aligned (aligned) using the dot marks 11.
At this time, irradiation of a laser beam and measurement of light returning from the dot mark 11 are performed by the upper alignment microscope. More specifically, the measurement is performed on the laser light diffracted by the step surface forming the contour of the dot mark 11.

(4) Fourth Step After depositing a phosphorus-doped amorphous silicon (a-Si: H) film 25, an island-shaped semiconductor active layer is formed at the TFT by patterning using a third mask pattern. I do. At this time, the alignment between the third mask pattern and the pattern on the array substrate is performed using the dot marks 11 as in the third step.

However, a gate insulating film 15, an amorphous silicon film 16, and a phosphorus-doped amorphous silicon film 25 are deposited on the dot mark 11, and a resist layer 7 is formed.
Is applied (FIG. 14). Therefore, when the position of the dot mark 11 is detected by the alignment microscope, the light diffracted from the dot mark 11 may be weakened by interfering with the light reflected on the interface between the films and the upper surface of the multilayer film. is there. Depending on the combination of the refractive index and the reflectance of the deposited multilayer film and the resist layer, they interfere with the diffracted light from the dot mark 11 and cancel.

Therefore, the intensity of the signal obtained by the alignment microscope becomes weak, which causes a measurement error of the alignment position and a deviation of the exposure position. In some cases, the alignment operation itself may not be performed because the required signal strength cannot be obtained or the signal waveform itself cannot be obtained. That is, a situation may occur in which the exposure operation itself for patterning cannot be performed.

(5) Subsequent Steps After this fourth step, pixel electrodes, contact holes, signal lines, source / drain electrodes, and the like are sequentially formed. A similar problem arises.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the above problem. In an array substrate such as a liquid crystal display device and a method of manufacturing the same, a mask pattern and a pattern already formed on the array substrate are provided. To improve the accuracy and reliability of alignment with the mask pattern, and prevent a reduction in manufacturing yield and a product defect due to a misalignment or an error of the mask pattern.

[0014]

According to a first aspect of the present invention, there is provided an array substrate for a display device having an alignment mark for performing alignment with a mask pattern. It is characterized by comprising a lower layer mark and an upper layer mark provided so as to match the lower layer mark.

According to the above configuration, the accuracy and reliability of the alignment between the mask pattern and the pattern already formed on the array substrate can be remarkably improved, and the manufacturing yield due to the misalignment or error of the mask pattern can be improved. Can be prevented from lowering and product defects.

According to a second aspect of the present invention, in a method of manufacturing an array substrate for a display device, a lower layer mark is formed in one patterning, and an upper layer mark is aligned with the upper layer mark in a subsequent patterning. In the subsequent patterning, using an alignment mark in which the lower layer mark and the upper layer mark are overlapped, a pattern already formed on the insulating substrate, a mask pattern for photolithography Is performed.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
9 will be described.

<Basic Configuration of Array Substrate> First, FIG. 1 schematically shows a configuration of a main part of an array substrate according to an embodiment. The array substrate of the embodiment is used for a light-transmitting liquid crystal display device of a TFT system.

A plurality of alignment marks 1 are arranged on the periphery of the array substrate 10. The alignment mark 1 is used for aligning the mask pattern with the substrate when the array substrate 10 is manufactured. As shown in FIG. 1, the alignment mark 1 is formed by superposing a dot mark 11 in a lower layer and a dot mark 21 in the upper layer, which is substantially the same shape and slightly smaller in size.

The dot mark 11 in the lower layer is
And is made of the same material in the same step as the gate electrode 11a of the TFT 45 in FIG. On the other hand, the upper dot mark 2
1 is made of the same material in the same step as the channel protective film 22 of the TFT 45. As will be described in detail below, the upper dot mark 21 is formed by patterning the protective film layer in a self-aligned manner (in a self-aligned manner) with respect to the lower dot mark 11 by a backside exposure technique.

<Manufacturing Process of Array Substrate> Next, a manufacturing process of the array substrate 10 of the embodiment will be described with reference to FIGS.

(1) First Step (FIG. 2, Preparation of Lower Layer Dot Mark 11 and Gate Electrode 11a) A molybdenum-tungsten alloy (Mo.
W) is deposited to a thickness of 200 nm. Then, after applying a resist layer on the metal thin film, a resist pattern is formed by exposure, development and patterning using the first mask pattern. Next, by performing etching,
A gate electrode 11a, a scanning line 11b integrated with the gate electrode 11a, and an auxiliary capacitance line are formed in the pixel region, and a rectangular island-shaped dot mark 11 is formed on the periphery of the substrate.

The photolithography process using the first mask pattern is performed by a first patterning,
Or, it is called “1 PEP”. FIG. 2 schematically shows a state after the first patterning.

(2) Second Step (Continuous Film Formation by Plasma CVD) After the first step, the glass substrate is heated and the atmospheric pressure plasma CV
After depositing a silicon oxide film (SiOx film) by the D method, a silicon nitride film (Si
An Nx film is deposited to form a gate insulating film 15 composed of a two-layer film. Subsequently, an amorphous silicon film (a-Si: H) 16 for forming the semiconductor active layer 32 of the TFT 45 and a silicon nitride film 1 for forming the channel protection film 22 of the TFT 45 by a low pressure plasma CVD method.
7 are continuously formed without exposure to the atmosphere. Such a continuous film formation layer is referred to as “2PEP film formation layer”.

(3) Third Step (FIGS. 3-4, Preparation of Upper Layer Dot Mark 21 and Channel Protective Film 22) After the second step, a resist layer is applied again. Then, the front side (the upper side in the figure) using the second mask pattern 52
And exposure from the back side using the metal pattern such as the lower dot mark 11 and the gate electrode 11a as a mask. Here, the second mask pattern 52 is provided with a metal light shielding layer 51 covering the vicinity of the dot mark 11 and a metal light shielding layer 52a corresponding to the location of the TFT 45, as shown in FIG.

A resist pattern is formed by such an exposure operation, development and patterning. Next, by performing etching, the island-shaped channel protection film 22 is formed at each of the TFTs 45, and the rectangular island-shaped dot marks 11 are formed at the periphery of the substrate.

Such a series of photolithography steps using the second mask pattern is called a second patterning or "2PEP". FIG. 4 schematically shows a state after the 2PEP film-formed layer is patterned in this manner.

(4) Fourth step (FIGS. 5 and 6, n ⁺ a-Si:
Deposition of H and patterning thereof) After the third step, a phosphorus-doped amorphous silicon layer containing phosphorus as an impurity (n ⁺ a-
(Si: H) 25 is deposited.

A resist layer is applied thereon again, and a resist pattern is formed by exposure using the third mask pattern 53, development and patterning.

At this time, the alignment microscope 6
By catching the alignment mark 1 on the array substrate 10, precise alignment between the pattern already formed on the array substrate 10 and the mask pattern 53 is performed.
Such alignment is performed similarly in the second patterning and also in subsequent patterning (exposure, development, and etching using a mask pattern).

The alignment microscope 6 irradiates a laser beam from immediately above the area where the alignment marks 1 are arranged, and measures the light returning to the alignment microscope 6 by a photoelectric conversion element (CCD). Detect the position. More specifically, the position of the dot mark 11 is determined by capturing the light that is diffracted by the laser light on the step surface forming the contour of the lower dot mark 11 and the end face forming the contour of the dot mark 21 of the upper layer and returns upward. Is detected.

When positioning the array substrate 10 with respect to the third mask pattern, a plurality of films are deposited on the lower dot mark 11, but these films are deposited due to the presence of the upper dot mark 21. Light interference and cancellation caused by the film can be sufficiently prevented. Therefore, a very sharp signal waveform can be obtained by the CCD of the alignment microscope 6, and the alignment mark 1
In this case, the position detection accuracy, and the positioning accuracy of the mask pattern can be significantly improved. For this,
This will be further described with reference to FIGS.

By performing etching after the formation of the resist pattern described above, at locations other than the TFT 45,
The amorphous silicon film (a-Si: H) 16 and the phosphorus-doped amorphous silicon layer (n ⁺ a-Si: H) 25 are collectively removed. As a result, an island-like pattern composed of the two layers of the semiconductor active layer 32 and the low-resistance semiconductor layer 33 is formed so as to wrap the channel protection film 22 from above and below at the location of the TFT 45 (third patterning). In FIG.
The state after this patterning is shown. As shown in FIG. 6, the amorphous silicon film 16 remains even at the portion covered by the upper dot mark 21 to form an island-shaped pattern 31.

(5) Subsequent Steps After the fourth step, for example, a step of forming an ITO film so as to cover the pixel region 40, a step of forming a contact hole penetrating the gate insulating film, and a step of patterning the ITO film Forming a pixel electrode 41 by using a source electrode 42;
A step of forming the drain electrode 43 and the signal line 44 and the like are performed. In each of these patterning steps, the positioning of the mask pattern using the alignment mark 1 is repeatedly performed.

<Detection of Position of Alignment Mark> Next, the detection of the position of the alignment mark will be described in detail with reference to FIGS.

FIG. 7 shows a photograph of the array substrate 10 of the embodiment.
2 shows a state in which the alignment marks 1 are arranged in the peripheral portion of FIG. From this photograph, for each alignment mark 1, the outline of the lower-layer dot mark 11 and the outline of the upper-layer dot mark 21 inside it can be confirmed.

In a specific embodiment, the dot mark 11 below each alignment mark 1 is about 10 μm × about 1 μm.
It has a substantially rectangular shape of 0 μm, and the dot mark 21 in the upper layer has a substantially rectangular shape of about 7 μm × about 7 μm.

As shown in FIG.
Are arranged in three rows, and the intervals between the rows are large, while the intervals in the rows are narrow. Also, there is a difference in the interval between the rows, and the first row and the second row are viewed from the upper side of the photograph.
The interval between the second and third columns is 2/3 of the interval between the second and third columns.

The rows of the alignment marks 1 are provided, for example, in the direction along the X axis and the direction along the Y axis of the array substrate 10, respectively. By using such a row of the alignment marks 1, it is possible to detect a positional shift of the pattern on the array substrate in the X-axis direction and the Y-axis direction.

FIG. 8 is a schematic graph for explaining a position detection signal waveform obtained by the alignment microscope 6.

The horizontal axis of this graph is the stage coordinates in the direction crossing the row of the alignment marks 1, and the vertical axis is the intensity of a direct current (DC) signal obtained by photoelectric conversion.
A sharp peak is formed at the row of the alignment mark 1, and the position of the pattern formed on the array substrate 10 can be accurately detected from the position of this peak.

FIG. 9 shows measured data of signal waveforms obtained for detecting the position of 3 PEP in the manufacturing process of the array substrate 10 of the embodiment. The three peaks shown in the figure are:
Each corresponds to a row of the alignment marks 1. As can be seen from the figure, a very large signal intensity of about 10.0 V was obtained, and a very sharp peak was obtained.

FIGS. 10 to 11 show a photograph corresponding to FIG. 7 and a signal waveform data corresponding to FIG. 9 for a comparative example according to the prior art. The comparative example was completely the same as the above example except that the upper layer dot mark 21 was not provided and only the lower layer dot mark 11 was provided.

As shown in FIG. 11, the signal intensity at the peak is as low as about 0.57 V, and the peak is a dull peak split right and left.

As is clear from the comparison between the signal waveform data of FIG. 9 and the signal waveform data of FIG. 11, according to the embodiment of the present invention, the accuracy and reliability of position detection are remarkably improved as compared with the prior art. I was able to. Further, the situation where the position cannot be detected is completely prevented.

Therefore, the third patterning (3PE
In P) and the subsequent patterning step, the accuracy and reliability of the alignment between the mask pattern and the pattern already formed on the array substrate can be remarkably improved. It is possible to almost completely prevent a decrease in manufacturing yield and a product defect.

[0047]

According to the present invention, in an array substrate such as a liquid crystal display device and a method of manufacturing the same, the accuracy and reliability of alignment between a mask pattern and a pattern already formed on the array substrate are remarkably improved. Accordingly, it is possible to prevent a reduction in the production yield and a defective product due to a misalignment or an error in the alignment of the mask pattern.

[Brief description of the drawings]

FIG. 1 is a sectional perspective view schematically showing a main part of an array substrate according to an embodiment.

FIG. 2 is a schematic cross-sectional perspective view corresponding to FIG. 1 and showing a state after a first patterning in the method of manufacturing an array substrate according to the embodiment.

FIG. 3 is a cross-sectional perspective view corresponding to FIG. 1 for describing exposure at the time of second patterning.

FIG. 4 is a cross-sectional perspective view corresponding to FIG. 1 and illustrating a state after a second patterning.

FIG. 5 is a sectional perspective view corresponding to FIG. 1 for describing positioning in third patterning.

FIG. 6 is a sectional perspective view corresponding to FIG. 1 and showing a state after a third patterning.

FIG. 7 is a micrograph of an alignment mark array portion on the array substrate of the example.

FIG. 8 is a schematic graph for explaining a signal waveform obtained by an alignment microscope for detecting the position of an alignment mark.

FIG. 9 is a photograph of a monitor screen showing a position detection signal waveform obtained by a positioning operation for the third patterning according to the example.

FIG. 10 is a micrograph corresponding to FIG. 7, showing an alignment mark array portion on an array substrate of a comparative example.

FIG. 11 shows a position detection signal waveform obtained by a positioning operation for the third patterning according to a comparative example.
3 is a photograph of a monitor screen corresponding to FIG.

FIG. 12 is a schematic longitudinal sectional view showing a state after a first patterning, for describing a conventional array substrate manufacturing method.

FIG. 13 is a schematic longitudinal sectional view showing a state after a second patterning in a conventional array substrate manufacturing method.

FIG. 14 illustrates a conventional method of manufacturing an array substrate.
FIG. 11 is a schematic longitudinal sectional view showing a state of positioning for third patterning.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Self-alignment type alignment mark 10 Array substrate 11 Lower dot mark formed simultaneously with gate electrode 11a Gate electrode 15 Gate insulating film 21 Upper dot mark formed simultaneously with channel protective film 22 Channel protective film 45 TFT

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA29 JA24 JA37 JA41 JA46 JB22 JB31 KA05 MA07 MA12 MA30 NA25 NA29 PA01 PA08 2H097 KA03 KA12 KA13 KA15 KA16 KA22 LA12 5F110 CC07 DD02 EE06 EE37 EE44 FF02 GG03 FF02 GG03 FF02 GG03 FF02 GG02 HK09 HK16 HK25 HK37 HM18 NN03 NN12 NN24 NN35 NN73 QQ02 QQ09 QQ12 QQ30

Claims (5)

[Claims] 1. An array substrate for a display device provided with an alignment mark for performing alignment with a mask pattern, wherein each of the alignment marks is a lower mark, a layer arbitrarily stacked, and a layer stacked on this layer. And an upper layer mark provided so as to be located above the lower layer mark. 2. A method for manufacturing an array substrate for a display device comprising at least three or more steps of film formation and patterning on an insulating substrate, wherein a lower mark is formed in one patterning, and a lower mark is formed on the lower mark. An arbitrary layer is laminated, and in the patterning after the lamination, an upper layer mark is formed so as to be located above the lower layer mark, and in the subsequent patterning, the lower layer mark and the upper layer mark are A method for manufacturing an array substrate for a display device, comprising: performing alignment between a pattern already formed on the insulating substrate and a mask pattern for photolithography by using the aligned alignment marks. 3. The method of manufacturing an array substrate for a display device according to claim 2, wherein said lower layer mark is formed by first patterning, and said upper layer mark is formed by subsequent patterning. 4. The insulating substrate is a transparent insulating substrate, wherein the lower layer mark is made of a light-shielding film, and the upper layer mark is formed on the transparent insulating substrate using a backside exposure technique using the lower layer mark as a mask. 4. The method of manufacturing an array substrate for a display device according to claim 2, wherein the deposition film is formed by patterning the deposited film on the substrate so as to be positioned above the lower mark. 5. The manufacturing of an array substrate for a display device according to claim 2, wherein said upper layer mark is simultaneously formed by film formation and patterning for forming a channel protective film of a thin film transistor in a pixel region. Method.