JPH095786A - Tft array substrate as well as liquid crystal display device formed by using the tft array substrate and production of tft array substrate - Google Patents

Tft array substrate as well as liquid crystal display device formed by using the tft array substrate and production of tft array substrate

Info

Publication number
JPH095786A
JPH095786A JP15486495A JP15486495A JPH095786A JP H095786 A JPH095786 A JP H095786A JP 15486495 A JP15486495 A JP 15486495A JP 15486495 A JP15486495 A JP 15486495A JP H095786 A JPH095786 A JP H095786A
Authority
JP
Japan
Prior art keywords
tft array
electrode
pattern
pixel
metal pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15486495A
Other languages
Japanese (ja)
Inventor
Hirokazu Sakamoto
弘和 阪本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Display Inc
Original Assignee
Advanced Display Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Display Inc filed Critical Advanced Display Inc
Priority to JP15486495A priority Critical patent/JPH095786A/en
Priority to TW085105967A priority patent/TW300341B/zh
Priority to KR1019960018811A priority patent/KR100363140B1/en
Priority to CN96107917A priority patent/CN1105324C/en
Publication of JPH095786A publication Critical patent/JPH095786A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To provide a TFT array with which the sure repair of a dot defect is possible and a process for producing this array. CONSTITUTION: This TFT array substrate has a dot defect repair pattern 11 which is simultaneously formed of the same material as the material of storage capacitance electrodes 2 and overlaps on adjacent two pixels and an island 12 which is formed on this dot defect repair pattern 11 via a storage capacitance dielectric film 3. The transistor part of the pixel recognized to be the spot defect is cut at a C-C line part by a laser beam and thereafter, the D part on the pixel electrode 5 and the D part on the pixel electrode 5 of the adjacent pixel are irradiated with the laser beam, by which the pixel electrodes of the adjacent pixels are shorted via the dot defect repair pattern 11. Two metallic films via the insulating film, i.e., the dot defect repair pattern 11 and the island 12 are connected by the laser and, therefore, the repair is easily and surely executed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、TFTアレイ基板と
その製造方法、特に、歩留まり低下要因の1つである点
欠陥の修復方法を提供するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a TFT array substrate and a method of manufacturing the same, and in particular, a method of repairing a point defect which is one of the factors that reduce the yield.

【0002】[0002]

【従来の技術】[Prior art]

【0003】図9は、従来の液晶表示装置に用いられる
TFTアレイの部分拡大図、図10は図9中のA−A断
面図である。図において、1はガラス基板、2は蓄積容
量電極、3は蓄積容量の誘電体、4はゲート電極を兼ね
備えたゲート配線、5は透明導電膜よりなる画素電極、
6はゲート絶縁膜、7は半導体層、8はオーミックコン
タクト層、9はソース電極を兼ね備えたソース配線、1
0はドレイン電極をそれぞれ示す。
FIG. 9 is a partially enlarged view of a TFT array used in a conventional liquid crystal display device, and FIG. 10 is a sectional view taken along line AA in FIG. In the figure, 1 is a glass substrate, 2 is a storage capacitor electrode, 3 is a storage capacitor dielectric, 4 is a gate wiring also serving as a gate electrode, 5 is a pixel electrode made of a transparent conductive film,
6 is a gate insulating film, 7 is a semiconductor layer, 8 is an ohmic contact layer, 9 is a source wiring also serving as a source electrode, 1
Reference numeral 0 denotes a drain electrode, respectively.

【0004】次に従来のTFTアレイの製造プロセスお
よび構造を説明する。まず、洗浄したガラス基板1にC
r、Ta、Ti等の金属薄膜をスパッタリング法等の方
法で成膜し、これをフォトエッチング法等の方法でパタ
ーン形成し、蓄積容量電極2を形成する。次に、蓄積容
量の誘電体膜3となるSiNやSiO2等の膜をプラズ
マCVD(化学的気相成長)法等で成膜し、後に形成す
るゲート電極およびゲート配線4とコンタクトするため
のコンタクトホール等をパターン形成する。次に、C
r、Ta、Ti等の金属薄膜をスパッタリング法等の方
法で成膜し、これをフォトエッチング法等の方法でパタ
ーン形成し、ゲート電極およびゲート配線4を形成す
る。さらに、ITO(インジウムすず酸化物)等の透明
導電膜をスパッタリング等の方法で成膜し、これをフォ
トエッチング法等の方法でパターン形成し、画素電極5
を形成する。
Next, the manufacturing process and structure of a conventional TFT array will be described. First, C on the washed glass substrate 1
A metal thin film of r, Ta, Ti or the like is formed by a method such as a sputtering method, and this is patterned by a method such as a photoetching method to form the storage capacitor electrode 2. Next, a film of SiN, SiO 2 or the like to be the dielectric film 3 of the storage capacitor is formed by a plasma CVD (chemical vapor deposition) method or the like, and a gate electrode and a gate wiring 4 to be formed later are contacted. A contact hole or the like is patterned. Then C
A metal thin film of r, Ta, Ti or the like is formed by a method such as a sputtering method, and this is patterned by a method such as a photoetching method to form the gate electrode and the gate wiring 4. Further, a transparent conductive film such as ITO (Indium Tin Oxide) is formed by a method such as sputtering, and this is pattern-formed by a method such as a photo etching method.
To form

【0005】次に、ゲート絶縁膜6となるSiNやSi
2等の絶縁膜、半導体層7となるi−a−Siや、p
oly−Si等、およびオーミックコンタクト層8とな
るn−a−Si等をプラズマCVD法等で成膜する。次
に、フォトエッチング法等の方法でn−a−Siおよび
i−a−Siをアイランド状もしくはライン状にパター
ン形成する。次に、フォトエッチング法等の方法でパタ
ーン形成し、画素電極5上にコンタクトホールを形成す
る。さらに、Al、Cr等の金属薄膜をスパッタリング
法等で成膜し、これをフォトエッチング法等でパターン
形成し、ソース電極およびソース配線9およびドレイン
電極10を形成後、ソース・ドレイン間にあるn−a−
Siをエッチオフする。最後に、必要に応じてSiN等
で保護膜を形成する。
Next, SiN or Si to be the gate insulating film 6 is formed.
An insulating film such as O 2 or ia-Si that becomes the semiconductor layer 7, or p
Poly-Si or the like, and n-a-Si or the like to be the ohmic contact layer 8 are formed by the plasma CVD method or the like. Next, the na-Si and i-a-Si are patterned into an island shape or a line shape by a method such as a photoetching method. Next, a pattern is formed by a method such as a photo etching method to form a contact hole on the pixel electrode 5. Further, a metal thin film of Al, Cr or the like is formed by a sputtering method or the like, and this is pattern-formed by a photo etching method or the like to form the source electrode, the source wiring 9 and the drain electrode 10, and then n between the source and the drain is formed. -A-
Etch off Si. Finally, a protective film made of SiN or the like is formed if necessary.

【0006】上記のように構成されたTFTアレイで
は、異物などによりゲート電極4とドレイン電極10が
短絡したり、オーミックコンタクトが十分にとれない等
の理由により、正常に動作しない画素いわゆる点欠陥が
数ppmの確立で発生する。この欠陥を修復する方法と
しては、特開平2−284120や特開平5−6641
5に示されるように、互いに隣り合う駆動電極間を接続
するパターンを蓄積容量と同時に形成し、これをレーザ
照射により溶融し、欠陥となった画素電極を隣り合った
画素電極へ接続する方法がある。
In the TFT array configured as described above, a pixel that does not operate normally, that is, a point defect, is generated due to a short circuit between the gate electrode 4 and the drain electrode 10 due to foreign matter or insufficient ohmic contact. Occurs with a probability of a few ppm. As a method for repairing this defect, Japanese Patent Application Laid-Open No. 2-284120 and Japanese Patent Application Laid-Open No. 5-6641 are known.
As shown in FIG. 5, there is a method in which a pattern for connecting drive electrodes adjacent to each other is formed at the same time as a storage capacitor, and this is melted by laser irradiation to connect a defective pixel electrode to an adjacent pixel electrode. is there.

【0007】[0007]

【発明が解決しようとする課題】上記のように、従来の
TFTアレイにおいては、点欠陥の発生により歩留まり
が低下するという問題があった。また、従来の点欠陥修
復方法では、点欠陥を修復するためのパターンを備えて
いるが、このパターンと隣接する画素電極をレーザ照射
により接続する場合、画素電極側からの照射では、画素
電極が透明であるためレーザを透過してしまい、十分に
接続することが難しいという問題があった。
As described above, the conventional TFT array has a problem that the yield is reduced due to the generation of point defects. Further, the conventional point defect repairing method has a pattern for repairing the point defect. However, when the pixel electrode adjacent to this pattern is connected by laser irradiation, the pixel electrode is irradiated by irradiation from the pixel electrode side. Since it is transparent, it passes through the laser, and there is a problem that it is difficult to make a sufficient connection.

【0008】本発明は、上記のような問題を解決するた
めになされたもので、点欠陥修復を容易にしかも確実に
行える構造のTFTアレイとその製造方法を提供するも
のである。
The present invention has been made to solve the above problems, and provides a TFT array having a structure capable of easily and surely repairing a point defect and a manufacturing method thereof.

【0009】[0009]

【課題を解決するための手段】この発明に係わるTFT
アレイ基板は、透明絶縁基板上に形成された金属薄膜よ
りなるゲート電極を兼ね備えたゲート配線、このゲート
配線上にゲート絶縁膜を介して設けられた半導体層、こ
の半導体層と共に半導体素子を構成するソース電極を兼
ね備えたソース配線およびドレイン電極、上記半導体素
子の近傍に設けられた透明導電膜よりなる画素電極、上
記透明絶縁基板上に形成された金属薄膜よりなる蓄積容
量電極、この蓄積容量電極上に設けられた蓄積容量誘電
体膜、上記蓄積容量電極と同一の金属材料よりなり、隣
接する2つの画素にまたがって配置された第1の金属パ
ターン、この第1の金属パターン上に上記蓄積容量誘電
体膜等の絶縁膜を介して配置された第2の金属パターン
を備え、レーザ照射にて上記第1の金属パターンと上記
第2の金属パターンを溶融して接続することにより隣接
する2つの画素電極間を接続し、画素欠陥の修復を行う
ようにしたものである。また、蓄積容量電極および第1
の金属パターンはCr、TaまたはTi等の金属よりな
るものである。また、第2の金属パターンは、Cr、T
aまたはTi等の金属よりなるものである。また、第2
の金属パターンは、ゲート配線と同一の金属材料よりな
るものである。さらに、第2の金属パターンは画素電極
の上あるいは下に接して形成されているものである。
SUMMARY OF THE INVENTION A TFT according to the present invention
The array substrate forms a semiconductor element together with a gate wiring that also serves as a gate electrode made of a metal thin film formed on a transparent insulating substrate, a semiconductor layer provided on the gate wiring via a gate insulating film, and this semiconductor layer. A source wiring and a drain electrode which also serve as a source electrode, a pixel electrode made of a transparent conductive film provided in the vicinity of the semiconductor element, a storage capacitor electrode made of a metal thin film formed on the transparent insulating substrate, on this storage capacitor electrode A storage capacitor dielectric film, a first metal pattern made of the same metal material as that of the storage capacitor electrode and extending over two adjacent pixels, and the storage capacitor on the first metal pattern. A second metal pattern arranged via an insulating film such as a dielectric film is provided, and the first metal pattern and the second metal pattern are formed by laser irradiation. The connecting between the two adjacent pixel electrodes by connecting by melting, in which to perform the repair of pixel defects. Also, the storage capacitor electrode and the first
The metal pattern of is made of a metal such as Cr, Ta or Ti. The second metal pattern is made of Cr, T
It is made of a metal such as a or Ti. Also, the second
The metal pattern of is made of the same metal material as the gate wiring. Furthermore, the second metal pattern is formed in contact with the top or bottom of the pixel electrode.

【0010】また、この発明に係るTFTアレイ基板の
製造方法は、透明絶縁基板上にCr、TaまたはTi等
の金属薄膜をスパッタリング法等で成膜し、これをフォ
トエッチング法等の方法でパターン形成し、蓄積容量電
極および隣接する2つの画素にまたがって第1の金属パ
ターンを形成する工程と、Cr、TaまたはTi等の金
属薄膜をスパッタリング法等で成膜し、これをフォトエ
ッチング法等の方法でパターン形成し、ゲート電極・配
線および第1の金属パターン上に少なくとも蓄積容量誘
電体膜を介して第2の金属パターンを形成する工程と、
画素欠陥が認められた場合にレーザ照射にて該画素の信
号レベルを切り離し、さらに第1の金属パターンと第2
の金属パターンを溶融し、隣接する2つの画素電極間を
接続することにより、画素欠陥の修復を行う工程とを含
むものである。
Further, in the method of manufacturing a TFT array substrate according to the present invention, a metal thin film of Cr, Ta, Ti or the like is formed on a transparent insulating substrate by a sputtering method or the like, and is patterned by a method such as a photo etching method. A step of forming and forming a first metal pattern across the storage capacitor electrode and two adjacent pixels, and forming a metal thin film of Cr, Ta, Ti or the like by a sputtering method, etc. Forming a second metal pattern on the gate electrode / wiring and the first metal pattern via at least the storage capacitor dielectric film.
When a pixel defect is recognized, the signal level of the pixel is separated by laser irradiation, and the first metal pattern and the second metal pattern are separated.
And melting the metal pattern and connecting the two adjacent pixel electrodes to repair the pixel defect.

【0011】[0011]

【作用】この発明におけるTFTアレイ基板は、画素欠
陥が認められた場合に、レーザ照射にて該画素の信号レ
ベルを切り離し、さらに欠陥画素とこれに隣接する画素
の第1の金属パターンと第2の金属パターンをそれぞれ
溶融し、第1の金属パターンと画素電極とを接続するこ
とにより、隣接する2つの画素電極が接続され、欠陥画
素とこれに隣接する画素の画素電極が同電位となり、同
一表示をするので、欠陥が視認し難くなり、容易且つ確
実に画素欠陥の修復が行える。さらに、第2の金属パタ
ーンは画素電極の上または下に接して形成されているの
で、第1の金属パターンと第2の金属パターンを溶融す
ることにより、第1の金属パターンと画素電極とを確実
に接続することができ、特に画素電極側からのレーザ照
射に対して効果的である。
In the TFT array substrate according to the present invention, when a pixel defect is recognized, the signal level of the pixel is separated by laser irradiation, and the defective pixel and the first metal pattern and the second metal pattern of the pixel adjacent thereto are separated. By melting the respective metal patterns and connecting the first metal pattern and the pixel electrode, two adjacent pixel electrodes are connected, and the defective pixel and the pixel electrode of the pixel adjacent thereto have the same potential, Since the display is made, it becomes difficult to visually recognize the defect, and the pixel defect can be easily and surely repaired. Furthermore, since the second metal pattern is formed in contact with the upper or lower part of the pixel electrode, the first metal pattern and the second metal pattern are melted to form the first metal pattern and the pixel electrode. The connection can be surely made, and it is particularly effective for laser irradiation from the pixel electrode side.

【0012】また、この発明におけるTFTアレイ基板
の製造方法では、第1の金属パターンを蓄積容量電極
と、第2の金属パターンをゲート配線と、それぞれ同じ
金属材料で同時に形成するので、従来の工程と同じ工程
数で、マスクのみを変更すれば良く、コスト高にならず
容易に製造することができる。
In the method of manufacturing a TFT array substrate according to the present invention, the first metal pattern and the second metal pattern are simultaneously formed of the same metal material and the storage capacitor electrode, respectively. Only the mask needs to be changed in the same number of steps as in (3), and the manufacturing can be performed easily without increasing the cost.

【0013】[0013]

【実施例】【Example】

実施例1.本発明の実施例1を図について説明する。図
1は、本発明の表示装置に用いられるTFTアレイの部
分平面図、図2は図1のA−A断面図、図3は図1のB
−B断面図である。図において、11は蓄積容量電極2
と同材料で同時に形成された第1の金属パターンである
点欠陥修復パターン、12はゲート電極およびゲート配
線4と同材料で同時に形成された第2の金属パターンで
あるアイランドをそれぞれ示し、アイランド12は画素
電極5の下に接して形成されている。また、図中C−C
およびDは点欠陥修復の際のレーザ照射箇所である。な
お、従来例と同一部分については同符号を付し、説明を
省略する。
Embodiment 1 FIG. Example 1 of the present invention will be described with reference to the drawings. FIG. 1 is a partial plan view of a TFT array used in the display device of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is B of FIG.
It is a -B sectional view. In the figure, 11 is the storage capacitor electrode 2
Is a first metal pattern simultaneously formed with the same material as the point defect repair pattern, and 12 is an island which is a second metal pattern simultaneously formed with the same material as the gate electrode and the gate wiring 4, and an island 12 Are formed below and in contact with the pixel electrode 5. Also, C-C in the figure
And D are laser irradiation points at the time of repairing point defects. The same parts as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

【0014】次に、本実施例におけるTFTアレイの製
造方法について説明する。まず、洗浄したガラス基板1
にCr、Ta、Ti等の金属薄膜をスパッタリング法等
の方法で成膜し、これをフォトエッチング法等の方法で
パターン形成し、蓄積容量電極2および点欠陥修復パタ
ーン11を形成する。次に、蓄積容量の誘電体膜3とな
るSiNやSiO2等の膜をプラズマCVD(化学的気
相成長)法等で成膜し、後に形成するゲート電極および
ゲート配線4とコンタクトするためのコンタクトホール
等をパターン形成する。次に、Cr、Ta、Ti等の高
融点金属薄膜を膜厚300nm程度スパッタリング法等
の方法で成膜し、これをフォトエッチング法等の方法で
パターン形成し、ゲート電極・配線4および点欠陥修復
パターン11との接続部分にアイランド12を形成す
る。すなわち、点欠陥を修復する場合のレーザ照射箇所
Dには、点欠陥修復パターン11上に蓄積容量の誘電体
3を介してアイランド12が形成されている。
Next, a method of manufacturing the TFT array in this embodiment will be described. First, the washed glass substrate 1
Then, a metal thin film of Cr, Ta, Ti or the like is formed by a method such as a sputtering method, and this is patterned by a method such as a photoetching method to form the storage capacitor electrode 2 and the point defect repair pattern 11. Next, a film of SiN, SiO 2 or the like to be the dielectric film 3 of the storage capacitor is formed by a plasma CVD (chemical vapor deposition) method or the like, and a gate electrode and a gate wiring 4 to be formed later are contacted. A contact hole or the like is patterned. Next, a refractory metal thin film of Cr, Ta, Ti or the like is formed to a film thickness of about 300 nm by a method such as a sputtering method, and this is pattern-formed by a method such as a photoetching method to form the gate electrode / wiring 4 and point defects. The island 12 is formed at the connection portion with the repair pattern 11. That is, the island 12 is formed on the point defect repair pattern 11 via the dielectric 3 of the storage capacitor at the laser irradiation position D when repairing the point defect.

【0015】さらに、ITO(インジウムすず酸化物)
等の透明導電膜をスパッタリング等の方法で膜厚100
nm程度成膜し、これをフォトエッチング法等の方法で
パターン形成し、画素電極5を形成する。次に、ゲート
絶縁膜6となるSiNやSiO2等の絶縁膜を膜厚30
0nm程度、半導体層7となるi−a−Siや、pol
y−Si等を膜厚200nm程度、およびオーミックコ
ンタクト層8となるn−a−Si等を50nm程度、プ
ラズマCVD(化学的気相成長)法等で成膜する。次
に、フォトエッチング法等の方法でn−a−Siおよび
i−a−Siをライン状もしくはアイランド状にパター
ン形成する。次に、フォトエッチング法等の方法でパタ
ーン形成し、画素電極5上にコンタクトホールを形成す
る。次に、Al、Cr等の金属薄膜をスパッタリング法
等で膜厚400nm程度成膜し、これをフォトエッチン
グ法等でパターン形成し、ソース電極・配線9およびド
レイン電極10を形成後、ソース・ドレイン間にあるn
−a−Siをエッチオフする。最後に、必要に応じてS
iN等で保護膜を形成する。
Further, ITO (indium tin oxide)
A transparent conductive film such as a film having a thickness of 100 is formed by a method such as sputtering.
A film having a thickness of about nm is formed, and this is patterned by a method such as a photoetching method to form the pixel electrode 5. Next, an insulating film such as SiN or SiO 2 to be the gate insulating film 6 is formed to a thickness of 30.
About 0 nm, ia-Si that becomes the semiconductor layer 7 and pol
A film thickness of about 200 nm of y-Si or the like and about 50 nm of na-Si or the like to be the ohmic contact layer 8 is formed by a plasma CVD (chemical vapor deposition) method or the like. Next, the na-Si and i-a-Si are patterned into a line shape or an island shape by a method such as a photoetching method. Next, a pattern is formed by a method such as a photo etching method to form a contact hole on the pixel electrode 5. Next, a metal thin film of Al, Cr or the like is formed to a film thickness of about 400 nm by a sputtering method or the like, and this is patterned by a photo etching method or the like to form the source electrode / wiring 9 and the drain electrode 10, and then the source / drain. N between
Etch off a-Si. Finally, if necessary, S
A protective film is formed with iN or the like.

【0016】以上のようにして作成したTFTアレイお
よびそれを用いた液晶表示装置において、点欠陥として
認識される画素に対し、その画素のトランジスタ部をレ
ーザ光で図1に示すC−C線部で切断し、その後、画素
電極5上のD部および隣接画素の画素電極5上のD部に
レーザ光を照射して、点欠陥修復パターン11を介して
隣接する画素の画素電極を短絡させる。この場合、蓄積
容量の誘電体3を介した2つの金属膜、すなわち点欠陥
修復パターン11およびアイランド12をレーザで接続
するため、容易にしかも確実に修復が行える。特に、画
素電極5側からのレーザ照射に対して効果的である。な
お、本実施例では左右の画素電極を接続するよう構成し
たが、上下の画素電極を接続することも可能である。
In the TFT array manufactured as described above and the liquid crystal display device using the TFT array, for the pixel recognized as a point defect, the transistor portion of the pixel is irradiated with laser light and the CC line portion shown in FIG. Then, the D portion on the pixel electrode 5 and the D portion on the pixel electrode 5 of the adjacent pixel are irradiated with laser light to short-circuit the pixel electrodes of the adjacent pixels via the point defect repair pattern 11. In this case, since the two metal films, that is, the point defect repair pattern 11 and the island 12 are connected by the laser via the dielectric 3 of the storage capacitor, the repair can be performed easily and surely. In particular, it is effective for laser irradiation from the pixel electrode 5 side. Although the left and right pixel electrodes are connected in this embodiment, the upper and lower pixel electrodes can be connected.

【0017】本実施例によれば、点欠陥として認識され
た画素を、点欠陥修復パターン11を利用して隣接する
画素と短絡させることにより、互いに隣接する画素電極
が同電位となり、同一の表示を行うので、点欠陥として
視認しにくくなり、TFTアレイの歩留まりが向上す
る。また、従来と同様の製造方法でパターンのみの変更
であるので、工程数を増やすことなくコスト高にならな
い利点がある。また、本発明によれば、TFTアレイ段
階で発見された点欠陥は言うに及ばず、このTFTアレ
イ基板と透明電極およびカラーフィルタ等を有する対向
電極基板との間に液晶を挟持した液晶表示装置となった
後でも、すなわち画素電極側からレーザ光を入射する場
合でも、容易にしかも確実な修復が可能となる。
According to this embodiment, a pixel recognized as a point defect is short-circuited with an adjacent pixel by using the point defect repair pattern 11, so that the pixel electrodes adjacent to each other have the same potential and the same display. Therefore, it becomes difficult to visually recognize as a point defect, and the yield of the TFT array is improved. Further, since only the pattern is changed by the manufacturing method similar to the conventional method, there is an advantage that the cost is not increased without increasing the number of steps. Further, according to the present invention, not to mention the point defect found in the TFT array stage, a liquid crystal display device in which liquid crystal is sandwiched between this TFT array substrate and a counter electrode substrate having a transparent electrode, a color filter and the like. After that, that is, even when the laser light is incident from the pixel electrode side, the repair can be performed easily and surely.

【0018】実施例2.図4は、本発明の実施例2であ
る表示装置に用いられるTFTアレイを示す部分断面図
である。本実施例は、ゲート電極・配線4と画素電極5
の製造工程の順序を入れ換えた以外は、実施例1と同様
の構造である。すなわち、点欠陥修復パターン11上
に、蓄積容量の誘電体3を介して画素電極5が形成さ
れ、その上にアイランド12が形成される。このように
アイランド12は、画素電極5の上あるいは下のどちら
でも良く、どちらの構造であっても、点欠陥修復パター
ン11を利用して容易に点欠陥を修復することが可能で
あり、実施例1と同様の効果が得られる。
Embodiment 2 FIG. FIG. 4 is a partial cross-sectional view showing a TFT array used in a display device which is Embodiment 2 of the present invention. In this embodiment, the gate electrode / wiring 4 and the pixel electrode 5 are
The structure is the same as that of the first embodiment except that the order of the manufacturing steps is changed. That is, the pixel electrode 5 is formed on the point defect repair pattern 11 via the dielectric 3 of the storage capacitor, and the island 12 is formed thereon. As described above, the island 12 may be above or below the pixel electrode 5, and it is possible to easily repair the point defect by using the point defect repair pattern 11 in any structure. The same effect as in Example 1 can be obtained.

【0019】実施例3.本発明の実施例3を図について
説明する。図5は、本発明の液晶表示装置に用いられる
TFTアレイの部分平面図、図6は図5のA−A断面
図、図7は図5のB−B断面図である。図において、1
3はエッチングストッパ膜である。
Embodiment 3 FIG. A third embodiment of the present invention will be described with reference to the drawings. 5 is a partial plan view of a TFT array used in the liquid crystal display device of the present invention, FIG. 6 is a sectional view taken along line AA of FIG. 5, and FIG. 7 is a sectional view taken along line BB of FIG. In the figure, 1
3 is an etching stopper film.

【0020】本実施例におけるTFTアレイの製造方法
について説明する。まず、洗浄したガラス基板1にC
r、Ta、Ti等の金属薄膜をスパッタリング法等の方
法で成膜し、これをフォトエッチング法等の方法でパタ
ーン形成し、蓄積容量電極2、さらに点欠陥修復パター
ン11を形成する。次に、蓄積容量の誘電体膜3となる
SiNやSiO2等の膜をプラズマCVD(化学的気相
成長)法等で成膜し、後で形成するゲート電極・配線と
コンタクトするためのコンタクトホール等をパターン形
成する。次に、Cr、Ta、Ti等の高融点金属薄膜を
膜厚300nm程度スパッタリング法等の方法で成膜
し、これをフォトエッチング法等の方法でパターン形成
し、ゲート電極・配線4、さらに点欠陥修復パターン1
1との接続部分にアイランド12を形成する。すなわ
ち、点欠陥を修復する場合のレーザ照射箇所には、点欠
陥修復パターン11上に蓄積容量の誘電体3を介してア
イランド12が形成されている。
A method of manufacturing the TFT array in this embodiment will be described. First, C on the washed glass substrate 1
A metal thin film of r, Ta, Ti or the like is formed by a method such as a sputtering method, and this is patterned by a method such as a photoetching method to form the storage capacitor electrode 2 and the point defect repair pattern 11. Next, a film such as SiN or SiO 2 which will be the dielectric film 3 of the storage capacitor is formed by a plasma CVD (chemical vapor deposition) method or the like, and a contact for contacting a gate electrode / wiring to be formed later is formed. Pattern holes and the like. Next, a refractory metal thin film of Cr, Ta, Ti or the like is formed to a film thickness of about 300 nm by a method such as a sputtering method, and this is formed into a pattern by a method such as a photoetching method. Defect repair pattern 1
The island 12 is formed at the connection portion with 1. That is, the island 12 is formed on the point defect repair pattern 11 via the dielectric 3 of the storage capacitor at the laser irradiation position when repairing the point defect.

【0021】さらに、ITO(インジウムすず酸化物)
等の透明導電膜をスパッタリング等の方法で膜厚100
nm程度成膜する。この膜厚は、液晶表示装置として要
求される輝度を得るため、最大150nmまでとする。
これをフォトエッチング法等の方法でパターン形成し、
画素電極5を形成する。次に、ゲート絶縁膜6となるS
iNやSiO2等の絶縁膜を膜厚300nm程度、半導
体層7となるi−a−Siや、poly−Si等を膜厚
100nm程度、およびエッチングストッパ膜13とな
るSiNやSiO2等の絶縁膜を膜厚200nm程度、
プラズマCVD法等で成膜する。次に、フォトエッチン
グ法等の方法でエッチングストッパ膜13をパターン形
成する。続いて、オーミックコンタクト層8となるn−
a−Si等をプラズマCVD法等で50nm程度成膜
し、フォトエッチング法等の方法でパターン形成し、画
素電極5上にコンタクトホールを形成する。次に、A
l、Cr等の金属薄膜をスパッタリング法等で膜厚40
0nm程度成膜し、これをフォトエッチング法等でパタ
ーン形成し、ソース電極・配線9およびドレイン電極1
0を形成する。次に、ソース・ドレイン間にあるn−a
−Siおよび画素部にある不要なn−a−Siやi−a
−Siをエッチオフする。最後に、必要に応じてSiN
等で保護膜を形成する。
Further, ITO (indium tin oxide)
A transparent conductive film such as a film having a thickness of 100 is formed by a method such as sputtering.
A film having a thickness of about nm is formed. This film thickness is 150 nm at maximum in order to obtain the brightness required for a liquid crystal display device.
This is patterned by a method such as photo etching,
The pixel electrode 5 is formed. Next, S that becomes the gate insulating film 6
Insulating films such as iN and SiO 2 having a film thickness of about 300 nm, ia-Si forming the semiconductor layer 7 and poly-Si having a film thickness of about 100 nm, and insulating films such as SiN and SiO 2 forming the etching stopper film 13. The film thickness is about 200 nm,
A film is formed by a plasma CVD method or the like. Next, the etching stopper film 13 is patterned by a method such as a photo etching method. Then, n- which becomes the ohmic contact layer 8 is formed.
A film of a-Si or the like having a thickness of about 50 nm is formed by a plasma CVD method or the like, and a pattern is formed by a method such as a photo-etching method or the like to form a contact hole on the pixel electrode 5. Next, A
l, a metal thin film such as Cr having a film thickness of 40 by a sputtering method or the like.
A film having a thickness of about 0 nm is formed, and a pattern is formed by a photoetching method or the like to form the source electrode / wiring 9 and the drain electrode 1.
Form 0. Next, na between the source and the drain
-Si and unnecessary n-a-Si and i-a in the pixel section
Etch off Si. Finally, if necessary, SiN
Etc. to form a protective film.

【0022】以上のようにして作成したTFTアレイお
よびそれを用いた液晶表示装置において、点欠陥として
認識される画素に対し、その画素のトランジスタ部をレ
ーザ光で図5に示すC−C線部で切断し、その後、画素
電極5上のD部および隣接画素の画素電極5上のD部に
それぞれレーザ光を照射して、点欠陥修復パターン11
を介して隣接する画素の画素電極を短絡させる。上記の
ような構造のTFTアレイにおいても、実施例1および
2と同様の効果が得られる。
In the TFT array produced as described above and the liquid crystal display device using the TFT array, for the pixel recognized as a point defect, the transistor portion of the pixel is irradiated with laser light to show the CC line portion shown in FIG. Then, the D portion on the pixel electrode 5 and the D portion on the pixel electrode 5 of the adjacent pixel are respectively irradiated with laser light, and the point defect repair pattern 11 is formed.
The pixel electrodes of the adjacent pixels are short-circuited via. Also in the TFT array having the above structure, the same effects as those of the first and second embodiments can be obtained.

【0023】実施例4.図8は、本発明の実施例4であ
る液晶表示装置に用いられるTFTアレイを示す部分断
面図である。本実施例は、ゲート電極4と画素電極5の
製造工程の順序を入れ換えた以外は、実施例3と同様の
構造である。すなわち、点欠陥修復パターン11上に、
蓄積容量の誘電体膜3を介して画素電極5が形成され、
その上にアイランド12が形成される。このような構造
であっても、点欠陥修復パターン11を利用して容易に
点欠陥を修復することが可能であり、実施例1〜3と同
様の効果が得られる。なお、上記実施例で示したTFT
アレイの構造はほんの一例にすぎず、本発明はこれらの
構造に限定されるものではない。
Embodiment 4 FIG. FIG. 8 is a partial cross-sectional view showing a TFT array used in a liquid crystal display device which is Embodiment 4 of the present invention. This embodiment has the same structure as that of the third embodiment except that the order of manufacturing steps of the gate electrode 4 and the pixel electrode 5 is changed. That is, on the point defect repair pattern 11,
The pixel electrode 5 is formed via the dielectric film 3 of the storage capacitor,
The island 12 is formed on it. Even with such a structure, the point defect can be easily repaired by using the point defect repair pattern 11, and the same effect as that of the first to third embodiments can be obtained. In addition, the TFT shown in the above embodiment
The structures of the arrays are only examples and the invention is not limited to these structures.

【0024】[0024]

【発明の効果】以上のように、この発明によれば、レー
ザ照射にて隣接する2つの画素に重複する第1の金属パ
ターンと、この第1の金属パターン上に蓄積容量誘電体
膜等の絶縁膜を介して形成された第2の金属パターンを
溶融することにより、画素欠陥の修復が容易且つ確実に
行えるTFTアレイ基板および該TFTアレイ基板を用
いた液晶表示装置が得られ、歩留まりが向上する効果が
ある。
As described above, according to the present invention, a first metal pattern that overlaps two adjacent pixels by laser irradiation, and a storage capacitor dielectric film or the like is formed on the first metal pattern. By melting the second metal pattern formed through the insulating film, a TFT array substrate in which pixel defects can be easily and reliably repaired and a liquid crystal display device using the TFT array substrate are obtained, and the yield is improved. Has the effect of

【0025】また、本発明における製造方法によれば、
第1の金属パターンを蓄積容量電極と、第2の金属パタ
ーンをゲート配線と、それぞれ同じ金属材料で同時に形
成するので、従来の工程と同じ工程数で、マスクのみを
変更すれば良く、コスト高にならず容易に製造すること
ができる。
According to the manufacturing method of the present invention,
Since the first metal pattern and the second metal pattern are simultaneously formed with the same metal material as the storage capacitor electrode and the second metal pattern, respectively, only the mask needs to be changed in the same number of steps as the conventional steps, which results in high cost. It can be easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明の一実施例である液晶表示装置に用
いるTFTアレイを示す部分平面図である。
FIG. 1 is a partial plan view showing a TFT array used in a liquid crystal display device according to an embodiment of the present invention.

【図2】 図1のA−A断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】 図1のB−B断面図である。FIG. 3 is a sectional view taken along line BB of FIG.

【図4】 本発明の第2の実施例である液晶表示装置に
用いるTFTアレイを示す部分断面図である。
FIG. 4 is a partial sectional view showing a TFT array used in a liquid crystal display device according to a second embodiment of the present invention.

【図5】 本発明の第3の実施例である液晶表示装置に
用いるTFTアレイを示す部分平面図である。
FIG. 5 is a partial plan view showing a TFT array used in a liquid crystal display device according to a third embodiment of the present invention.

【図6】 図5のA−A断面図である。6 is a cross-sectional view taken along the line AA of FIG.

【図7】 図6のB−B断面図である。7 is a sectional view taken along line BB of FIG.

【図8】 本発明の第4の実施例である液晶表示装置に
用いるTFTアレイを示す部分断面図である。
FIG. 8 is a partial cross-sectional view showing a TFT array used in a liquid crystal display device which is a fourth embodiment of the present invention.

【図9】 従来の液晶表示装置に用いるTFTアレイを
示す部分平面図である。
FIG. 9 is a partial plan view showing a TFT array used in a conventional liquid crystal display device.

【図10】 図9のA−A断面図である。10 is a cross-sectional view taken along the line AA of FIG.

【符号の説明】[Explanation of symbols]

1 ガラス基板、2 蓄積容量電極、3 蓄積容量の誘
電体膜、4 ゲート電極・配線、5 画素電極、6 ゲ
ート絶縁膜、7 半導体層、8 オーミックコンタクト
層、9 ソース電極・配線、10 ドレイン電極、11
点欠陥修復パターン、12 アイランド。
1 glass substrate, 2 storage capacitor electrode, 3 storage capacitor dielectric film, 4 gate electrode / wiring, 5 pixel electrode, 6 gate insulating film, 7 semiconductor layer, 8 ohmic contact layer, 9 source electrode / wiring, 10 drain electrode , 11
Point defect repair pattern, 12 islands.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 透明絶縁基板上に形成された金属薄膜よ
りなるゲート電極を兼ね備えたゲート配線、このゲート
配線上にゲート絶縁膜を介して設けられた半導体層、こ
の半導体層と共に半導体素子を構成するソース電極を兼
ね備えたソース配線およびドレイン電極、上記半導体素
子の近傍に設けられた透明導電膜よりなる画素電極、上
記透明絶縁基板上に形成された金属薄膜よりなる蓄積容
量電極、この蓄積容量電極上に設けられた蓄積容量誘電
体膜、上記蓄積容量電極と同一の金属材料よりなり、隣
接する2つの画素にまたがって配置された第1の金属パ
ターン、この第1の金属パターン上に上記蓄積容量誘電
体膜等の絶縁膜を介して配置された第2の金属パターン
を備え、レーザ照射にて上記第1の金属パターンと上記
第2の金属パターンを溶融して接続することにより隣接
する2つの画素電極間を接続し、画素欠陥の修復を行う
ことを特徴とするTFTアレイ基板。
1. A gate wiring formed on a transparent insulating substrate and also serving as a gate electrode made of a metal thin film, a semiconductor layer provided on the gate wiring via a gate insulating film, and a semiconductor element together with this semiconductor layer. A source wiring and a drain electrode which also serve as a source electrode, a pixel electrode made of a transparent conductive film provided in the vicinity of the semiconductor element, a storage capacitor electrode made of a metal thin film formed on the transparent insulating substrate, and this storage capacitor electrode. A storage capacitor dielectric film provided above, a first metal pattern made of the same metal material as that of the storage capacitor electrode and arranged over two adjacent pixels, and the storage on the first metal pattern. A second metal pattern arranged via an insulating film such as a capacitive dielectric film is provided, and the first metal pattern and the second metal pattern are formed by laser irradiation. A TFT array substrate, characterized in that the two pixel electrodes adjacent to each other are melted and connected to each other to repair pixel defects.
【請求項2】 蓄積容量電極および第1の金属パターン
はCr、TaまたはTi等の金属よりなることを特徴と
する請求項1記載のTFTアレイ基板。
2. The TFT array substrate according to claim 1, wherein the storage capacitor electrode and the first metal pattern are made of a metal such as Cr, Ta or Ti.
【請求項3】 第2の金属パターンは、Cr、Taまた
はTi等の金属よりなることを特徴とする請求項1記載
のTFTアレイ基板。
3. The TFT array substrate according to claim 1, wherein the second metal pattern is made of a metal such as Cr, Ta or Ti.
【請求項4】 第2の金属パターンは、ゲート配線と同
一の金属材料よりなることを特徴とする請求項1記載の
TFTアレイ基板。
4. The TFT array substrate according to claim 1, wherein the second metal pattern is made of the same metal material as the gate wiring.
【請求項5】 第2の金属パターンは画素電極の上ある
いは下に接して形成されていることを特徴とする請求項
1記載のTFTアレイ基板。
5. The TFT array substrate according to claim 1, wherein the second metal pattern is formed in contact with above or below the pixel electrode.
【請求項6】 請求項1〜請求項5のいずれか一項記載
のTFTアレイ基板と、透明電極およびカラーフィルタ
等を有する対向電極基板との間に液晶が配置されている
ことを特徴とする液晶表示装置。
6. A liquid crystal is arranged between the TFT array substrate according to any one of claims 1 to 5 and a counter electrode substrate having a transparent electrode and a color filter or the like. Liquid crystal display device.
【請求項7】 透明絶縁基板上にCr、TaまたはTi
等の金属薄膜をスパッタリング法等で成膜し、これをフ
ォトエッチング法等の方法でパターン形成して、蓄積容
量電極および隣接する2つの画素にまたがって第1の金
属パターンを形成する工程、 SiN、SiO2等をプラズマCVD(化学的気相成
長)法等で成膜し、これをパターン形成し、蓄積容量誘
電体膜を形成する工程、 Cr、TaまたはTi等の金属薄膜をスパッタリング法
等で成膜し、これをフォトエッチング法等の方法でパタ
ーン形成し、ゲート電極・配線および上記第1の金属パ
ターン上に少なくとも上記蓄積容量誘電体膜を介して第
2の金属パターンを形成する工程、 透明導電膜をスパッタリング等の方法で成膜し、パター
ン形成により画素電極を形成する工程、 ゲート絶縁膜、半導体層およびオーミックコンタクト層
をプラズマCVD法等で順次成膜し、これらをパターン
形成する工程、 Al、Cr等の金属薄膜をスパッタリング法等で成膜
し、パターン形成によりソース電極・配線およびドレイ
ン電極を形成する工程、 画素欠陥が認められた場合にレーザ照射にて該画素の信
号回路を切り離し、さらに上記第1の金属パターンと上
記第2の金属パターンを溶融し、隣接する2つの画素電
極間を接続することにより、画素欠陥の修復を行う工程
を含むことを特徴とするTFTアレイ基板の製造方法。
7. Cr, Ta or Ti on a transparent insulating substrate
Forming a first metal pattern across the storage capacitor electrode and two adjacent pixels by forming a metal thin film such as a film by a sputtering method or the like and forming a pattern by a method such as a photoetching method, SiN , SiO 2 etc. are formed by plasma CVD (Chemical Vapor Deposition) method etc., this is patterned to form a storage capacitor dielectric film, metal thin film of Cr, Ta or Ti etc. is sputtered etc. And forming a pattern by a method such as a photoetching method, and forming a second metal pattern on the gate electrode / wiring and the first metal pattern through at least the storage capacitor dielectric film. A step of forming a pixel electrode by patterning a transparent conductive film by a method such as sputtering, a gate insulating film, a semiconductor layer and an ohmic contact layer A step of sequentially forming a film by plasma CVD or the like and forming a pattern thereof, a step of forming a metal thin film of Al, Cr or the like by a sputtering method, and forming a source electrode / wiring and a drain electrode by pattern formation, a pixel defect If the signal is detected, the signal circuit of the pixel is cut off by laser irradiation, the first metal pattern and the second metal pattern are melted, and two adjacent pixel electrodes are connected to each other to form a pixel. A method of manufacturing a TFT array substrate, comprising the step of repairing defects.
JP15486495A 1995-05-30 1995-06-21 Tft array substrate as well as liquid crystal display device formed by using the tft array substrate and production of tft array substrate Pending JPH095786A (en)

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JP15486495A JPH095786A (en) 1995-06-21 1995-06-21 Tft array substrate as well as liquid crystal display device formed by using the tft array substrate and production of tft array substrate
TW085105967A TW300341B (en) 1995-05-30 1996-05-21
KR1019960018811A KR100363140B1 (en) 1995-05-30 1996-05-30 TFT array substrate, liquid crystal display using the same, and manufacturing method of TFT array substrate
CN96107917A CN1105324C (en) 1995-05-30 1996-05-30 Array base plate, liquid-crystal displaying device of thin-film transistor, and method for production of said base plate

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