KR100482343B1 - Thin film transistor array substrate for protecting loading effect and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of preventing loading effects by forming an equipotential pattern between active regions during a manufacturing process and a method of manufacturing the same.

According to the present invention, a thin film transistor array substrate includes a substrate, a plurality of thin film transistors formed on the substrate, a plurality of thin film transistor array panels each having a plurality of data lines connected to the thin film transistor to apply a data signal, and a thin film transistor. Equipotential pattern is formed on the edge of the substrate to form an equipotential with the array panel.

A method of manufacturing a thin film transistor array substrate according to the present invention includes the steps of providing a plurality of thin film transistor array panels each having a plurality of thin film transistors formed on the substrate and a plurality of data lines connected to the thin film transistors to apply a data signal; And forming an equipotential pattern at an edge of the substrate to form an equipotential with the thin film transistor array panel.

Description

TIN FILM TRANSISTOR ARRAY SUBSTRATE FOR PROTECTING LOADING EFFECT AND MANUFACTURING METHOD THEREOF}

The present invention relates to a method of manufacturing a thin film transistor array substrate for preventing the loading effect, and more particularly, to a thin film transistor array substrate and a method for manufacturing the thin film transistor array substrate that can prevent the loading effect by forming an equipotential pattern between the active region during the manufacturing process. .

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor array substrate and a color filter array substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor array panel constituting the thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed of a switch element at each intersection of the gate lines and the data lines, and a liquid crystal cell unit connected to the thin film transistor. Pixel electrode or the like. The gate lines and the data lines receive signals from the driving circuits through the respective pad parts. The thin film transistor supplies the pixel voltage signal supplied to the data line to the pixel electrode in response to the scan signal supplied to the gate line.

The color filter array substrate includes color filters formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal cells in common.

The liquid crystal panel is manufactured by separately manufacturing a thin film transistor array substrate and a color filter array substrate, and then injecting a liquid crystal.

In particular, in the thin film transistor array substrate, a plurality of thin film transistor array panels (for example, four) are simultaneously manufactured on the large glass substrate 51 as shown in FIG. 1. After the plurality of thin film transistor array panels manufactured at the same time are cut along the scribing line, the respective thin film transistor array substrates constitute each liquid crystal panel. In addition, the color filter array substrate bonded to the thin film transistor array substrate is also subjected to a process in which a plurality (for example, four) are simultaneously produced and cut on the large glass substrate.

In fact, each of the plurality of thin film transistor array panels includes an active region 53a, which is an area where pixel electrodes are positioned to display a screen, and a pad region 53b, which is an inactive area to which a signal for driving the active region 53a is supplied. Divided into

FIG. 2 is an enlarged view of an R region including a portion of the active region 53a and a portion of the pad region 53b of FIG. 1.

Referring to FIG. 2, in the thin film transistor array panel, the active region 53a includes a thin film transistor 5 formed at each intersection of the gate line 1 and the data line 3, and a pixel electrode connected to the thin film transistor 5. And a storage capacitor 17 formed at an overlapping portion of the pixel electrode 15 and the previous gate line 1, and a gate pad portion (not shown) connected to the gate line 1 in the pad region 53b. And the array shorting bar 8 commonly connected to the odd data lines 2 via the data pad part 31 and the array area including the data pad part 31 connected to the data line 3. And a shorting bar area including an even shorting bar 6 commonly connected to the even data lines 4.

The gate line 1 and the data line 3 intersect insulated with the gate insulating film interposed therebetween. The thin film transistor 5 formed at each intersection of the gate line 1 and the data line 3 includes a gate electrode 7 connected to the gate line 1, and a source electrode 9 connected to the data line 3. ), A drain electrode 11 connected to the pixel electrode 15, and an active layer (not shown) overlapping the gate electrode 7 and forming a channel between the source electrode 9 and the drain electrode 11. Equipped. The active layer usually extends along the data line 3. An ohmic contact layer is formed on the active layer except for the channel portion. The thin film transistor 5 allows the pixel voltage signal supplied to the data line 3 to be charged and maintained in the pixel electrode 15 in response to the scan signal supplied to the gate line 1.

The pixel electrode 15 is connected to the drain electrode 11 of the thin film transistor 5 through the first contact hole 13 penetrating a protective film (not shown). The pixel electrode 15 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor array substrate and the upper color filter array substrate is rotated by dielectric anisotropy and transmits the light incident through the pixel electrode 15 from the light source (not shown) toward the upper substrate. .

The storage capacitor 17 overlaps the previous gate line 1, the storage electrode 19 overlapping between the gate line 1 and the gate insulating layer, and the storage electrode 19 and the passivation layer therebetween. The pixel electrode 15 is connected via the second contact hole 21 formed in the protective film. The storage capacitor 17 allows the pixel voltage charged in the pixel electrode 15 to be stably maintained until the next pixel voltage is charged.

The data line 3 is connected to the data driver via the data link 23 and the data pad section 31, and the gate line 1 is also connected to the gate driver via the gate link and the gate pad section.

The data pad part 31 is connected to the data pad 25 through the data pad 25 extending from the data line 3 via the data link 23 and the third contact hole 29 penetrating the protective film. And a data pad protection electrode 27.

The data shorting bar is divided into an odd shorting bar and an even shorting bar connected by being divided into odd lines and even lines of each of the gate lines and the data lines, and after the manufacturing process of the thin film transistor array substrate, It is provided to detect line defects such as short and disconnection and defects of the thin film transistor. Specifically, the inspection of the gate lines is performed by using a gate odd shorting bar commonly connected to the odd gate lines and a gate even shorting bar commonly connected to the even gate lines. The inspection of the data lines detects a line defect using a data odd shorting bar commonly connected to odd data lines and a data even shorting bar commonly connected to even data lines. The dual odd shorting bar 8 is commonly connected to the odd data lines 2 via the data pad unit 31, and the even shorting bar 6 is connected to the even data lines via the data pad unit 31. 4) and common connection.

The odd shorting bar 8 is formed of a source / drain metal layer together with the data lines 3. Alternatively, the even shorting bar 6 is formed of a gate metal layer to be insulated from the odd data lines 2 across it. The even shorting bar 6 formed of the gate metal layer is connected to the even data lines 4 formed of the source / drain metal layer through the contact electrode 10 formed over the fourth contact hole 12, as shown in FIG. 2. do. When the thin film transistor array panel is completed, defect inspection of the data lines 1 is performed using the odd shorting bar 8 and the even shorting bar 6. Subsequently, the data shorting bars 6 and 8 are cut along the scribing line between the even shorting bar 6 and the data pad part 31.

3 is cut along the data shorting bar region, the thin film transistor region, and the data pad region shown in FIG. 2 along the lines A-A ', B-B', C-C ', and D-D'. It is sectional drawing.

Referring to FIG. 3, in the data shorting bar regions A-A 'and B-B', an even shorting bar 6 made of a gate metal layer is formed on the lower substrate 14, and the gate insulating layer 16 is formed thereon. Is formed. The odd data lines 2 and the even data lines 4 and the odd shorting bar 8 formed of the source / drain metal layer are formed on the gate insulating layer 16, and the passivation layer 18 is formed thereon. In addition, a contact hole 12 penetrating through the gate insulating layer 14 and the passivation layer 18 is formed to expose the even data lines 4 and the even shorting bar 6, and the contact is formed over the contact hole 12. An electrode 10 is formed to connect the even data lines 4 and the even shorting bar 6 formed of different metal layers.

In the thin film transistor region C-C ', a gate line 1 formed of a gate metal layer is formed on the lower substrate 14, and a gate insulating layer 16 is formed thereon. On the gate insulating layer 16, a source electrode 9, a drain electrode 11, and a storage electrode 19 formed of a source / drain metal layer are formed, and a passivation layer 18 is formed thereon. Contact holes 13 and 21 penetrating the passivation layer 18 are formed to expose the drain electrode 11 and the storage electrode 19, and the drain electrodes 7 and the contact holes 13 and 21 are formed therein. The pixel electrode 15 connected to the storage electrode 19 is formed.

In the data pad region D-D ', a gate insulating layer 16 is formed on the lower substrate 14. A data pad 25 made of a source / drain metal layer is formed on the gate insulating layer 16, and a passivation layer 18 is formed thereon. A third contact hole 29 penetrating the passivation layer 18 is formed to expose the data pad 25, and the data pad protection electrode 27 connected to the data pad 25 over the contact hole 29. ) Is formed.

A method of manufacturing the data shorting bar, the thin film transistor, and the data pad region will be described in detail with reference to FIGS. 4A through 4D in connection with the method of manufacturing the thin film transistor array substrate.

Referring to FIG. 4A, gate metal patterns including an even data shorting bar 6, a gate line 1, a gate electrode 7, and a gate pad (not shown) are formed on the lower substrate 14.

The gate metal patterns are formed by depositing a gate metal material on the lower substrate 14 by a deposition method such as sputtering, and then patterning the same by a photolithography process and an etching process using a first mask. As the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used in a single layer or a double layer structure.

Referring to FIG. 4B, a gate insulating layer 16 is stacked on a lower substrate 14 on which gate metal patterns are formed, and an odd shorting bar 8, data lines 2 and 4, a semiconductor layer, and a source are disposed thereon. Source / drain metal patterns including the electrode 9, the storage electrode 17, and the drain electrode 11 are stacked.

The gate insulating layer 16 is formed by depositing a gate insulating material on the entire surface by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). As the gate insulating material, silicon oxide (SiOx) or silicon nitride (SiNx) is used. Subsequently, an amorphous silicon layer and an n + amorphous silicon layer are sequentially stacked on the gate insulating layer 16, and then patterned by an photolithography process and an etching process using a second mask to form an active layer and an ohmic contact layer in the array shown in FIG. 2. To form.

The source / drain metal patterns are formed by depositing the source / drain metal material on the gate insulating layer 16 by a deposition method such as sputtering, and then patterning the photo / lithography process and etching process using a third mask. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal.

Referring to FIG. 4C, a passivation layer 18 including a plurality of contact holes 12, 13, 21, and 29 is formed.

The protective film 18 is formed by entirely depositing an insulating material by a deposition method such as PECVD. As the insulating material of the protective film 18, an inorganic insulating material such as the gate insulating film 16 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used. The fourth contact hole 12 of the even shorting bar 6, the contact hole 13 of the drain electrode 11, the contact hole 21 of the storage electrode 19, and the contact hole 29 of the data pad 25. They are formed by patterning the passivation layer 18 and the gate insulating layer 16 by a photolithography process and an etching process using a fourth mask.

Referring to FIG. 4D, a pixel electrode 15, a data pad protection electrode 27, and a contact electrode 10 connected to electrodes, pads, and shorting bars through a plurality of contact holes 12, 13, 21, and 29 are included. Transparent electrode patterns are formed.

The transparent electrode pattern is formed by depositing a transparent electrode material on the passivation layer 18 by a deposition method such as sputtering, and then patterning the photoresist process and etching process using a fifth mask. Indium tin oxide (ITO), tin oxide (TO) or indium zinc oxide (IZO) is used as the transparent electrode material.

A plurality of thin film transistor array panels formed on such a large glass substrate are laminated with a plurality of metal layers by a technique such as PECVD during the manufacturing process. At this time, since the plasma is a particle having a polarity, when the plasma particles are accelerated to pattern the metal layer on the substrate, the movement direction of the particles is changed by the potential difference. As a result, a loading effect is generated, which is a distortion phenomenon in which plasma particles are bent to the glass substrate on the outer side of the thin film transistor array panels 53a and 53b in which many metal patterns exist. As a result, as shown in FIG. 1, patterns formed near and above the large glass substrate 51 among the plurality of thin film transistor array panels 53a and 53b are added with plasma particles that are curved toward the glass substrate. More etched excess etched portions 52,54 are created. The excessive etching portions 52 and 54 may be a generation site of irregular spots when driving the liquid crystal panel at low temperature.

Accordingly, an object of the present invention is to provide a thin film transistor array substrate and a method for manufacturing the same, which can prevent loading effects by forming an equipotential pattern between thin film transistor array substrate regions during a manufacturing process.

In order to achieve the above object, a thin film transistor array substrate according to the present invention is a thin film having a substrate, a plurality of thin film transistors formed on the substrate and a plurality of data lines connected to the thin film transistor to apply a data signal, respectively And an equipotential pattern formed at an edge of the substrate to form an equipotential with the transistor array panel and the thin film transistor array panel.

In the thin film transistor array substrate according to the present invention, the equipotential pattern is characterized by including a plurality of stripe patterns parallel to the data lines of the thin film transistor array panel.

In the thin film transistor array substrate according to the present invention, the width of each of the equipotential patterns is the same as the pattern width of the data line.

In the thin film transistor array substrate according to the present invention, each of the equipotential patterns is positioned on the same layer as the data line.

In the thin film transistor array substrate according to the present invention, the material of the equipotential pattern is the same as that of the source / drain metal layer.

A method of manufacturing a thin film transistor array substrate according to the present invention includes the steps of providing a plurality of thin film transistor array panels each having a plurality of thin film transistors formed on the substrate and a plurality of data lines connected to the thin film transistors to apply a data signal; And forming an equipotential pattern at an edge of the substrate to form an equipotential with the thin film transistor array panel.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the equipotential pattern is characterized by consisting of a plurality of stripe patterns parallel to the data line.

In the method of manufacturing a thin film transistor array substrate according to the present invention, each of the equipotential patterns is formed to have the same width as the pattern width of the data lines.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the equipotential pattern is formed of the same material as the source / drain metal layer.

In the method of manufacturing a thin film transistor array substrate according to the present invention, each of the equipotential patterns is formed on the same layer as the data line.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the forming of the data lines, the thin film transistors, and the equipotential pattern includes a gate line intersecting the data line on the substrate and a gate electrode included in the thin film transistor. Forming a gate pattern; depositing a gate insulating film on the substrate on which the gate patterns are formed; forming a semiconductor pattern forming a channel of the thin film transistor on the gate insulating film; and forming a gate insulating film on which the semiconductor pattern is formed. And forming source / drain metal patterns including data lines, source and drain electrodes included in the thin film transistor, and an equipotential pattern.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIG. 5.

FIG. 5 is a plan view illustrating a large glass substrate on which thin film transistor array panels including a dummy pattern according to an exemplary embodiment of the present invention are formed.

In this case, since the thin film transistor array panels 53 are the same as in the related art, the thin film transistor array substrate according to the exemplary embodiment of the present invention may be manufactured by only modifying the dummy pattern 57a and 57b production masks.

Referring to FIG. 5, the dummy patterns 57a and 57b formed on the upper and lower sides of the large glass substrate 51 have the same pattern as the source line and drain of the data line 3 of the thin film transistor array panel 53, unlike the conventional cylindrical pattern. The metal is patterned. That is, the same stripe pattern as the data line 3 is provided.

Since the dummy patterns 57a and 57b are formed of a plurality of stripe patterns made of source / drain metals, they are formed together when forming the source / drain metal patterns during thin film transistor array substrate fabrication. Since the dummy patterns 57a and 57b are formed at the same size and spacing as the source / drain metal patterns of the thin film transistor array panels 53a and 53b, the dummy patterns 57a and 57b form an equipotential pattern that forms an equipotential with the thin film transistor array panel 53. That is, they are formed with the same size and spacing as the data lines, which are patterns formed of source / drain metal. Accordingly, even if a phenomenon in which the plasma particles are bent to the outer glass substrate during the process occurs, an excessive etching portion is generated only on the dummy patterns 57a and 57b.

Accordingly, the thin film transistor array substrate according to the embodiment of the present invention includes a dummy pattern formed of a plurality of stripe patterns identical to the source / drain pattern of the thin film transistor array panel, thereby over-etching portions generated in the outer portion of the conventional thin film transistor array panel. Occurrence is prevented.

In this case, the thin film transistor array panel is divided into source / drain patterns formed in the active region 53a which is a screen display area, and areas in which patterns such as a data pad part and a shorting bar, which are inactive regions 53b, are formed.

However, the source / drain pattern area of the active region 53a is different from the source / drain pattern area present in the inactive region 53b. The area difference between the source / drain patterns in these two regions affects the equipotential with the dummy patterns 57a and 57b formed adjacent to these two regions. Accordingly, it is necessary to determine the areas of the dummy patterns 57a and 57b formed to be close to the two areas in consideration of the area difference between the source / drain patterns of the two areas.

In detail, if the source / drain pattern area of the active region 53a is A and the source / drain pattern area of the non-active region 53b is B, it is closer to the upper side of the large glass substrate 51. The area of the source / drain pattern formed is B + 0.5A, and the area of the source / drain pattern formed adjacent to the lower side is about 0.5A. Therefore, the thin film transistor array panel and the dummy pattern may have an equipotential by forming the area of the dummy pattern formed on the upper side and the lower side in proportion thereto.

As a result, the thin film transistor array substrate according to the embodiment of the present invention includes a dummy pattern composed of a plurality of patterns of the same pattern as the source / drain pattern, thereby preventing the occurrence of an excessive etching portion of the thin film transistor array panel. Therefore, in the thin film transistor array substrate according to the embodiment of the present invention, occurrence of irregular irregularities in the liquid crystal panel is prevented.

As described above, the thin film transistor array substrate and the method of manufacturing the same according to an embodiment of the present invention is provided with a dummy pattern composed of a plurality of stripe patterns identical to the source / drain pattern of the thin film transistor array panel to overetch the thin film transistor array panel. It will prevent the occurrence of negative. As a result, the thin film transistor array substrate according to the embodiment of the present invention is prevented the occurrence of irregular irregularities in the liquid crystal panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing a large glass substrate on which a plurality of conventional thin film transistor array panels are located;

FIG. 2 is a plan view of the region “R” of FIG. 1. FIG.

3 is a cross-sectional view of the region shown in FIG. 2 taken along line A-A ', B-B', C-C ', and D-D'.

4A through 4E are cross-sectional views illustrating a method of manufacturing the region shown in FIG.

5 is a plan view illustrating a thin film transistor array substrate including an equipotential pattern according to an exemplary embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

1: gate line 2: aod data line

3: data line 4: even data line

5: thin film transistor 6: Even shorting bar

7 gate electrode 8 electrode shorting bar

9 source electrode 10 contact electrode

11 drain electrode 12 fourth contact hole

13: first contact hole 14: lower substrate

15 pixel electrode 16 gate insulating film

17: storage capacitor 18: protective film

19: storage electrode 21: second contact hole

23: Data Link 25: Data Pad

27: data pad protective electrode 29: third contact hole

31: data pad portion 51: large glass substrate

52, 54: over-etching part 53: thin film transistor array panel

57a, 57b: equipotential patterns

Claims (11)

Substrate, A plurality of thin film transistor array panels each having a plurality of thin film transistors formed on the substrate and a plurality of data lines connected to the thin film transistors to apply a data signal; And an equipotential pattern formed at an edge of the substrate to form an equipotential with the thin film transistor array panel. The method of claim 1, The equipotential pattern is, And a plurality of stripe patterns parallel to the data lines of the thin film transistor array panel. The method of claim 2, The width of each of the equipotential patterns is the same as the pattern width of the data line. The method of claim 2, Each of the equipotential patterns is on the same layer as the data line. The method of claim 2, The material of the equipotential pattern is a thin film transistor array substrate, characterized in that the same as the source / drain metal layer. Providing a plurality of thin film transistor array panels each having a plurality of thin film transistors formed on a substrate and a plurality of data lines connected to the thin film transistors to apply a data signal; And forming an equipotential pattern at an edge of the substrate to form an equipotential with the thin film transistor array panel. The method of claim 6, The equipotential pattern is, And a plurality of stripe patterns parallel to the data lines. The method of claim 7, wherein And each of the equipotential patterns is formed to have the same width as the pattern width of the data lines. The method of claim 7, wherein The equipotential pattern is a thin film transistor array substrate manufacturing method, characterized in that formed of the same material as the source / drain metal layer. The method of claim 7, wherein Each of the equipotential patterns is formed on the same layer as the data line. The method of claim 6, Forming the data lines, the thin film transistors, and the equipotential pattern on the substrate Forming gate patterns on the substrate, the gate patterns including a gate line crossing the data line and a gate electrode included in the thin film transistor; Depositing a gate insulating film on the substrate on which the gate patterns are formed; Forming a semiconductor pattern to form a channel of the thin film transistor on the gate insulating layer; Forming source / drain metal patterns including the data line, source and drain electrodes included in the thin film transistor, and an equipotential pattern on the gate insulating layer on which the semiconductor pattern is formed. Manufacturing method.