CN110071119A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN110071119A CN110071119A CN201910279172.XA CN201910279172A CN110071119A CN 110071119 A CN110071119 A CN 110071119A CN 201910279172 A CN201910279172 A CN 201910279172A CN 110071119 A CN110071119 A CN 110071119A
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- telltale mark
- metal layer
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- array substrate
- capacitor
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
Abstract
The present invention provides a kind of array substrate and display panel, the array substrate includes gate driving circuit area and viewing area, the gate driving circuit area includes the first metal layer and second metal layer, the first metal layer is equipped with public cabling and the first pole plate, the second metal layer is equipped with the second pole plate, and first pole plate and second pole plate form capacitor；Wherein, at least one telltale mark is set to the region of the corresponding capacitor；By the region that telltale mark is set to the corresponding capacitor, so that telltale mark is close to grid cabling, facilitate localization examination, and since telltale mark is set to the region of the corresponding capacitor, public cabling can overstriking, the stability for improving public cabling solves existing GOA circuit framework and there is the unreasonable technical problem of design.
Description
Technical field
The present invention relates to field of display technology, more particularly, to a kind of array substrate and display panel.
Background technique
GOA circuit (Gate Driver On Array, gate driving circuit), i.e., make gate line scanning drive signal
In array substrate, the driving method that progressively scan to grid is realized, since it is few with process, achievable narrow frame etc.
Advantage is widely used.
As shown in Figure 1 and Figure 2, in conventional GOA circuit, grid line 13 is connected to by via hole again across public cabling 14
In viewing area 11, the people in order to facilitate engineering section checks and label, can represent corresponding grid series by label by public cabling
Number and arrow, however this mark mode will affect the stability of public cabling.
So existing GOA circuit framework, which exists, designs unreasonable technical problem.
Summary of the invention
The present invention provides a kind of array substrate and display panel, does not conform to for solving existing GOA circuit framework in the presence of design
The technical issues of reason.
To solve the above problems, technical solution provided by the invention is as follows:
The present invention provides a kind of array substrate, which includes gate driving circuit area and viewing area, the grid
Drive circuit area includes:
The first metal layer is equipped with public cabling and the first pole plate；
Second metal layer, is equipped with the second pole plate, and first pole plate forms capacitor in second pole plate；
Wherein, at least one telltale mark is set to the region of the corresponding capacitor.
In array substrate provided by the invention, the telltale mark for being set to the region of the corresponding capacitor is set to first
Metal layer.
In array substrate provided by the invention, the telltale mark for being set to the region of the corresponding capacitor is set to second
Metal layer.
In array substrate provided by the invention, is etched in second metal layer or deposition forms telltale mark.
In array substrate provided by the invention, the array substrate further includes gate insulating layer, is set to described in corresponding to
The telltale mark in the region of capacitor is set to gate insulating layer.
In array substrate provided by the invention, at least one telltale mark is set to corresponding left side gate driving circuit area
The region of middle capacitor.
In array substrate provided by the invention, the telltale mark is all set in the region of the corresponding capacitor.
In array substrate provided by the invention, it is set to determining for the region of capacitor in corresponding left side gate driving circuit area
Position label is set to the first metal layer, is set to the telltale mark setting in the region of capacitor in corresponding right side gate driving circuit area
In second metal layer.
In array substrate provided by the invention, the telltale mark same layer setting.
Meanwhile the present invention provides a kind of display panel, which includes any above-mentioned array substrate.
The utility model has the advantages that it includes gate driving circuit that the present invention, which provides a kind of array substrate and display panel, the array substrate,
Area and viewing area, the gate driving circuit area include the first metal layer and second metal layer, and the first metal layer is equipped with public affairs
Cabling and the first pole plate altogether, the second metal layer are equipped with the second pole plate, and first pole plate and second pole plate form electricity
Hold；Wherein, at least one telltale mark is set to the region of the corresponding capacitor；By the way that telltale mark is set to described in correspondence
The region of capacitor, so that telltale mark facilitates localization examination close to grid cabling, and since telltale mark is set to described in correspondence
The region of capacitor, public cabling can overstriking, improve the stability of public cabling, solve existing GOA circuit framework and exist and set
Count unreasonable technical problem.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is display panel schematic diagram in the prior art；
Fig. 2 is display panel GOA circuit diagram in the prior art；
Fig. 3 is the first schematic diagram of array substrate in the embodiment of the present invention；
Fig. 4 is the second schematic diagram of array substrate in the embodiment of the present invention；
Fig. 5 is array substrate third schematic diagram in the embodiment of the present invention；
Fig. 6 is the 4th schematic diagram of array substrate in the embodiment of the present invention；
Fig. 7 is the 5th schematic diagram of array substrate in the embodiment of the present invention；
Fig. 8 is liquid crystal display panel schematic diagram in the embodiment of the present invention；
Fig. 9 is OLED display panel schematic diagram in the embodiment of the present invention.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention exists for existing GOA circuit framework designs unreasonable technical problem, and the embodiment of the present invention is to solve
The certainly problem.
As shown in Figure 1 and Figure 2, existing display panel includes viewing area 11, GOA circuit region 12, and the GOA circuit region 12 is set
There is capacitor 15, then the grid line 13 that the GOA circuit region 12 is drawn is linked into viewing area by via hole across public cabling 14
In pixel 111 in 11, so that GOA circuit drives pixel light emission.
Existing display panel can mark corresponding grade at every level-one grid line in order to facilitate people's localization examination of engineering section
Number, as shown in Fig. 2, arrow in figure and letter a indicate that the grid line for a grades of grid lines, but arrow and represents series
Letter can occupy biggish space so that public cabling is thinner, to influence the stability of public cabling, and by arrow and
The capacitor that will affect public cabling on public cabling is arranged in the letter for representing series, i.e., there are framework presence for existing GOA circuit
Design unreasonable problem.
As shown in figure 3, the embodiment of the present invention provides a kind of array substrate, which includes that viewing area 21 and grid drive
Dynamic circuit region 22, the grid line 23 that the gate driving circuit area 22 is equipped with capacitor 25, the gate driving circuit is drawn across
Then public cabling 24 is linked into the pixel 211 in viewing area 21 by via hole, so that gate driving circuit driving pixel hair
Light.
In one embodiment, as shown in figure 3, telltale mark 26 to be set to the region of corresponding capacitor, so that positioning mark
Remember close to corresponding grid line, is not in read error, facilitates the corresponding grid series of localization examination, and telltale mark is set
Be placed in the region of corresponding capacitor, the public cabling of corresponding position can overstriking, to improve the stability of public cabling.
As shown in Fig. 4, Fig. 5, Fig. 6, the embodiment of the present invention provides array substrate, which includes gate driving circuit
Area and viewing area, the gate driving circuit area include:
The first metal layer 31 is equipped with public cabling 312 and the first pole plate 311；
Second metal layer 32, is equipped with the second pole plate 321, and first pole plate 311 forms electricity with second pole plate 321
Hold；
Wherein, at least one telltale mark 323 is set to the region of the corresponding capacitor.
The embodiment of the present invention provides a kind of array substrate, which includes gate driving circuit area and viewing area, institute
Stating gate driving circuit area includes the first metal layer and second metal layer, and the first metal layer is equipped with public cabling and the first pole
Plate, the second metal layer are equipped with the second pole plate, and first pole plate and second pole plate form capacitor；Wherein, at least one
A telltale mark is set to the region of the corresponding capacitor；By the way that telltale mark to be set to the region of the corresponding capacitor, make
It obtains telltale mark and facilitates localization examination close to grid cabling, and since telltale mark is set to the region of the corresponding capacitor, it is public
Altogether cabling can overstriking, improve the stability of public cabling, solve existing GOA circuit framework and exist and design unreasonable technology
Problem.
In one embodiment, as shown in figure 4, the telltale mark that will be set to the region of the corresponding capacitor is set to the
Two metal layers, so that telltale mark facilitates localization examination close to corresponding grid line, and corresponding public cabling is due to being not necessarily to
Telltale mark is set in side, public cabling overstriking to improve public cabling stability, can be solved GOA circuit framework
Design unreasonable technical problem.
In one embodiment, the telltale mark for being set to the region of corresponding capacitor is set to the first metal layer.
In one in embodiment, as shown in figure 5, the telltale mark that will be set to the region of the corresponding capacitor is set to the
The telltale mark 324 in the not set region in the correspondence capacitor is set to second metal layer, by that will not set by two metal layers
The telltale mark for being placed in the region of the corresponding capacitor is set to second metal layer, enables the whole overstriking of public cabling, into
One step improves the stability of public cabling.
In one embodiment, part telltale mark can be set to the region of the corresponding capacitor in array substrate,
Part telltale mark is set to the region of corresponding public cabling, then in the array substrate public cabling can whole overstriking, thus
The stability of public cabling is improved, and the telltale mark for being set to the region of the corresponding capacitor can be set to the first metal
Layer, the telltale mark that will be set to the region of corresponding public cabling are set to second metal layer, or by all telltale marks
It is all set in second metal layer, position is arranged in the unlimited telltale mark processed of the embodiment of the present invention, to be actually able to solve GOA circuit frame
Structure designs the position of setting telltale mark on the basis of unreasonable technical problem.
In one embodiment, all telltale marks are set to the region of corresponding shown capacitor, so that all determines
Position is marked close to corresponding grid line, so that the people's localization examination and label of engineering section, and enable public cabling whole
It is unreasonable to solve the problems, such as that existing GOA circuit framework designs to improve the stability of public cabling for body overstriking.
In one embodiment, as shown in fig. 6, being set to determining for the region of capacitor in corresponding left side gate driving circuit area
Position label is set to the first metal layer, and the telltale mark for being set to capacitor in corresponding right side gate driving circuit area is set to second
Metal layer, by the way that telltale mark to be set to the region of corresponding capacitor, so that telltale mark is closer apart from corresponding grid line, from
And facilitate the people's localization examination and label of engineering section, and corresponding public cabling overstriking, the stability of public cabling is improved,
It is unreasonable to solve the problems, such as that existing GOA circuit framework designs.
In one embodiment, determining for gate driving circuit area on the left of corresponding can will be set to when forming the first metal layer
Position label is formed on the first metal layer surface, and gate driving electricity on the right side of corresponding then will be set to when forming second metal layer
The telltale mark in road area is formed in second metal layer surface.
As shown in fig. 7, the embodiment of the present invention provides a kind of array substrate, which includes the first metal layer 31,
Two metal layers 32 and gate insulating layer 33, the first metal layer 31 are equipped with the first pole plate 311 and public cabling 312, institute
It states second metal layer 32 and is equipped with the second pole plate 321 and grid line 322, first pole plate 311 and 321 shape of the second pole plate
At capacitor, the gate insulating layer 33 is equipped with telltale mark 331, the telltale mark in the region by that will be set to corresponding capacitor
It is arranged on gate insulating layer, so that telltale mark is easy to be read and do not interfere with the capacitor of public cabling, and corresponding
Public cabling energy overstriking, improve the stability of public cabling.
As shown in figure 8, the embodiment of the present invention provides a kind of liquid crystal display panel, which includes array base
Plate, liquid crystal 43 and color membrane substrates 44, the array substrate include underlay substrate 41 and thin film transistor array layer 42, the array
Barricade is equipped between substrate and the color membrane substrates 44, by the way that any of the above-described array substrate is set to the liquid crystal display panel,
So that telltale mark facilitates localization examination, and corresponding public cabling energy overstriking in the GOA circuit of the display panel, improve public
The stability of cabling altogether.
In one embodiment, telltale mark can be set to barricade to correspond on the region of capacitor, for LCD display
There are will use barricade during array substrate and color membrane substrates pairing to prevent liquid crystal from exposing in plate, telltale mark setting is existed
Barricade corresponds on the region of capacitor, so that telltale mark does not interfere with the arrangement of array substrate, and telltale mark will not influence
To the operation of GOA circuit so that without by telltale mark setting it is public walk line side, to not interfere with the electricity of public cabling
Hold, and can the public cabling of overstriking, improve the stability of public cabling.
As shown in figure 9, the embodiment of the present invention provides a kind of OLED display panel, which includes substrate, drives
Dynamic circuit layer, pixel defining layer, luminescent layer, the substrate include substrate 511, barrier layer 512, first grid insulating layer 513, the
Two gate insulating layers 514, interlayer insulating film 515, planarization layer 516 and pixel defining layer 517, the drive circuit layer include
Active layer 520, source electrode 521, drain electrode 522, the first metal layer 523 and second metal layer 524, the luminescent layer include luminescence unit and
Common electrode layer 630, the luminescence unit include anode layer 610 and luminous material layer 620.
In one embodiment, for display panel, the telltale mark for being set to the region of corresponding capacitor is set to
Perhaps second metal layer is equipped with circuit devcie or circuit trace to one metal layer on the first metal layer and second metal layer,
While not influencing circuit, telltale mark is arranged on the first metal layer or second metal layer, so that telltale mark is conducive to work
The people of journey section marks and checks, and can the corresponding public cabling of overstriking, he improves the stability of public cabling, solve existing
GOA circuit framework has that design is unreasonable.
In one embodiment, the telltale mark for being set to the region of corresponding capacitor is set to first grid insulating layer,
In the case where not interfering with source electrode, drain electrode and active layer, telltale mark is set to first grid insulating layer, so that it is being solved
While certainly existing GOA circuit framework designs unreasonable technical problem, the first metal layer and the bimetallic normal is not influenced
Operation.
In one embodiment, by the telltale mark for being set to the region of corresponding capacitor be set to second grid insulating layer or
Person's interlayer insulating film corresponds to the region of capacitor, then corresponding public cabling overstriking increases stability, alleviates existing GOA
Circuit framework has that design is unreasonable.
In one embodiment, by telltale mark be set to substrate, barrier layer, active layer, flatness layer, pixel defining layer and
At least one layer in luminescent layer corresponds to the region of capacitor, so that telltale mark is conducive to people's label of engineering section and checks, and can
The corresponding public cabling of overstriking, improves the stability of public cabling, and it is unreasonable in the presence of designing to solve existing GOA circuit framework
The problem of.
The embodiment of the present invention provides display panel, which includes any of the above-described array substrate, the array base
Plate includes gate driving circuit area and viewing area, and the gate driving circuit area includes the first metal layer and second metal layer, institute
The first metal layer is stated equipped with public cabling and the first pole plate, the second metal layer is equipped with the second pole plate, first pole plate with
Second pole plate forms capacitor；Wherein, at least one telltale mark is set to the region of the corresponding capacitor；By that will position
Label is set to the region of the corresponding capacitor, so that telltale mark facilitates localization examination close to grid cabling, and due to positioning
Label is set to the region of the corresponding capacitor, public cabling can overstriking, improve the stability of public cabling, solve existing
GOA circuit framework, which exists, designs unreasonable technical problem.
For the prior art due to the limitation of position, the label of setting is smaller, and in embodiments of the present invention, telltale mark is set
It sets in the region of corresponding capacitor, so that telltale mark can increase accordingly the size of telltale mark according to the size of capacitor, thus
So that telltale mark is high-visible, facilitate the people's localization examination and label of engineering section.
In one embodiment, when making telltale mark, the corresponding capacitor of formation can be etched in second metal layer
Region telltale mark, the telltale mark for forming the region of the corresponding capacitor can also be deposited in second metal layer, may be used also
Hollow out second metal layer forms telltale mark, and the size of telltale mark is formed according to capacitance size, so that telltale mark is clear
As it can be seen that facilitating the people's localization examination and label of engineering section, it is unreasonable to solve the problems, such as that existing GOA circuit framework has design.
It in one embodiment, can be by the telltale mark in the region of the correspondence capacitor and the region for not corresponding to the capacitor
Telltale mark different layers setting.
In one embodiment, all telltale mark same layer is arranged, such as by all telltale mark settings the
One metal layer, so that technique is simplified, without repeatedly forming telltale mark.
In one embodiment, all telltale mark same layer is arranged, it, can will be all when forming the first metal layer
Telltale mark, which is deposited on, corresponds to the region surface of capacitor in the first metal layer, or by etching on the capacitor of corresponding grid line
Or hollow out metal layer forms the telltale mark for corresponding to grid line series；Also the can be being formed after forming the first metal layer
When two metal layers, telltale mark deposition is formed in the surface of second metal layer, wherein part telltale mark is deposited on the second gold medal
Belong to the region that layer corresponds to capacitor, either etching or hollow out second metal layer form telltale mark, part of telltale mark position
The region of capacitor is corresponded in second metal layer, the position of the unlimited telltale mark processed of the embodiment of the present invention is guaranteeing that at least one is fixed
It is fixed with preparation method preparation easy as far as possible according to actual fabrication process while position label is set to the region of corresponding capacitor
Position label, and the operation of circuit is not influenced.
According to above embodiments:
The embodiment of the present invention provides a kind of array substrate and display panel, the array substrate include gate driving circuit area and
Viewing area, the gate driving circuit area include the first metal layer and second metal layer, the first metal layer be equipped with it is public walk
Line and the first pole plate, the second metal layer are equipped with the second pole plate, and first pole plate and second pole plate form capacitor；Its
In, at least one telltale mark is set to the region of the corresponding capacitor；By the way that telltale mark is set to the corresponding capacitor
Region so that telltale mark close to grid cabling, facilitates localization examination, and since telltale mark is set to the corresponding capacitor
Region, public cabling can overstriking, improve the stability of public cabling, solve existing GOA circuit framework and there is design not
Reasonable technical problem.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate, which is characterized in that including gate driving circuit area and viewing area, the gate driving circuit area packet
It includes:
The first metal layer is equipped with public cabling and the first pole plate；
Second metal layer, is equipped with the second pole plate, and first pole plate and second pole plate form capacitor；
Wherein, at least one telltale mark is set to the region of the corresponding capacitor.
2. array substrate as described in claim 1, which is characterized in that be set to the telltale mark in the region of the corresponding capacitor
It is set to the first metal layer.
3. array substrate as described in claim 1, which is characterized in that be set to the telltale mark in the region of the corresponding capacitor
It is set to second metal layer.
4. array substrate as claimed in claim 3, which is characterized in that etch or deposit formation positioning in second metal layer
Label.
5. array substrate as described in claim 1, which is characterized in that the array substrate further includes gate insulating layer, setting
Telltale mark in the region of the correspondence capacitor is set to gate insulating layer.
6. array substrate as described in claim 1, which is characterized in that at least one telltale mark is set to corresponding left side grid
The region of capacitor in drive circuit area.
7. array substrate as described in claim 1, which is characterized in that the telltale mark is all set in the corresponding capacitor
Region.
8. array substrate as claimed in claim 7, which is characterized in that be set to capacitor in corresponding left side gate driving circuit area
The telltale mark in region be set to the first metal layer, be set to determining for the region of capacitor in corresponding right side gate driving circuit area
Position label is set to second metal layer.
9. array substrate as claimed in claim 7, which is characterized in that the telltale mark same layer setting.
10. a kind of display panel, which is characterized in that including array substrate as described in any one of claim 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910279172.XA CN110071119B (en) | 2019-04-09 | 2019-04-09 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910279172.XA CN110071119B (en) | 2019-04-09 | 2019-04-09 | Array substrate and display panel |
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|---|---|
| CN110071119A true CN110071119A (en) | 2019-07-30 |
| CN110071119B CN110071119B (en) | 2021-07-06 |
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| CN201910279172.XA Active CN110071119B (en) | 2019-04-09 | 2019-04-09 | Array substrate and display panel |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110518022A (en) * | 2019-09-10 | 2019-11-29 | 合肥京东方卓印科技有限公司 | Gate drive configuration, array substrate and display device |
| CN110888250A (en) * | 2019-11-19 | 2020-03-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN110989228A (en) * | 2019-12-06 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111128965A (en) * | 2019-12-16 | 2020-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| JP2006243007A (en) * | 2005-02-28 | 2006-09-14 | Optrex Corp | Liquid crystal display element |
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| CN111128965A (en) * | 2019-12-16 | 2020-05-08 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111128965B (en) * | 2019-12-16 | 2022-05-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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