CN110888250A - Display panel - Google Patents
Display panel Download PDFInfo
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- CN110888250A CN110888250A CN201911134325.8A CN201911134325A CN110888250A CN 110888250 A CN110888250 A CN 110888250A CN 201911134325 A CN201911134325 A CN 201911134325A CN 110888250 A CN110888250 A CN 110888250A
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- Prior art keywords
- display panel
- common electrode
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- layer
- display area
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- 239000002184 metal Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 238000007689 inspection Methods 0.000 abstract description 3
- 239000010409 thin film Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The utility model provides a display panel, including set up in gate drive circuit, a plurality of pixel unit, many scanning lines in non-display area, set up in gate drive circuit with common electrode between the display area and with a plurality of location marks that the different layer of common electrode set up, the first end of scanning line is connected gate drive circuit, the second end extends to in the display area, the location mark is in orthographic projection on the common electrode is located in the common electrode, and is close to correspondingly the scanning line. The positioning mark and the public electrode are arranged in different layers, and the orthographic projection of the positioning mark is arranged in the public electrode, so that the space can be saved, the wiring of the public electrode is thickened, the stability of the public electrode is improved, the positioning mark can be close to a scanning line, and the inspection and marking of workers are facilitated.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel.
Background
The goa (gate Driver On array) technology uses the array process in the thin film transistor liquid crystal display to make the line scanning driving signal circuit On the array substrate, so as to realize the driving mode of scanning the grid line by line.
In a conventional GOA circuit design, a common electrode is disposed between a GOA circuit and a display area, and in a display panel, the more stable the common electrode is, the better the common electrode is, and it is a common practice to thicken the common electrode so that a capacitance formed by the common electrode and an upper plate is increased. However, grid level marks are generally made near the common electrode, and the purpose of this is to facilitate personnel in the engineering section to locate and check the corresponding grid level, which occupies the space of the common electrode. To solve this problem, it is common practice to mark the side of the sectioning line, so that although space is made available for the common electrode, the mark is too far from the display area to facilitate human positioning of the engineering section; alternatively, the common electrode can be marked directly, which makes room for it, but which interferes with the capacitance of the common electrode to some extent.
Disclosure of Invention
The invention provides a display panel, which aims to solve the technical problems that in the existing display panel, because a common electrode is arranged between a GOA circuit and a display area, grid stage number marks are usually made near the common electrode, so that personnel in a project section can conveniently position and check corresponding grid stage numbers, but the marks occupy the space of the common electrode, influence the stability of the common electrode and further influence the display.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a display panel, which comprises a display area and a non-display area, wherein the display panel comprises a substrate, a grid drive circuit arranged in the non-display area, a plurality of pixel units arranged in the display area, a plurality of scanning lines arranged on the substrate, a common electrode arranged between the grid drive circuit and the display area, and a plurality of positioning marks arranged in a different layer with the common electrode; the first end of the scanning line is connected with the grid driving circuit, and the second end of the scanning line extends into the display area; wherein, the orthographic projection of the positioning mark on the common electrode is positioned in the common electrode and close to the corresponding scanning line.
In at least one embodiment of the present invention, the positioning mark is disposed in the same layer as any one of the amorphous silicon layer, the pixel electrode layer, the color resist layer, and the support pad on the display panel.
In at least one embodiment of the present invention, the display panel further includes a first metal layer disposed on the substrate base and a second metal layer disposed on the first metal layer.
In at least one embodiment of the present invention, the scan lines include first signal lines and second signal lines disposed in different layers, and the first signal lines and the second signal lines are connected by vias.
In at least one embodiment of the present invention, the first signal line and the second metal layer are disposed on the same layer and connected to the gate driving circuit, and the second signal line and the first metal layer are disposed on the same layer and extend to the display region.
In at least one embodiment of the present invention, the common electrode and the first metal layer are disposed in the same layer.
In at least one embodiment of the present invention, the positioning marks include numerical marks and arrow marks.
In at least one embodiment of the present invention, the display panel further includes a dummy pixel unit disposed at an edge of the display area.
In at least one embodiment of the present invention, a scan line is electrically connected to a plurality of pixel units in the same row and is insulated from the dummy pixel units in the row.
In at least one embodiment of the present invention, the pixel unit includes a main pixel region and a sub pixel region, and the scan line is disposed between the main pixel region and the sub pixel region in a row direction.
In at least one embodiment of the present invention, the display panel further includes a control board, a source board connected to the control board, a WOA wiring area connected to the source board and arranged in a fan shape, and a plurality of data lines connected to the WOA wiring area
The invention has the beneficial effects that: the positioning mark and the public electrode are arranged in different layers, and the orthographic projection of the positioning mark is arranged in the public electrode, so that the space can be saved, the wiring of the public electrode is thickened, the stability of the public electrode is improved, the positioning mark can be close to a scanning line, and the inspection and marking of workers are facilitated.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a GOA circuit to a display area according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a thin film transistor according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Aiming at the existing display panel, because a common electrode is arranged between the GOA circuit and the display area, grid stage number marks are usually made near the common electrode, so that personnel in engineering sections can conveniently position and check the corresponding grid stage number, but the marks occupy the space of the common electrode, influence the stability of the common electrode and further influence the display, and the technical problem can be solved by the embodiment.
As shown in fig. 1 and fig. 2, an embodiment of the invention provides a display panel 100, which includes a display area 101 and a non-display area 102, where the display area 101 is used for displaying, and the non-display area 102 is used for routing and setting a driving circuit. The display panel 100 includes a gate driving circuit 10 disposed in a non-display region 102, a plurality of pixel units 40 disposed in a display region 101, a plurality of scan lines 20, a common electrode 30, and a plurality of positioning marks 80.
The scan lines 20 are horizontally arranged in parallel, a first end of each scan line 20 is connected to the gate driving circuit 10, and a second end of each scan line 20 extends into the display region 101.
The pixel units 40 can be distributed in the display area 101 in an array manner, and one scanning line 20 is connected to the pixel units 40 in the same row, so that row driving of the gates of the pixel units 40 is realized.
One common electrode 30 is disposed between the gate driving circuit 10 and the display region 101, and thus the scan line 20 needs to cross the common electrode 30 and enter the display region 101. Generally, in order to facilitate the positioning and checking of the personnel in the engineering section, the positioning mark 80 is arranged at each stage to mark the corresponding stage number, and if the positioning mark 80 is arranged at one side of the common electrode 30, the space of the common electrode 30 is occupied, so that the routing of the common electrode 30 cannot be wider, and the stability of the common electrode 30 is affected; if the positioning mark 80 is directly disposed on the common electrode 30, a certain interference may be generated on the capacitance formed by the common electrode 30, and thus, the embodiment of the present invention improves the stability of the common electrode 30.
The positioning mark 80 is disposed in a different layer from the common electrode 30, so as to make a space for the common electrode 30, so that the common electrode 30 can be thickened, thereby enhancing the stability of the common electrode 30.
The orthographic projection of the positioning mark 80 on the common electrode 30 is located in the common electrode 30 and close to the corresponding scanning line 20. The positioning marks include a number mark n that marks the corresponding gate stage number and an arrow mark whose direction points to the scanning line 20 of the corresponding stage number.
The embodiment of the present invention is described by taking an lcd panel with a resolution of UD (3840 × 2160) as an example, that is, the lcd panel 100 includes 3840 data lines and 2160 scan lines. One of the pixel units 40 may be any one of a red pixel unit, a green pixel unit, and a blue pixel unit. The pixel unit 40 has an eight-domain 3T pixel structure, the pixel unit 40 includes a main pixel region 401 and a sub-pixel region 402, and the scan line 20 is located between the main pixel region 401 and the sub-pixel region 402.
The pixel unit 40 includes a pixel electrode layer and three thin film transistors (a main area thin film transistor, a sub area thin film transistor, and a shared thin film transistor), the pixel electrode layer includes a main pixel electrode 41 and a sub pixel electrode 42 the main pixel electrode 41 and the sub pixel electrode 42 divide the pixel unit into eight domains, the main pixel electrode 41 and the sub pixel electrode 42 have the same structure, and include a cross-shaped main electrode and branch electrodes extending from the main electrode into each domain, so as to improve the dark fringe phenomenon generated by the liquid crystal molecules at the edge of the pixel unit due to the unsatisfactory deflection.
As shown in fig. 3, the thin film transistor includes a gate electrode 43, an amorphous silicon layer 44 disposed on the gate electrode 43, an N-type doped amorphous silicon layer 45 disposed on two sides above the amorphous silicon layer 44, and a source electrode 47 and a drain electrode 46 disposed on the N-type doped amorphous silicon layer 45, wherein a passivation layer 13 is disposed on the source electrode 47 and the drain electrode 46, the main pixel electrode 41 and the sub pixel electrode 42 are disposed on the passivation layer 13, and a via hole is disposed on the passivation layer 13, and the main pixel electrode 41 and the sub pixel electrode 42 are connected to the drain electrode 46 (or the source electrode 47) through the via hole.
The display panel 100 further includes a substrate 11, a first metal layer, and a second metal layer disposed on the first metal layer, the scan line 20 is disposed on the substrate 11, the scan line 20 includes a first signal line 21 and a second signal line 22 disposed in different layers, the first signal line 21 and the second signal line 22 are connected through a via 201, the first signal line 21 is output from the gate driving circuit 10, that is, connected to the gate driving circuit 10, and then crosses the common electrode 30, and is changed to the second signal line 22 through the via 201, the second signal line 22 is input to the display region 101, and one of the second signal lines 22 is connected to the gates 43 of the plurality of pixel units 40 in the same row, so as to implement the row-by-row scanning of the pixel units 40 by the gate driving circuit 10.
The orthographic projection of the positioning mark 80 on the first signal line 21 is close to the first signal line 21, so that personnel in an engineering section can conveniently check the corresponding grid level.
The gate driving circuits 10 may be disposed at two opposite sides of the display region 101, the plurality of scanning lines 20 are output from the gate driving circuits 10 and extend into the display region 101, the gate driving circuit 10 at one side of the display region 101 is connected to the plurality of scanning lines 20 at odd-numbered rows, and the gate driving circuit 10 at the other opposite side is connected to the plurality of scanning lines at even-numbered rows, in other embodiments, the gate driving circuits 10 at two sides may be connected to two ends of the same scanning line, or the gate driving circuit 10 may be disposed at only one side of the display region 101.
The display panel 100 further includes a control board (C-board)50, a source board (X-board)60 connected to the control board, a WOA (wire On array) wiring area 70 connected to the source board 60, and a plurality of data lines 90 connected to the WOA wiring area 70. The control board 50 and the source board 60 provide power signals with corresponding timings for the display devices on the display panel 100. The WOA wiring area 70 is arranged at the edge of the display panel 100 at intervals in a fan shape, a plurality of WOA wirings are arranged in the WOA wiring area 70 in a fan shape, the data line 90 is output from the WOA wiring area 70 and enters the display area 101, the data line 90 is connected with a source electrode 47 or a drain electrode 46 of a thin film transistor, and the data line 90 is arranged corresponding to each row of the pixel units 40.
The second signal line 22, the gate 43, and the common electrode 30 are all disposed on the same layer as the first metal layer, and the second signal line 22 avoids the common electrode 30. The first signal line 21, the scan line 20, and the source 47 and the drain 46 are all disposed on the same layer as the second metal layer, and a gate insulating layer 12 is further disposed between the first metal layer and the second metal layer.
The display panel further comprises a virtual pixel unit 40 ', the virtual pixel unit 40' is arranged at the edge of the display area 101, the pixel electrode structure of the virtual pixel unit 40 'is the same as that of the pixel unit 40, and the etching of the whole pixel electrode can be more uniform by arranging the virtual pixel unit 40'.
The thin film transistors in the dummy pixel units 40 ' exist independently, and do not access corresponding electrical signals, the dummy pixel units 40 ' are insulated from the scan lines 20 and the data lines, and the scan lines 20 are output by the gate driving circuit 10, pass through the dummy pixel units 40 ' after being changed in line by the via holes 201, and then are connected to the pixel units 40.
In one embodiment, the positioning mark 80 may be disposed on the same layer as the amorphous silicon layer 44, and the patterned positioning mark 80 is formed at a position corresponding to the common electrode 30 while the amorphous silicon layer 44 is formed.
In other embodiments, the positioning mark 80 may be disposed on the same layer as the pixel electrode layer (the main pixel electrode 41 and the sub-pixel electrode 42), and the patterned positioning mark 80 is formed at a position corresponding to the common electrode 30 while the pixel electrode layer is patterned.
The display panel 100 further includes a color resistance layer disposed on the pixel electrode layer, the positioning mark 80 may also be disposed on the same layer as the color resistance layer, and a patterned positioning mark 80 is formed at a position corresponding to the common electrode 30 while the color resistance layer is formed, where the positioning mark 80 may be formed by using the same composition process as any one of the red, green, and blue color resistances in the color resistance layer.
The display panel 100 further includes a supporting pad disposed in the liquid crystal layer for supporting a certain height, and the positioning mark 80 may be disposed on the same layer as the supporting pad, so that the patterned positioning mark 80 is formed at a position corresponding to the common electrode 30 while the supporting pad is formed.
When the arrow and the number mark in the positioning mark 80 are marked by one of the amorphous silicon layer 44, the pixel electrode layer, the color resistance layer, and the supporting pad on the display panel, not only the space for the common electrode 30 can be saved, but also the capacitance formed by the common electrode 30 and other metal layers is not interfered.
Has the advantages that: the positioning mark and the public electrode are arranged in different layers, and the orthographic projection of the positioning mark is arranged in the public electrode, so that the space can be saved, the wiring of the public electrode is thickened, the stability of the public electrode is improved, the positioning mark can be close to a scanning line, and the inspection and marking of workers are facilitated.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A display panel including a display area and a non-display area, the display panel comprising:
a substrate base plate;
the grid driving circuit is arranged in the non-display area;
the pixel units are arranged on the substrate base plate and are positioned in the display area;
the scanning lines are arranged on the substrate base plate, the first ends of the scanning lines are connected with the grid driving circuit, and the second ends of the scanning lines extend into the display area;
the common electrode is arranged between the grid driving circuit and the display area; and
a plurality of positioning marks arranged in a different layer from the common electrode; wherein,
the orthographic projection of the positioning mark on the common electrode is positioned in the common electrode and close to the corresponding scanning line.
2. The display panel according to claim 1, wherein the positioning mark is provided in the same layer as any one of an amorphous silicon layer, a pixel electrode layer, a color resist layer, and a support pad on the display panel.
3. The display panel of claim 1, further comprising a first metal layer disposed on the substrate base and a second metal layer disposed on the first metal layer.
4. The display panel according to claim 3, wherein the scan lines include first and second signal lines arranged in different layers, and the first and second signal lines are connected by a via.
5. The display panel according to claim 4, wherein the first signal line and the second metal layer are disposed in the same layer and connected to the gate driving circuit, the second signal line and the first metal layer are disposed in the same layer and extend to the display region, and the common electrode and the first metal layer are disposed in the same layer.
6. The display panel according to claim 1, wherein the positioning mark comprises a numeral mark and an arrow mark.
7. The display panel of claim 1, further comprising dummy pixel units disposed at edges of the display area.
8. The display panel of claim 7, wherein a scan line electrically connects the pixel cells in a row and is insulated from the dummy pixel cells in the row.
9. The display panel according to claim 1, wherein the pixel unit includes a main pixel region and a sub pixel region, and the scan line is disposed between the main pixel region and the sub pixel region in a row direction.
10. The display panel of claim 1, further comprising a control board, a source board connected to the control board, a WOA routing area connected to the source board in a fan shape, and a plurality of data lines connected to the WOA routing area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911134325.8A CN110888250A (en) | 2019-11-19 | 2019-11-19 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911134325.8A CN110888250A (en) | 2019-11-19 | 2019-11-19 | Display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110888250A true CN110888250A (en) | 2020-03-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911134325.8A Pending CN110888250A (en) | 2019-11-19 | 2019-11-19 | Display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341758A (en) * | 2020-04-13 | 2020-06-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253751C (en) * | 2002-07-04 | 2006-04-26 | Nec液晶技术株式会社 | LCD device with address mark connected with wiring |
| CN202975550U (en) * | 2012-12-26 | 2013-06-05 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and display device |
| CN103760728A (en) * | 2014-01-29 | 2014-04-30 | 北京京东方显示技术有限公司 | Array substrate and display device thereof |
| CN110071119A (en) * | 2019-04-09 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
-
2019
- 2019-11-19 CN CN201911134325.8A patent/CN110888250A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253751C (en) * | 2002-07-04 | 2006-04-26 | Nec液晶技术株式会社 | LCD device with address mark connected with wiring |
| CN202975550U (en) * | 2012-12-26 | 2013-06-05 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal panel and display device |
| CN103760728A (en) * | 2014-01-29 | 2014-04-30 | 北京京东方显示技术有限公司 | Array substrate and display device thereof |
| CN110071119A (en) * | 2019-04-09 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341758A (en) * | 2020-04-13 | 2020-06-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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