KR20180025533A - Display Device - Google Patents

Abstract

The specification of the present invention provides a display device which prevents a contact defect of a test pin when testing a signal line. The display device comprises: a substrate including a display area and a non-display area; and a signal line arranged on the substrate. The signal line includes: a first conductive layer connected to a pad; a second conductive layer separated from the first conductive layer; an insulating layer positioned on the first and second conductive layers, and including an open area in which an end unit of the first conductive layer, an end unit of the second conductive layer, and a space between the first and second conductive layers are exposed; and a conductive pattern positioned in the open area, and positioned on the end unit of the first conductive layer and the end unit of the second conductive layer exposed to the open area.

Description

[0001]

TECHNICAL FIELD The present invention relates to a display device for displaying an image.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an OLED (Organic Light Emitting Diode Display Device) are being utilized.

Generally, the display device includes a drive circuit for driving the display panel. The driving circuit includes a gate driver for sequentially applying a scan signal to the gate lines and a data driver for applying image information to the pixels through the data lines corresponding to the scan signal of the gate driver.

In recent years, display devices have been increasing in resolution according to technological advances and consumer demands. In addition, the resolution increase is caused by the addition of the auto-probe (AP) test pin and the decrease of the pitch of the pin to pin for inspecting the signal line, .

Also, as the resolution is increased, the heat generation in the signal lines and the pads may increase, which may cause abnormal driving of the display device. Accordingly, it is required to solve the problem caused by the heat generation and to minimize the cost incurred.

One embodiment of the present invention is to provide a display device for preventing a contact failure of a test pin at the time of inspecting a signal line.

Another embodiment of the present invention is to provide a display device for lowering the resistance of a signal line and a pad thereof so as to reduce power consumption and reduce a heat generation amount.

In one aspect, a display device according to an embodiment includes a substrate including a display region and a non-display region, and a signal line arranged on the substrate.

The signal line includes a first conductive layer connected to the pad and a second conductive layer spaced apart from the first conductive layer. The signal line is located on the first conductive layer and the second conductive layer and includes an end portion of the first conductive layer, an end portion of the second conductive layer, and an opening region exposed between the first conductive layer and the second conductive layer And an insulating layer. The signal line includes a conductive pattern located at an end of the first conductive layer and the end of the second conductive layer, which are located in the opening region and exposed to the opening region.

In another aspect, a display device according to another embodiment includes a substrate including a display area and a non-display area, a log line arranged on the substrate, and a connection line connecting the log line to the driving circuit.

The log line includes a conductive layer connected to the pad and an insulating layer disposed on the conductive layer. The insulating layer includes a first insulating layer including a first contact hole exposing a portion of the conductive layer, and a second contact hole located on the first insulating layer and exposing a portion of the first contact hole and the connection line And a second insulating layer.

The log line includes a connection pattern located on the conductive layer and a portion of the connection line in the first contact hole and the second contact hole.

The display device according to one embodiment can prevent the contact failure of the test pin at the time of inspecting the signal line.

In addition, the display device according to another embodiment can lower the resistance of the signal line and its pad, thereby lowering the power consumption and reducing the heat generation amount.

1 is a schematic configuration diagram of a display device according to the present embodiments.
2 is a view schematically showing a part of the display device of FIG.
FIG. 3 is a view showing the X region of FIG. 2 in detail.
4 is a cross-sectional view taken along the line A-A 'in Fig.
5 is a cross-sectional view taken along the line B-B 'in Fig.
6 is a cross-sectional view taken along the line C-C 'of FIG.
FIG. 7 is a detailed view of the Z region of FIG. 2. FIG.
8 is a cross-sectional view taken along the line E-E 'of Fig.
9 is a view showing the Y region of FIG. 2 in detail.
10 is a cross-sectional view taken along the line D-D 'of FIG.
11 is a cross-sectional view of a display device when the display device is a touch screen panel-integrated liquid crystal display device.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic configuration diagram of a display device according to the present embodiments.

Referring to FIG. 1, the display device according to the exemplary embodiments of the present invention includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting diode (OLED) ), And the like.

A display device according to the present embodiment includes a thin film transistor TFT for driving a pixel Pixel at an intersection of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, A gate driver 110 for supplying a scan signal to the gate lines GL1 to GLn; a data driver 120 for supplying data to the data lines DL1 to DLm; And a timing controller 130 for controlling the gate driver 110 and the data driver 120.

The gate driver 110 may supply a plurality of scan signals to the plurality of gate lines GL1 to GLn in response to a gate control signal GCS from the timing controller 130. [ The plurality of scan signals may enable the plurality of gate lines GL1 to GLn to sequentially enable one horizontal synchronous signal period. The gate driver 110 may comprise a plurality of gate driver integrated circuits.

The data driver 120 generates a plurality of pixel data voltages each time one of the plurality of gate lines GL1 to GLn is enabled in response to the data control signals DCS from the timing controller 130 To the plurality of data lines DL1 to DLm on the display panel 100, respectively. The data driver 120 may comprise a plurality of data driver integrated circuits.

The timing controller 130 receives the synchronization signals (Vsync, Hsync) supplied from an external system (for example, a graphics module of a computer system or a video demodulation module of a television receiving system, not shown) A gate control signal GCS for controlling the gate driver 110 and a data control signal DCS for controlling the data driver 120 are generated using the clock signal CLK and the DE signal. In addition, the timing controller 130 may sort the image data (Data) input from the external system and supply the aligned data (Vdata) to the data driver 120.

2 is a view schematically showing a part of the display device of FIG.

2, the display panel 100 includes a substrate 101 including a display region 104 for displaying an image and a non-display region 105 for not displaying an image around the display region 104 .

The data printed circuit board 124 is connected to the non-display area 105 of the display panel 100 by a tape automated bonding (TAB) method, for example, a flexible film And may be electrically and physically connected through a flexible printed circuit (128).

The flexible film 128 is mounted with the data driver integrated circuit 122 constituting the data driver 120 shown in Fig. The flexible film 128 includes a plurality of data lead wires 126 electrically connected to the plurality of data lines DL and a plurality of gate lead wires electrically connected to the gate driver integrated circuit 111 constituting the gate driver 110 113).

The plurality of data leads 126 are connected to the plurality of data lines DL arranged on the display panel 100 through the pad structure so that the video signals can be transferred from the data driver IC 122 to the data lines DL have. The gate lead line 113 may be connected to the start signal line SSL arranged on the display panel 110 through a pad structure to transmit a start pulse to the gate driver integrated circuit 111.

The flexible film 128 may be connected to a log line lead 114 electrically connected to the log line LOG. The plurality of log line lead lines 114 may transmit control signals, a clock signal, a gate voltage, a power supply voltage, a ground voltage, and the like to the gate driver IC 111 via a log line LOG.

The gate driver integrated circuit 111 receives the control signals supplied through the log line LOG and the start signal supplied via the start signal line SSL with the clock signal, gate voltage, power supply voltage, ground voltage, Or the gate signal to the gate lines GL of the display panel 100. [

The data line DL and the gate line GL, the log line LOG and the start signal line SSL are referred to as signal lines arranged on the substrate 101. 3 to 5, the signal lines are exemplarily illustrated as the data lines DL, and the signal lines are exemplarily shown as the log lines LOG with reference to FIGS. 6 to 10, Herein, the signal line may be any signal line electrically connected to the flexible film 128, for example, a start signal line (SSL) or various power supply lines not shown.

FIG. 3 is a view showing the X region of FIG. 2 in detail.

Referring to FIG. 3, the data line DL includes a first conductive layer 210 connected to the pad 205, a second conductive layer 212 spaced apart from the first conductive layer 210, And a conductive pattern 230 located between the first conductive layer 210 and the second conductive layer 212 and electrically connected to the first conductive layer 210 and the second conductive layer 212.

The pad 205 may be electrically connected to the data lead 126 as described with reference to FIG. 2 to transfer the video signal from the data driver integrated circuit 122 to the data line DL.

4 is a cross-sectional view taken along the line A-A 'in Fig.

Referring to FIGS. 3 and 4, the first conductive layer 210 and the second conductive layer 212 are spaced apart from each other on the substrate 101. The first conductive layer 210 and the second conductive layer 212 may be located in the same layer with the same material. In the process, the first conductive layer 210 and the second conductive layer 212 may be simultaneously formed on the same layer with the same material.

An insulating layer 220 is disposed on the first conductive layer 210 and the second conductive layer 212. The insulating layer 220 is formed on the insulating layer 220 between the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212 and between the first conductive layer 210 and the second conductive layer 212, And an open area (OA). The insulating layer 220 includes a first insulating layer 222 disposed on the first conductive layer 210 and the second conductive layer 212 and a second insulating layer 224 disposed on the first insulating layer 222 ). The second insulating layer 224 may be inclined in the opening area OA as shown in FIG. 4, but is not limited thereto.

The conductive pattern 230 is positioned on the end portion 210a of the first conductive layer 210 and the end portion 212a of the second conductive layer 212 which are located in the opening region OA and are exposed to the opening region OA do. Accordingly, the first conductive layer 210 and the second conductive layer 212 are electrically connected through the conductive pattern 230.

The conductive patterns 230 may serve as inspection pads for inspecting the data lines DL and the data integration circuits 122 and the pixels P. [ As the conductive pattern 230 is disposed in the opening area OA of the insulating layer 220 as shown in Figs. 3 and 4, the auto-probe inspection pin for inspecting the data line DL is brought into contact with the data line DL, the data integration circuit 122, and the pixel P can be checked.

The metal oxide 240 may be located on the conductive pattern 230. The metal oxide 240 may be the same material as the pixel electrode constituting the pixel P as described below with reference to FIG. 11, but is not limited thereto. The metal oxide 240 may shield the conductive pattern 230 from the outside.

5 is a cross-sectional view taken along the line B-B 'in Fig. 6 is a cross-sectional view taken along the line C-C 'of FIG.

5, the line width W1 of the conductive pattern 230 may be wider than the line widths W2 of the first conductive layer 210 and the second conductive layer 212. Referring to FIG. The line width of the metal oxide 240 may be substantially equal to the line width W1 of the conductive pattern 230 when the metal oxide 240 is disposed on the conductive pattern 230. [ The line width W1 of the metal oxide 240 may be wider than the line widths W2 of the first conductive layer 210 and the second conductive layer 212. [

The line width W1 of the conductive pattern 230 and the metal oxide 240 is wider than the line width W2 of the first conductive layer 210 so that the conductive pattern 230 and the metal oxide 240 form the first conductive layer 210, The upper surface 210b and the side surface 210c of the end portion 210a of the housing 210a. The line width W1 of the conductive pattern 230 and the metal oxide 240 is wider than the line width W2 of the end 212a of the second conductive layer 212 so that the conductive pattern 230 and the metal oxide 240 And may cover the top and sides of the second conductive layer 212.

5 and 6, the conductive pattern 230 is electrically connected to the conductive pattern 230 located between the end portion 210a of the first conductive layer 210 and the end portion 212a of the second conductive layer 212 The width W4 of the upper surface 230a of the second conductive layer 212 is greater than the width W4 of the upper surface 230a of the conductive pattern 230 located at the end 210a of the first conductive layer 210 and the end 212a of the second conductive layer 212 230b, respectively.

The width of the upper surface of the metal oxide 240 may be substantially the same as the width of the upper surface of the conductive pattern 230 when the metal oxide 240 is located on the conductive pattern 230. The width of the upper surface of the metal oxide 240 located on the conductive pattern 230 located between the end portion 210a of the first conductive layer 210 and the end portion 212a of the second conductive layer 212 The upper surface W4 of the metal oxide 240 located on the conductive pattern 230 located at the end portion 210a of the first conductive layer 210 and the end portion 212a of the second conductive layer 212 And may be wider than the width W3.

As a comparative example, the first conductive layer 210 and the second conductive layer 212 are not disposed on the substrate 101, but are connected to one conductive layer and disposed in the opening area OA The conductive pattern 230 can be disposed on the conductive pattern 230. In this case, the width of the upper surface of the conductive pattern 230 is the same as the width of the end portion 210a of the first conductive layer 210 and the end portion 212a of the second conductive layer 212, Becomes equal to the width W3 of the upper surface 230a of the pattern 230.

In the comparative example, the width W3 of the upper surface of the conductive pattern 230 to which the auto-probe inspection pin is contacted is small, so that contact failure with the inspection pin may occur. As described above, since the resolution of the display device is increased and the number of the auto-probe (AF) inspection pins and the pitch of the PIN to PIN are decreased to inspect the signal lines, The width W3 of the surface is too small to cause a problem of contact failure with the test pin or even the test itself becomes impossible.

The width W4 of the upper surface 230b of the conductive pattern 230 in contact with the auto-probe inspection pin is widened in the embodiment, so that the contact failure of the inspection pin can be prevented.

FIG. 7 is a detailed view of the Z region of FIG. 2. FIG. 8 is a cross-sectional view taken along the line E-E 'of Fig.

7 and 8, the log line LOG may be bent on the substrate 101 in the non-display area 105. [ The log line LOG includes an insulating layer 320 on which the conductive layer 310 and the other opening area OA1 are disposed and a conductive pattern 330 on the other opening area OA1, (Not shown). This pad 305 may be referred to as a log line pad.

The log line pad 305 is electrically connected to the log line lead 114 as described with reference to FIG. 2, and outputs control signals, a clock signal, a gate voltage, a power supply voltage, and a ground voltage to the log line LOG To the gate driver integrated circuit (111).

The insulating layer 320 may include a first insulating layer 322 located on the conductive layer 310 and a second insulating layer 324 located on the first insulating layer 322.

The conductive layer 310 may be located on the same layer of the same material as the first conductive layer 210 and the second conductive layer 212 described with reference to FIGS. The conductive layer 310 may be formed on the same layer of the same material as the first conductive layer 210 and the second conductive layer 212 at the same time. The conductive pattern 330 may be located in the same layer with the same material as the conductive pattern 230 described with reference to Figs. The conductive patterns 330 may be formed on the same layer with the same material as the conductive patterns 230 at the same time.

The metal oxide 340 may be positioned on the conductive pattern 330. The metal oxide 340 may be the same material as the pixel electrode constituting the pixel P as described below with reference to FIG. 11, but is not limited thereto. The metal oxide 340 may shield the conductive pattern 330 from the outside.

In the comparative example, only the metal oxide 340 may be disposed on the conductive layer 310 in the opening area OA1 of the insulating layer 320 in the log line pad. At this time, the resistance R between the conductive layer 310 and the metal oxide 340 may be relatively large. Accordingly, in the comparative example, the power consumption (P = I ² x R) of the log line pad is relatively large and the heat generation amount (Heat? I ² x R x t) proportional to the power consumption can be relatively increased.

The log line pad 305 including the conductive pattern 330 between the conductive layer 310 and the metal oxide 340 may lower the resistance as a whole. Thus, the log line pad 305 can reduce the power consumption (P = I ² x R) and reduce the heat generation amount (Heat? I ² x R x t) proportional to the power consumption.

The structure of the log line pad 305 described above can be applied to the pad 205 shown in FIGS. 3 to 6 in the same manner. The structure of the log line pad 305 may be applied to any signal line electrically connected to the flexible film 128, for example, a start signal line (SSL) or a pad of various power supply lines can do.

9 is a view showing the Y region of FIG. 2 in detail. 10 is a cross-sectional view taken along the line D-D 'of FIG.

Referring to FIG. 9, the log line LOG arranged on the substrate 101 extends from the pad 305 shown in FIG. This log line (LOG) is connected to the connection line (CL). This connection line CL connects the log line LOG to a drive circuit, for example, a gate drive integrated circuit 111 constituting the gate driver shown in Fig.

The connection line CL is connected to the log line LOG on a one-to-one basis and can supply various signals and voltages supplied to the log line LOG to the gate driver integrated circuit 111. At this time, an antistatic circuit may be disposed at an input terminal of the gate driver integrated circuit 111 into which various signals and voltages are input. The antistatic circuit can prevent static electricity from being generated in various signals and voltages supplied from the connection line CL.

Here, the connection line CL may be formed on the same plane as the data line DL. Further, the connection line CL may be formed of the same material as the data line DL. Since such a connection line CL can be formed without an additional process, the process cost and time can be saved.

10, the log line LOG includes a conductive layer 410 connected to the pad 305 shown in FIGS. 7 and 8, a conductive layer 410 disposed on the conductive layer 410, A first insulating layer 422 including a first contact hole OA2 for exposing a part of the first contact hole OA2 and a second insulating layer 422 located on the first insulating layer 422 and including a part of the first contact hole 0A2 and the connection line CL And a second insulating layer 420 including a second contact hole OA3.

The connection pattern 430 is positioned on the conductive layer 410 and the portion CLa of the connection line CL in the first contact hole 0A2 and the second contact hole OA3. The metal oxide 440 may be located on the connection pattern 330, but is not limited thereto. As a result, the connection pattern 430 and the metal oxide 440 may be disposed in the second contact hole OA3 as shown in FIG.

The connection pattern 430 may contact the gate drive integrated circuit 111 and the connection line CL connected to the static electricity prevention circuit (not shown) in the second contact hole OA3 as shown in FIG.

The first conductive layer 210 and the second conductive layer 212 of the data line DL as well as the conductive layer of the pad 305 described with reference to FIGS. 310 and the conductive layer 410 of the log line LOG described with reference to FIGS. 9 and 10 may be formed by the same process with the same material, for example, a single layer or a multi-layer metal or metal alloy. For example, the conductive layer 210, the second conductive layer 212, the conductive layer 310, and the conductive layer 410 may be formed simultaneously by the same process using the same material as the gate line GL.

As described with reference to Figs. 3 to 6, the conductive pattern 230 of the data line DL, the conductive pattern 330 of the pad 305 described with reference to Figs. 7 and 8, Figs. 9 and 10 The connection pattern 430 of the log line (LOG) described can be formed by the same process with the same material, for example a single layer or a multi-layer metal or metal alloy. For example, the conductive pattern 230 of the data line DL, the conductive pattern 330 of the pad 305, and the connection pattern 430 of the log line LOG are formed as shown in FIG. The same material and the same material as the touch line that transmits the touch signal to the touch electrode disposed at the same time can be simultaneously formed by the same process.

The metal oxide 240 of the data line DL and the metal oxide 440 of the pad 305 described with reference to FIGS. 7 and 8, FIGS. 9 and 10, as described with reference to FIGS. 3 to 6 The metal oxide 440 of the log line (LOG) described can be formed by the same process with the same material. For example, as described with reference to FIGS. 3 to 6, the metal oxide 240 of the data line DL, the metal oxide 440 of the pad 305 described with reference to FIGS. 7 and 8, The metal oxide 440 of the log line LOG described with reference to FIG. 10 can be simultaneously formed by the same process with the same material as the pixel electrode constituting the pixel P as described later with reference to FIG.

The first insulating layer 222 and the second insulating layer 224 of the insulating layer 220 of the data line DL described with reference to Figs. 3 to 6, the pads 305 described with reference to Figs. 7 and 8, The first insulating layer 322 and the second insulating layer 324 of the insulating layer 320 of the log line LOG and the first insulating layer 422 of the insulating layer 420 of the log line LOG described with reference to FIGS. And the second insulating layer 424 are formed of the same material as one of the gate insulating layer, the first protective layer and the second protective layer constituting the pixel P by the same process .

11 is a cross-sectional view of a display device when the display device is a touch screen panel-integrated liquid crystal display device.

Referring to FIG. 11, in the touch screen panel integrated type liquid crystal display device according to one embodiment, for example, a gate line 502 is formed in the first direction on the first substrate 500, and a gate insulating layer Gate Insulator 504 is formed.

A data line 506 is formed in a second direction on the gate insulating layer 504, and a first passivation layer 508 is formed thereon.

The pixel electrode 510 of each pixel region and the touch line 512 may be formed on the first passivation layer 508 and the second passivation layer 514 may be formed thereon. Here, the touch line 512 is connected from the plurality of electrodes serving as the common electrode and the touch electrode to the touch integrated circuit. In the display driving mode, the common voltage Vcom generated in the common voltage supply unit is transmitted to the plurality of electrodes In the touch driving mode, a touch driving signal generated in the touch integrated circuit is transmitted to a plurality of electrodes.

On the second passivation layer 514, one electrode 516 serving as a common electrode and a touch electrode is formed, and a liquid crystal layer 518 is formed thereon. An upper substrate 520 on which a black matrix 519a, a color filter 519b, and the like are formed is disposed on the liquid crystal layer 518.

Although the liquid crystal display device is described with reference to FIG. 11, the present invention is not limited thereto and can be applied to various display devices that can be combined with a touch panel.

The above-described display device can reduce the line resistance and reduce the power consumption and the calorific power by configuring the log line by utilizing the conductive layer having a low resistance. Particularly, the display device described above can be formed without any additional process in the forming process since the log line is formed by utilizing a low-resistance touch line.

The above-described display device has a problem in that, even if the resolution is increased, an auto-probe (AF) inspection pin is added for inspecting a signal line, a pin contact Defects can be prevented.

The above-described display device can reduce power consumption and heat generation even when resolution is increased. Particularly, since the above-described display device is formed without any additional process in the forming process, the manufacturing cost can be lowered and the manufacturing time can be shortened.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display panel
101: substrate
DL: Data line
GL: gate line
LOG: log line
Conductive layers 210, 212, 310, 410
Insulation layers: 220, 320, 420
Conductive patterns: 230, 330, 430
Metal oxides: 240, 340, 440

Claims (12)

A substrate including a display region and a non-display region; And
A signal line arranged on the substrate,
The signal line includes:
A first conductive layer connected to the pad,
A second conductive layer spaced apart from the first conductive layer,
And an opening region located on the first conductive layer and the second conductive layer and between the end of the first conductive layer and the end of the second conductive layer and between the first conductive layer and the second conductive layer, An insulating layer,
And a conductive pattern located in the opening region and positioned on an end of the first conductive layer exposed to the opening region and an end of the second conductive layer. The method according to claim 1,
Wherein the line width of the conductive pattern is larger than the line widths of the first conductive layer and the second conductive layer. 3. The method of claim 2,
The conductive pattern may include:
Wherein a width of an upper surface of the conductive pattern located between an end of the first conductive layer and an end of the second conductive layer is smaller than a width of the end of the first conductive layer and the end of the second conductive layer, The width of the upper surface being larger than the width of the upper surface. The method according to claim 1,
And a metal oxide disposed on the conductive pattern. The method according to claim 1,
Wherein the first conductive layer and the second conductive layer are located in the same layer with the same material. The method according to claim 1,
Wherein the signal line is a data line for supplying a video signal. The method according to claim 1,
Wherein the signal line is a log line for supplying a control signal or a power supply voltage to the gate driver. The method according to claim 1,
Wherein the conductive pattern is the same material as the touch line that transmits touch signals to the touch electrodes disposed in the display area. The method according to claim 1,
Wherein the pad includes an insulating layer on which an opening region different from the conductive layer on the substrate is disposed, and a conductive pattern located in the other opening region. A substrate including a display region and a non-display region;
A log line arranged on the substrate; And
And a connection line connecting the log line to a driving circuit,
The log-
A conductive layer connected to the pad,
A first insulating layer disposed on the conductive layer and including a first contact hole exposing a portion of the conductive layer; a second insulating layer located on the first insulating layer and partially exposing a portion of the first contact hole and the connecting line; An insulating layer including a second insulating layer including a second contact hole,
And a connection pattern located on the conductive layer and a part of the connection line in the first contact hole and the second contact hole. 11. The method of claim 10,
Wherein the connection pattern is the same material as a touch line that transmits a touch signal to the touch electrode disposed in the display area. 11. The method of claim 10,
Wherein the pad comprises an insulating layer on which a conductive layer and an opening region are disposed, and a conductive pattern located in the opening region.

Images