KR20060001652A - Liquid crystl display device for preventing gate pad from erosion - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of preventing corrosion of the gate pad and a method of manufacturing the same, and includes a seal pattern formed on the periphery of the first and second substrates and the first and second substrates to define an active region. A plurality of gate wirings and data wirings arranged on the first substrate in first and second directions to define a plurality of pixels, and gate pads formed at an outer side of the active region and connected to one side of the gate wirings; And a liquid crystal layer formed in the active region, the first contact hole electrically connecting the gate wiring and the gate pad and a liquid crystal layer formed between the first substrate and the second substrate.

Description

Liquid crystal display device and method for manufacturing the same for preventing corrosion of gate pad {LIQUID CRYSTL DISPLAY DEVICE FOR PREVENTING GATE PAD FROM EROSION}

1 is a view showing a plane of a general liquid crystal display device.

Figure 2a is a plan view showing a part of the conventional gate pad in detail, Figure 2b is a cross-sectional view taken along line II 'of Figure 2a.

3 is a plan view of a liquid crystal display device according to the present invention;

Figure 4a is a detailed view showing the connection portion of the gate wiring and the gate pad, Figure 4b is a cross-sectional view of II-II 'of Figure 4a.

Figure 5 shows another embodiment of the present invention, Figure 5a is a plan view, Figure 5b is a cross-sectional view of III-III'II-II 'of Figure 5a.

6A to 6D are cross-sectional views showing the manufacturing process of the liquid crystal display device according to the present invention.

*** Explanation of symbols for main parts of drawing ***

116,216,316: Gate pads 121,221,321: Gate wiring

125,225,325: gate antistatic wiring

139a, 239a, 339a: first contact hole

139b, 239b, 339b: first contact hole

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same for preventing corrosion of the gate pad.

In general, a liquid crystal display (LCD) displays an image corresponding to a video signal on a liquid crystal panel by adjusting light transmittance of liquid crystal cells arranged in a matrix form according to a video signal. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving integrated circuit (hereinafter, referred to as an IC) for driving the liquid crystal cells. The liquid crystal panel is composed of an upper substrate and a lower substrate, and a liquid crystal layer formed therebetween, a color filter is formed on the upper substrate, and a gate wiring and data wiring defining a liquid crystal cell on the lower substrate, and a gate wiring and data wiring of A gate / data pad is formed at one end and connected to the driving IC.

1 is a plan view illustrating a liquid crystal panel of a general liquid crystal display device.

As shown in the figure, the liquid crystal panel 1 includes an upper substrate 10, a lower substrate 20, and a liquid crystal layer (not shown) formed therebetween, and the liquid crystal cells are arranged in a matrix to form an actual image. The active area P and the gate / data pads 16 and 26 are displayed, and the gate / data pads 16 and 26 do not overlap the upper substrate 10 and the lower substrate 20. Located in the edge region of the lower substrate 20.

The upper substrate 10 includes black filters and color filters applied separately for each cell region, and a common electrode for applying a signal to the liquid crystal layer.

The lower substrate 20 has a gate wiring 21 and a data wiring 23 arranged vertically and horizontally to define liquid crystal cells, and switching liquid crystal cells in an intersection area between the gate wiring 21 and the data wiring 23. A thin film transistor and a pixel electrode connected to the thin film transistor to drive the liquid crystal cell are formed.

The gate / data pads 16 and 26 extend from the gate wiring 21 and the data wiring 23, respectively, and the gate pad 16 is connected to a gate driving circuit (not shown), so that the gate wiring ( A gate signal is applied to 21, and the data pad 26 is connected to a data driving circuit (not shown) to apply a data signal to the data line 23.

The upper substrate 10 and the lower substrate 20 having such a configuration are bonded by the seal pattern 25 located at the outer side of the active region P. FIG. In this case, a cell gap of a predetermined interval is provided between the upper substrate 10 and the lower substrate 20 by the height at which the seal pattern 25 is applied. The liquid crystal is filled in the space thus prepared, and a constant cell gap is maintained by the spacers scattered before the liquid crystal injection.

Meanwhile, at one side of the gate pad 16 of the lower substrate 20, a gate antistatic wiring 25 may be formed to connect the respective gate pads 16 to electrically short the gate wirings 21. 26, a data antistatic wiring 26 is formed on one side to electrically connect the respective data pads 26 to electrically short the gate wirings 21.                         

The gate antistatic wiring 25 and the data antistatic wiring 24 are formed together in the process of forming the gate wiring 21 and the data wiring 23, and prevent static electricity in the active region P during the process. This is done so that once the device is complete, it is removed. That is, along the breakline 28, and as the gate / data antistatic wiring 26 is removed, each of the gate / data wirings 21 and 23 is insulated.

As the liquid crystal panel is enlarged, an electrode material having low wiring resistance is used to prevent signal delay. In particular, in the case of a gate wiring, an AlNd electrode material is used. Since the AlNd is easily corroded to contact with external air, the MoN is formed on the AlNd layer. Therefore, when the size of the liquid crystal panel is increased, the gate wiring uses a double electrode layer made of Mo / AlNd.

However, a transparent electrode pattern is formed on the gate pad 16, and the transparent electrode pattern 37 is electrically connected to the gate pad 16 to connect the gate pad 16 to an external gate driving circuit. do. In this case, corrosion occurs due to external air contacting the AlNd layer, which is the material for forming the gate pad 16, through a pin hole formed on the transparent electrode pattern 37.

FIG. 2 is for explaining a problem of the conventional liquid crystal display device. FIG. 2A shows a part of the gate pad, and FIG. 2B shows a cross section of II ′ of FIG. 2A.

As shown in the figure, the gate pad 16 is formed outside the seal pattern 22. In this case, the gate pad 16 has the gate wiring 21 of the active region P extending outside the seal pattern 22 and is formed of a double electrode layer of Mo / AlNd 31b / 31a. The gate insulating layer 33 and the passivation layer 35 are formed on the lower substrate 20 on which the gate pad 16 is formed, and a gate contact hole 39 exposing a portion of the gate pad 16 is formed. .

In addition, a transparent electrode pattern 37 is formed on the gate contact hole 39 for connection with an external driving circuit. The transparent electrode pattern 37 is formed together with the pixel electrode of the active region P. The transparent electrode pattern 37 is formed of a material such as ITO or IZO, and the gate pad 16 passes through the gate contact hole 39. (37).

Therefore, as the gate driving circuit is connected to the transparent electrode pattern 37, the gate pad 16 and the gate driving circuit can be connected.

In the process of removing the passivation layer 35 and the gate insulation layer 33 to form the gate contact hole 39, the Mo layer 16b forming the gate pad 16 is removed together to form the AlNd layer 16a. ) And the transparent electrode pattern 37 is in direct contact with the AlNd layer 16a.

In the meantime, the transparent electrode pattern 37 forms a pinhole 37 'on the surface thereof. Therefore, after completion of the liquid crystal panel, the AlNd layer 16a is in contact with air through the pinhole 37 'because the transparent electrode pattern 37 is exposed to the outside while preventing the connection with the driving circuit. It will cause corrosion.

In this way, when corrosion occurs in the gate pad 16, the contact resistance between the gate pad 16 and the transparent electrode pattern 37 becomes very high, so that the signal supplied from the gate driving circuit is properly received. Since it is not received, a defect due to signal delay occurs.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can prevent corrosion of a gate pad.

In order to achieve the above object, the liquid crystal display device of the present invention includes a first and second substrate, a seal pattern formed on the periphery of the first and second substrate to define an active region, and on the first substrate. A plurality of gate wirings and data wirings arranged in first and second directions to define a plurality of pixels, a gate pad formed outside the active region and connected to one side of the gate wiring, and formed in the active region, And a first contact hole electrically connecting the gate wiring and the gate pad, and a liquid crystal layer formed between the first substrate and the second substrate.

An extension line of the gate line may further include a gate antistatic line electrically connecting all the gate lines.

In addition, the gate pads may be configured to further include a gate anti-static wiring for electrically connecting, wherein the gate pad is electrically connected through a second contact hole that exposes a portion of the gate anti-static wiring. .

The gate wiring formed in the active region is formed of Mo / AlNd, and the gate pad formed outside the active region is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO).

And a switching element formed at an intersection of the gate wiring and the data wiring, a pixel electrode formed at each pixel of the first substrate, and a common electrode formed on the front surface of the second substrate. It is also possible to be formed on the first substrate.

In addition, the liquid crystal display device of the present invention includes a first and a second substrate, a seal pattern formed on the periphery of the first and second substrate to define an active region, and a first direction on the first substrate of the active region. A plurality of gate wirings arranged together with the gate wirings, a gate insulating film formed on the entire surface of the first substrate including the gate wirings, and a second direction crossing the first direction on the gate insulating film of the active region. A data line defining a plurality of pixels, a passivation layer formed on an entire surface of the first substrate including the data line, and a portion of the gate insulation layer and the passivation layer are removed to expose a portion of one side of the gate lines formed in the active region. A first contact hole, a gate pad formed on the protective layer outside the seal pattern, and connected to the gate wiring through the first contact hole, and on the first substrate and the second substrate. Generated is configured to include a liquid crystal layer.

It further comprises an antistatic wiring for electrically connecting the gate pad, the gate pad is electrically connected through a second contact hole for exposing a portion of the antistatic wiring.

The gate wiring is formed of Mo / AlNd, and the gate pad is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The pixel electrode may further include a switching element formed at an intersection of the gate wiring and the data wiring, a pixel electrode formed on each pixel of the first substrate, and a common electrode formed on the entire surface of the second substrate. The common electrode may be formed together on the first substrate.

In addition, a method of manufacturing a liquid crystal display device according to the present invention includes preparing a first and a second substrate, forming a gate wiring arranged in a first direction on the first substrate, and the gate wiring. Forming a gate insulating film formed on the entire surface of the first substrate, and forming a data wiring on the gate insulating film in a second direction crossing the first direction to define a plurality of pixels together with the gate wiring; Forming a passivation layer formed on an entire surface of the first substrate including the data line, removing a portion of the gate insulating layer and the passivation layer to form a first contact hole exposing a portion of one side of the gate line; Forming a gate pad connected to the gate wiring through the first contact hole on the passivation layer, and active on any one of the first and second substrates; But form a seal pattern to define a station, such that the first contact hole included in the active region.

In this case, the gate wiring is formed of a double layer of Mo / AlNd, the gate pad is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO).

As described above, the present invention forms a connection portion between the gate wiring and the gate pad in the active region and forms the gate pad as a transparent electrode, thereby preventing corrosion of the gate pad. That is, conventionally, the gate wiring and the gate pad are formed in the same process, and after the gate pad is exposed, a separate transparent electrode pattern is formed on the gate pad. Therefore, external air contacts the gate pad through the pinhole formed on the transparent electrode pattern, and in particular, when the gate wiring and the gate pad are made of Mo / AlNd electrode material, there is a problem that corrosion of the gate pad occurs. . On the other hand, the present invention solves the gate pad corrosion problem by forming a gate pad exposed outside the active area as a transparent electrode and forming a connection portion between the gate wiring and the gate pad inside the active area.

Hereinafter, the liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view showing a liquid crystal panel of the liquid crystal display device according to the present invention.

As shown in the figure, the liquid crystal panel 100 includes an upper substrate 110, a lower substrate 120, and a liquid crystal layer (not shown) formed therebetween, and the liquid crystal cells are arranged in a matrix to form an actual image. The lower substrate 120 is divided into an active region P and a gate / data pad 116 and 126 region, and the gate / data pad 116 and 126 region does not overlap the upper substrate 110 and the lower substrate 120. ) Is located in the edge area.

The upper substrate 110 includes color filters coated separately for each black matrix and cell region, and a common electrode for applying a signal to the liquid crystal layer.

A gate wiring 121 and a data wiring 123 are arranged on the lower substrate 120 to define liquid crystal cells arranged vertically and horizontally, and the liquid crystal cells are switched in an intersection area between the gate wiring 121 and the data wiring 123. A thin film transistor and a pixel electrode connected to the thin film transistor to drive the liquid crystal cell are formed.

Meanwhile, the pixel electrode and the common electrode may be formed on the same substrate (ie, the lower substrate) 120. In this case, the pixel electrode or the common electrode may be formed of a transparent material such as the pixel electrode or the common electrode ITO or IZO to improve the aperture ratio. .

In addition, the color filter formed on the upper substrate 110 may be formed on the lower substrate 120, it may be formed on the top or bottom of the thin film transistor (TFT), respectively. That is, both a color filter on TFT (COT) structure and a TFT on color filter (TOC) structure are possible.

The data pad 126 extends from the data line 123 and is connected to a data driver circuit (not shown) to apply a data signal to the data line 123.

The gate pad 116 is electrically connected to the gate wiring 121 through a contact hole (not shown) formed in the active region P. The gate pad 116 is connected to a gate driving circuit (not shown) to apply a gate signal to the gate wiring 121.

The upper substrate 110 and the lower substrate 120 having such a configuration are bonded by the seal pattern 125 positioned at the outer side of the active region P. FIG. In this case, a cell gap of a predetermined interval is provided between the upper substrate 110 and the lower substrate 120 by the height at which the seal pattern 125 is applied. The liquid crystal is filled in the space thus prepared, and a constant cell gap is maintained by the spacers scattered before the liquid crystal injection.                     

On the other hand, a gate antistatic wiring 125 is formed on one side of the gate pad 116 of the lower substrate 120 to electrically short the gate wirings 121 by connecting the respective gate pads 116 to each other. One side of the data antistatic wiring 126 is formed to connect the respective data pads 126 to electrically short the gate wiring 121.

The gate antistatic wiring 125 and the data antistatic wiring 124 are formed together in the process of forming the gate wiring 121 and the data wiring 123, and prevent static electricity in the active region P during the process. This is done so that once the device is complete, it is removed. In other words, as the break line 128 is cut and the gate / data antistatic wirings 116 and 126 are removed, each of the gate / data wirings 121 and 123 is insulated.

In addition, the gate wiring 121 is used as a low resistance electrode material such as AlNd to reduce wiring resistance, and Mo is formed on the AlNd to prevent corrosion by contact with external air. Accordingly, the gate wiring 121 is formed of a double electrode layer of Mo / AlNd, and the gate antistatic wiring 125 is also formed of the same double electrode layer of Mo / AlNd as the gate wiring 121.

On the other hand, the gate pad 116 is formed of a transparent electrode pattern, such as ITO or IZO, and is electrically connected to the gate wiring 121 through a first contact hole (not shown) formed in the active region P. . In addition, the gate may be connected to the antistatic wiring 125 through a second contact hole (not shown).                     

4A and 4B show a connection area between the gate wiring and the gate pad, FIG. 4A is a plan view, and FIG. 4B is a cross-sectional view taken along line II-II 'of FIG. 4A and shows only a cross section of the lower substrate except for the upper substrate. .

As shown in the figure, the active region P is defined by a seal pattern formed on the outer side of the upper substrate 110 and the lower substrate 120, and in particular, the upper substrate 110 on the outer side of the seal pattern 122. A gate pad 116 made of a transparent conductive material such as ITO or IZO is formed in an outer region of the lower substrate 120 that does not overlap with the lower substrate 120. The gate pad 116 is connected to the gate wiring 121 through the first contact hole 139a formed in the active region P. In addition, before the liquid crystal panel is completed, a gate antistatic wiring 125 is formed at one side of the gate pad 121 to be connected to the gate pad 116 through the second contact hole 139b.

As mentioned, the gate antistatic wiring 125 is for preventing static electricity generated during the process, and is cut along the breakline 128 after the panel is completed. In this case, the second contact hole 139b Is also cut together. The gate pad 116 is connected to a gate driving circuit (not shown) through a gate TCP (not shown).

As shown in FIG. 4B, the gate wiring 121 and the gate antistatic wiring 125 are formed on the transparent substrate 120 ′, and include the gate wiring 121 and the gate antistatic wiring 125. A gate insulating film 133 is formed on the entire surface of the substrate 120 ′. Although not shown in the drawings, a data wiring (not shown) defining a plurality of pixels by crossing the gate wiring 121 on the gate insulating film 133 and a data pad (not shown) supplying an image signal to the data wiring (not shown). ) Is formed, and the data anti-static wiring connecting the data pad is formed on the outer side of the brake wiring.

A passivation layer 135 is formed on an entire surface of the substrate including the data line and the data pad, and a portion of the gate insulating layer 133 and the passivation layer 135 is removed to expose a portion of the gate pad 116. A second contact hole 139b exposing 139a and a portion of the gate antistatic wiring 125 is formed.

On the passivation layer 135, the gate pad 116 connects the first contact hole 139a with the gate wiring 121 and connects with the gate antistatic wiring 125 through the second contact hole 139b. Is formed. Therefore, the gate wiring 121 and the gate antistatic wiring 125 are electrically connected through the gate pad 116. In this case, since the first contact hole 139a is formed in the active region P, even if a pinhole is generated on the gate pad 116, the gate wiring 137 may be prevented from contacting air. In this case, corrosion may occur in a contact region between the gate antistatic wiring 125 and the gate pad 116 through the pinhole of the gate pad 116 formed in the second contact hole 139b. The hole 139b does not need to be considered because it is removed after the panel is completed.

On the other hand, it is also possible not to form the second contact hole 139b. That is, the gate antistatic wiring 125 may be formed by extending the gate wiring 121 without forming the second contact hole 139b.                     

Figure 5 shows another embodiment of the present invention, Figure 5a is a plan view, Figure 5b is a sectional view. All components except the connection method of the gate wiring and the gate antistatic wiring are the same as in the previous embodiment (Figs. 4A and 4B), and the detailed description of the same configuration as in the previous embodiment is omitted in the present embodiment. Be specific about the bay.

As shown in the figure, the gate wiring 221 formed on the transparent substrate 220 'is formed to extend outside the active region P to be integrated with the gate antistatic wiring 225. Therefore, as in the previous embodiment, a separate contact hole for electrically connecting the gate wiring 221 and the gate antistatic wiring 225 is not required, and the first contact hole 239a formed inside the active region P is not required. The gate pad 216 and the gate wiring 221 may be electrically connected to each other through the wire pad 216.

The liquid crystal display device of the present invention configured as described above is manufactured through the following process.

6A to 6D illustrate a method for manufacturing a liquid crystal display device according to the present invention, and in particular, show a process cross section along the cross section of FIG. 4B.

First, as shown in FIG. 6A, a transparent insulating substrate 320 'such as glass or plastic is prepared, and then AlNd, Cu, Ti, Cr, Al, Mo, Ta, Al alloy is formed on the substrate 320'. After depositing a metal such as through a sputtering method, it is patterned to form the gate wiring 321 and the gate antistatic wiring 325. In this case, a gate electrode (not shown) drawn out from the gate wiring 321 is also formed.

In addition, the gate wiring 321 is formed in the active region P for real image, and the gate antistatic wiring 325 is formed outside the break line 328 of the substrate 320 '.

In addition, the antistatic wiring 325 may be formed integrally with the gate wiring 321 by extending the gate wiring 321.

Subsequently, as illustrated in FIG. 6B, a gate insulating film 333 is formed by depositing SiNx or SiOx through a plasma CVD method over the entire surface of the substrate 320 ′ including the gate wiring 321.

Next, although not shown in the drawing, after the semiconductor layer is formed on the gate electrode of the active region, the data wiring crossing the source / drain electrode, the gate wiring 321 and the upper portion of the semiconductor layer. A data pad extending from the data wiring is formed. At this time, the data anti-static wiring for electrically connecting the data pad is formed together.

Subsequently, a protective film 215 is formed on the entire surface of the substrate including the data line (not shown). In this case, since no data material is formed in the corner region of the liquid crystal display panel, the passivation layer 335 is formed on the gate insulating layer 333.

Subsequently, as shown in FIG. 6C, a portion of the gate insulating layer 333 and the passivation layer 335 is removed to expose a portion of the gate wiring 321 and the gate antistatic property. A second contact hole 339b exposing a part of the wiring 325 is formed. In this case, when the gate antistatic wiring 325 is integrally formed with the gate wiring 321, the formation of the second contact hole is omitted.                     

Subsequently, as illustrated in FIG. 6D, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the passivation layer 335, and then patterned. A gate pad 316 is formed to contact the gate line 321 and the gate antistatic line 325 through contact holes 339a and 339b. In this case, a transparent electrode pattern (not shown) electrically connected to the data pad is also formed. The gate pad 316 is connected to a gate driving circuit through a gate TCP. The transparent electrode pattern is connected to a data through data TCP. It is connected to the driving circuit.

As described above, in the present invention, when the gate wiring is formed of an electrode material corroded by contact with air, such as Mo / AlNd, a contact hole for exposing the gate wiring is formed inside the seal pattern, that is, inside the active region. By electrically connecting the gate pad through the contact hole, Mo / AlNd is prevented from contacting the air, thereby preventing corrosion of the gate pad.

Therefore, the present invention prevents corrosion of the gate pad, thereby normally transferring the gate signal supplied from the external driving circuit to the gate wiring, and does not cause signal delay, thereby achieving an effect of further improving image quality. have.

Claims (18)

First and second substrates; A seal pattern formed on a periphery of the first and second substrates to define an active region; A plurality of gate lines and data lines arranged in the first and second directions on the first substrate to define a plurality of pixels; A gate pad formed outside the active region and connected to one side of a gate wiring; A first contact hole formed in the active region and electrically connecting the gate line and the gate pad; And And a liquid crystal layer formed between the first substrate and the second substrate. The liquid crystal display of claim 1, further comprising a gate antistatic wiring electrically connecting all the gate lines as an extension of the gate wiring. The liquid crystal display device of claim 1, wherein the gate pads further include gate antistatic wirings electrically connected to each other. The liquid crystal display of claim 1, wherein the gate pad is electrically connected to a second contact hole exposing a portion of the gate antistatic wiring. The liquid crystal display of claim 1, wherein the gate wiring is formed of Mo / AlNd. The liquid crystal display device of claim 1, wherein the gate pad is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 1, A switching element formed at an intersection of the gate wiring and the data wiring; A pixel electrode formed on each pixel of the first substrate; And And a common electrode formed on the entire surface of the second substrate. The method of claim 1, A switching element formed at an intersection of the gate wiring and the data wiring; And And a common electrode and a pixel electrode disposed on each pixel of the first substrate to form a horizontal electric field. First and second substrates; A seal pattern formed on an outer edge of the first and second substrates to define an active region; A gate wiring arranged in a first direction on a first substrate of the active region;  A gate insulating film formed on an entire surface of the first substrate including the gate wirings; A data line arranged on a gate insulating layer of the active region in a second direction crossing the first direction and defining a plurality of pixels together with the gate line; A passivation layer formed on an entire surface of the first substrate including the data line; A first contact hole removing portions of the gate insulating layer and the passivation layer to expose a portion of one side of the gate wirings formed in the active region; A gate pad formed on the passivation layer outside the seal pattern and connected to the gate wiring through the first contact hole; And And a liquid crystal layer formed on the first substrate and the second substrate. The liquid crystal display of claim 9, further comprising an antistatic wiring electrically connecting the gate pad. The liquid crystal display device of claim 10, wherein the gate pad is electrically connected to a second contact hole exposing a portion of the antistatic wiring line. 10. The liquid crystal display device according to claim 9, wherein the gate wiring is formed of Mo / AlNd. The liquid crystal display of claim 9, wherein the gate pad is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 9, A switching element formed at an intersection of the gate wiring and the data wiring; A pixel electrode formed on each pixel of the first substrate; And And a common electrode formed on the entire surface of the second substrate. The method of claim 9, A switching element formed at an intersection of the gate wiring and the data wiring; And And a common electrode and a pixel electrode disposed on each pixel of the first substrate to form a horizontal electric field. Preparing first and second substrates; Forming gate wirings arranged in a first direction on the first substrate; Forming a gate insulating film formed on an entire surface of the first substrate including the gate wiring; Forming a data line on the gate insulating layer in a second direction crossing the first direction to define a plurality of pixels together with the gate line; Forming a protective film formed on an entire surface of the first substrate including the data wirings; Removing a portion of the gate insulating layer and the passivation layer to form a first contact hole exposing a portion of one side of the gate line; Forming a gate pad on the passivation layer, the gate pad being connected to the gate line through the first contact hole; And And forming a seal pattern defining an active region on any one of the first substrate and the second substrate, wherein the first contact hole is included in the active region. The method of claim 16, wherein the gate wiring is formed of a double layer of Mo / AlNd. The method of claim 16, wherein the gate pad is formed of a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Images