CN109633947B - Testing system and testing method for wiring - Google Patents
Testing system and testing method for wiring Download PDFInfo
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- CN109633947B CN109633947B CN201910113177.5A CN201910113177A CN109633947B CN 109633947 B CN109633947 B CN 109633947B CN 201910113177 A CN201910113177 A CN 201910113177A CN 109633947 B CN109633947 B CN 109633947B
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- 238000012360 testing method Methods 0.000 title claims abstract description 130
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 9
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- 239000004973 liquid crystal related substance Substances 0.000 description 5
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The invention provides a testing system of wiring, comprising a testing signal generating module, a plurality of switch elements, a plurality of wirings and a display panel; the test signal generation module outputs a switching signal, a plurality of first pixel voltages and a plurality of second pixel voltages; each switching element comprises a first control end, a first path end and a second path end, wherein the first control end of each switching element receives a switching signal, and the first path end of each switching element receives a corresponding first pixel voltage or a corresponding second pixel voltage; the multi-layer wires of the plurality of wires are correspondingly connected with the second passage ends of the plurality of switch elements one by one, and each wire is of a laminated structure of three layers of wires; a plurality of data lines of the display panel are correspondingly connected with the multi-layer wiring lines of the plurality of wirings one by one. The invention also provides a testing method of the wiring. The invention can detect whether the short circuit between the wires exists in the wiring of the three layers of wires by only displaying two test images, has simple and rapid test and is beneficial to improving the productivity and the yield.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a testing system and a testing method for wiring.
Background
Because Liquid Crystal Displays (LCDs) have the characteristics of low radiation, small size, light weight, low power consumption and the like, they gradually replace the conventional Cathode Ray Tube (CRT) displays and are widely used in the fields of desktop computers, notebook computers, Personal Digital Assistants (PDAs), mobile phones, televisions and the like. With the development of liquid crystal display technology, the testing of liquid crystal displays, especially the testing of display panels, is becoming more important.
However, as the design requirement for the narrow frame of the display panel of the liquid crystal display is higher and higher, the width of the non-display area is narrower and narrower, so that it is very difficult to arrange all the wires required by the display panel in the non-display area in a single-layer wire arrangement manner, and therefore, a multi-layer wire arrangement manner, for example, a three-layer wire arrangement manner, needs to be considered, and the height space occupied by the wires is correspondingly increased.
However, in the wiring method of the multi-layer wirings, short circuits are likely to occur between the wirings due to the influence of processes such as film formation, development, etching, and the like in the manufacturing process and the environment, resulting in wiring defects. The conventional method for testing the wiring of the single-layer wire cannot fully meet the requirement, and therefore, a method for testing the wiring of a multi-layer wire, such as a three-layer wire, needs to be provided.
Disclosure of Invention
In view of the above, the present invention is directed to a testing system for wiring, which is used to solve the problem of how to test whether there is a short circuit between wirings of a three-layer wiring.
Specifically, the embodiment of the invention provides a wiring test system, which comprises a test signal generation module, a plurality of switch elements, a plurality of wirings and a display panel; the test signal generation module outputs a switching signal, a plurality of first pixel voltages and a plurality of second pixel voltages; each switch element comprises a first control end, a first path end and a second path end, the first control end of each switch element receives the switch signal, and the first path end of each switch element receives the corresponding first pixel voltage or the corresponding second pixel voltage; the multi-layer wires of the plurality of wires are correspondingly connected with the second path ends of the plurality of switch elements one by one, wherein each wire of the plurality of wires is a laminated structure of three layers of wires; a plurality of data lines of the display panel are correspondingly connected with the plurality of layers of wiring lines of the plurality of wires one by one; when the display panel displays a first test image, two adjacent data lines respectively receive two first pixel voltages with opposite polarities; when the display panel displays a second test image, every two adjacent data lines in the plurality of data lines form a group to form a plurality of groups, two data lines belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines belonging to the two adjacent groups respectively receive two second pixel voltages with opposite polarities.
Further, the plurality of first pixel voltages are four first pixel voltages, and the plurality of second pixel voltages are four second pixel voltages; the test signal generation module outputs the first pixel voltages or the second pixel voltages through four voltage output ends, and the four voltage output ends are sequentially connected with the first pass ends of the switch elements in a corresponding and circulating mode by taking the four switch elements as a period.
Further, the plurality of first pixel voltages and the plurality of second pixel voltages are all inverted in polarity once per frame.
Furthermore, the four voltage output ends are sequentially and oppositely arranged at two ends of the test system.
Further, a plurality of gate lines of the display panel all receive the switching signal.
Further, the test signal generation module, the plurality of switching elements, and the plurality of wirings are disposed in a non-display area of the display panel.
Further, the first layer wire, the second layer wire and the third layer wire of each wire have the same line width and completely overlap in projection on a plane perpendicular to the stacking direction.
The embodiment of the invention also provides a test method, which is applied to the test system and comprises the following steps: outputting corresponding switch signals to turn on the plurality of switch elements; outputting a plurality of first pixel voltages, wherein the plurality of first pixel voltages pass through the plurality of switched elements to a plurality of wirings and then pass through a plurality of layers of wirings to a plurality of data lines of the display panel, and each wiring of the plurality of wirings is a laminated structure of three layers of wirings; judging whether a line defect of a pixel row occurs when the display panel displays a first test image, and if the line defect of the pixel row occurs, judging whether a short circuit and a short circuit type occur, wherein two adjacent data lines of the display panel respectively receive two first pixel voltages with opposite polarities; outputting a plurality of second pixel voltages, wherein the plurality of second pixel voltages are transmitted to the plurality of wires through the plurality of switched-on switching elements and then transmitted to a plurality of data lines of the display panel through a plurality of layers of wires of the plurality of wires; and judging whether the line defects of the pixel rows appear when the display panel displays a second test image, and if the line defects of the pixel rows appear, judging whether short circuit and short circuit types occur, wherein every two adjacent data lines in the plurality of data lines form a plurality of groups, two data lines belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines belonging to the two adjacent groups respectively receive two second pixel voltages with opposite polarities.
Further, the step of determining whether a line defect of a pixel row occurs when the display panel displays the first test image, and if the line defect of the pixel row occurs, determining whether a short circuit occurs and a short circuit type includes: if two adjacent pixel rows have line defects, short circuit occurs, and the short circuit type is that two adjacent layers of wiring of the wiring are short circuited; if the line defect occurs in two pixel rows which are separated by two pixel rows, the short circuit occurs and the short circuit type is that the same layer of wires of two adjacent rows of wires is short-circuited.
Further, the step of determining whether a line defect of a pixel row occurs when the second test image is displayed on the display panel, and if a line defect of a pixel row occurs, determining whether a short circuit occurs and a short circuit type includes: if the line defect occurs in two pixel rows which are separated by one pixel row, the short circuit occurs, and the short circuit type is that the first layer wire and the third layer wire of the wire are short-circuited.
According to the wiring testing system and the wiring testing method provided by the embodiment of the invention, whether short circuit exists between the wirings of the three layers of wirings or not can be detected only by displaying two testing images during testing, the testing is simple and rapid, and the productivity and the yield are improved.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a connection diagram of a wiring test system according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a plurality of wirings according to a first embodiment of the present invention.
Fig. 3 is a connection diagram of a wiring test system according to a second embodiment of the present invention.
Fig. 4 is a diagram illustrating a relationship between a plurality of wires and a voltage output terminal of a test signal generating module according to a second embodiment of the invention.
FIG. 5 is a timing diagram illustrating the polarity of the first pixel voltage according to the second embodiment of the present invention.
Fig. 6 is a schematic polarity diagram of each data line when the display panel receives the first pixel voltage according to the second embodiment of the invention.
FIG. 7 is a timing diagram illustrating the polarity of the second pixel voltage according to the second embodiment of the present invention.
Fig. 8 is a schematic polarity diagram of each data line when the display panel receives the second pixel voltage according to the second embodiment of the invention.
FIG. 9 is a flowchart of a testing method according to a third embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the intended purpose, the following detailed description of the embodiments, methods, steps, structures, features and effects of the wiring testing system and the testing method according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
The foregoing and other aspects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. While the invention has been described in connection with specific embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.
First embodiment
Fig. 1 is a connection diagram of a wiring test system according to a first embodiment of the present invention. The present embodiment provides a testing system for wiring. The test system includes a test signal generating module 10, a plurality of switching elements 20, a plurality of wirings 30, and a display panel 40. The test signal generation module 10 outputs a switching signal, a plurality of first pixel voltages and a plurality of second pixel voltages; each of the switching elements 20 includes a first control terminal, a first path terminal, and a second path terminal, the first control terminal of each of the switching elements 20 receives a switching signal, and the first path terminal of each of the switching elements 20 receives a corresponding first pixel voltage or a corresponding second pixel voltage; the multilayer wirings of the plurality of wirings 30 are connected to the second path ends of the plurality of switching elements 20 in a one-to-one correspondence, and each wiring 30 is a laminated structure of three layers of wirings; the data lines of the display panel 40 are connected to the multi-layer traces of the wires 30 in a one-to-one correspondence.
In one embodiment, the plurality of first pixel voltages and the plurality of second pixel voltages may be polarity-inverted once per frame.
In one embodiment, the plurality of switching elements 20 may be, but not limited to, N-type TFTs, NMOS transistors, N-type triodes, or the like. Hereinafter, the plurality of switching elements 20 are all N-type TFTs as an example.
In an embodiment, the plurality of gate lines of the display panel 40 may each receive a switching signal, such that the switching signal may correspondingly turn on the plurality of thin film transistors connected to the gate lines, and simultaneously turn on the plurality of switching elements 20 connected to the test signal generating module 10, such that the plurality of first pixel voltages or the plurality of second pixel voltages may be transmitted to the plurality of wirings 30 through the plurality of turned-on switching elements 20, and then transmitted to the plurality of data lines through the wirings 30, and finally, the corresponding pixel receives the corresponding first pixel voltage or the corresponding second pixel voltage from the corresponding one of the data lines through the plurality of turned-on thin film transistors, such that the display panel 40 displays the corresponding test image.
In an embodiment, the test signal generating module 10, the plurality of switching elements 20, and the plurality of wirings 30 may all be disposed in the non-display region of the display panel 40.
Specifically, fig. 2 is a schematic cross-sectional view of a plurality of wirings 30 according to a first embodiment of the present invention. As shown in fig. 2, the wiring 30 of the present embodiment includes a first layer of trace M1 at the bottom, a second layer of trace M2 at the middle, and a third layer of trace M3 at the top. In an embodiment, the line widths of the first layer trace M1, the second layer trace M2 and the third layer trace M3 of each wire 30 may be the same and the projections on the plane perpendicular to the stacking direction completely overlap. In one embodiment, as shown in fig. 1, the wires 30 may first pass through the connecting members 50 to the display panel 40, and the wires of the wires 30 are then connected to the data lines on the display panel 40.
Specifically, in the test system of the present embodiment, when performing a test, the test signal generating module 10 outputs a corresponding switching signal, for example, a high level, to the first control terminal of each switching element 20, so that each switching element 20 is in a conducting state. Thus, the first path terminal and the second path terminal of each switching element 20 are connected. The first path end of each switch element 20 receives the corresponding first pixel voltage or the corresponding second pixel voltage output by the test signal generating module 10, and the second path ends of the switch elements 20 are connected to the multi-layer traces of the plurality of wires 30 in a one-to-one correspondence manner, for example, the second path end of the first switch element 20 is connected to the first layer trace M1 of the first wire 30, the second path end of the second switch element 20 is connected to the second layer trace M2 of the first wire 30, the second path end of the third switch element 20 is connected to the third layer trace M3 of the first wire 30, the second path end of the fourth switch element 20 is connected to the first layer trace M1 of the second wire 30, and the connections of the second path ends of the other switch elements 20 are sequentially set. Meanwhile, the plurality of layers of wires 30 are connected to the plurality of data lines of the display panel 40 in a one-to-one correspondence, for example, the first layer wire M1 of the first wire 30 is connected to the first data line S1 of the display panel 40, the second layer wire M2 of the first wire 30 is connected to the second data line S2 of the display panel 40, the third layer wire M3 of the first wire 30 is connected to the third data line S3 of the display panel 40, the first layer wire M1 of the second wire 30 is connected to the fourth data line S4 of the display panel 40, the second layer wire M2 of the second wire 30 is connected to the fifth data line S5 of the display panel 40, the third layer wire M3 of the second wire 30 is connected to the sixth data line S6 of the display panel 40, the first layer M1 of the third wire 30 is connected to the seventh data line S7 of the display panel 40, and the second layer M2 of the third wire 30 is connected to the eighth data line S8 of the display panel 40, the third layer trace M3 of the third wire 30 is connected to the ninth data line S9 of the display panel 40, and the connections of the corresponding traces of the remaining wires to the data lines can be arranged in this order.
Therefore, the plurality of first pixel voltages or the plurality of second pixel voltages can be sent to the corresponding wires of the plurality of wires 30 through the plurality of turned-on switching elements 20, and then sent to the plurality of data lines through the corresponding wires of the plurality of wires 30, so that finally, the pixels of the display panel 40 can display corresponding first test images according to the first pixel voltages on the data lines, or can display corresponding second test images according to the second pixel voltages on the data lines.
When the display panel 40 displays the first test image, two adjacent data lines respectively receive two first pixel voltages with opposite polarities. Thus, adjacent columns of pixels on the display panel 40 receive the first pixel voltages of opposite polarity. When the display panel 40 displays the first test image and a line defect of a pixel row occurs, for example, one or more dark lines or bright lines occur in the first test image, whether a short circuit or a short circuit type occurs can be determined according to the line defect of the pixel row. In an embodiment, if two pixel rows adjacent to each other have a line defect, a short circuit occurs and the short circuit type is that two adjacent layers of the wiring 30 are short-circuited, for example, the first layer of wiring M1 and the second layer of wiring M2 of the wiring 30 are short-circuited, or the second layer of wiring M2 and the third layer of wiring M3 of the wiring 30 are short-circuited. In one embodiment, if a line defect occurs in two columns of pixels spaced apart from two columns of pixels, a short circuit occurs in a type of the short circuit occurring in a same layer of the two adjacent columns of wires 30, for example, the second layer of wires M2 of the first wire 30 is short-circuited with the second layer of wires M2 of the second wire 30.
When the display panel 40 displays the second test image, every two adjacent data lines in the plurality of data lines form a group to form a plurality of groups, two data lines belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines belonging to two adjacent groups respectively receive two second pixel voltages with opposite polarities. Therefore, every two adjacent columns of pixel columns on the display panel 40 form a plurality of groups, the two columns of pixel columns belonging to the same group receive the same polarity of the second pixel voltage, and the two columns of pixel columns belonging to the two adjacent groups receive the opposite polarity of the second pixel voltage. When the second test image is displayed on the display panel 40 and a line defect of the pixel row occurs, for example, one or more dark lines or bright lines occur in the second test image, whether a short circuit or a short circuit type occurs can be determined according to the line defect of the pixel row. In one embodiment, if a line defect occurs in two pixel rows separated by one pixel row, a short circuit occurs and the short circuit occurs in the type of the short circuit between the first layer trace M1 and the third layer trace M3 of the wiring 30.
The test system of the wiring 30 provided by the embodiment of the invention can detect whether the wiring 30 of the three layers of wirings has short circuit between the wirings by displaying two test images during testing, the testing is simple and quick, and the productivity and the yield are improved.
Second embodiment
Fig. 3 is a connection diagram of a testing system for wiring 30 according to a second embodiment of the present invention. This embodiment is substantially the same as the first embodiment except that: the plurality of first pixel voltages are four first pixel voltages (D11, D21, D31, and D41), and the plurality of second pixel voltages are four second pixel voltages (D12, D22, D32, and D42); the test signal generating module 10 outputs a plurality of first pixel voltages or a plurality of second pixel voltages through four voltage output terminals (D1, D2, D3, and D4), and the four voltage output terminals (D1, D2, D3, and D4) are connected to the first path terminals of the plurality of switching elements 20 in a one-to-one correspondence.
In one embodiment, the plurality of first pixel voltages and the plurality of second pixel voltages may be polarity-inverted once per frame.
In one embodiment, four voltage output terminals (D1, D2, D3 and D4) are oppositely disposed at two ends of the testing system in sequence, as shown in fig. 3, a first voltage output terminal D1 and a third voltage output terminal D3 are disposed at one side of the system, and a second voltage output terminal D2 and a fourth voltage output terminal D4 are disposed at the other side of the testing system.
Specifically, the four voltage output terminals (D1, D2, D3 and D4) of the test signal generating module 10 may be a first voltage output terminal D1, a second voltage output terminal D2, a third voltage output terminal D3 and a fourth voltage output terminal D4, respectively, the test signal generating module 10 outputs a plurality of first pixel voltages or a plurality of second pixel voltages through the four voltage output terminals (D1, D2, D3 and D4), as shown in fig. 3, the four voltage output terminals (D1, D2, D3 and D4) are connected to the first pass terminals of the plurality of switching elements 20 in a one-to-one correspondence, for example, the first voltage output terminal D1 outputs the first pixel voltage D11 or the first second pixel voltage D12 to the first pass terminal of the first switching element 20, the second voltage output terminal D2 outputs the second first pixel voltage D21 or the second pixel voltage D22 to the second pass terminal of the second switching element 20, the third voltage output terminal D3 outputs the third first pixel voltage D31 or the third second pixel voltage D32 to the first pass terminal of the third switching element 20, the fourth voltage output terminal D4 outputs the fourth first pixel voltage D41 or the fourth second pixel voltage D42 to the first pass terminal of the fourth switching element 20, the first voltage output terminal D1 also outputs the first pixel voltage D11 or the first second pixel voltage D21 to the first pass terminal of the fifth switching element 20, the second voltage output terminal D2 also outputs the second first pixel voltage D21 or the second pixel voltage D22 to the first pass terminal of the sixth switching element 20, the third voltage output terminal D3 also outputs the third first pixel voltage D31 or the third second pixel voltage D32 to the first pass terminal of the seventh switching element 20, and the fourth voltage output terminal D4 to the fourth switching element 20D 4 or the fourth switching element voltage D41 to eight switching elements 20 The first path terminals of the switching elements 20 are connected in this order, and the four voltage output terminals (D1, D2, D3, and D4) output the corresponding first pixel voltage or the corresponding second pixel voltage, respectively, to the first path terminal of a corresponding one of the switching elements 20 of the plurality of switching elements 20.
When the test system of the present embodiment performs a test, the test signal generating module 10 may output a corresponding switching signal, for example, a high level, to the first control terminal of each switching element 20 through the switching signal terminal ADD1, so that each switching element 20 is in a conducting state, and thus, the first path terminal and the second path terminal of each switching element 20 are connected. The first via terminal of each switch element 20 receives the corresponding first pixel voltage or the corresponding second pixel voltage through a corresponding one of the four voltage output terminals (D1, D2, D3, and D4), and the multiple layers of wires 30 are connected to the second via terminals of the multiple switch elements 20 in a one-to-one correspondence, for example, the first layer wire M1 of the first wire 30 is connected to the second via terminal of the first switch element 20, the second layer wire M2 of the first wire 30 is connected to the second via terminal of the second switch element 20, the third layer wire M3 of the first wire 30 is connected to the second via terminal of the third switch element 20, and the first layer M1 of the second wire 30 is connected to the second via terminal of the fourth switch element 20, and the connections of the second via terminals of the other switch elements 20 are sequentially arranged in this order. Thus, the four voltage output terminals (D1, D2, D3, and D4) can output four first pixel voltages or four second pixel voltages, and send the four first pixel voltages or the four second pixel voltages to the plurality of wires 30 through the turned-on plurality of switch elements 20, fig. 4 is a schematic diagram illustrating the correspondence relationship between the plurality of wires and the voltage output terminals of the test signal generating module according to the second embodiment of the present invention, as shown in fig. 4, each layer of wires of the plurality of wires 30 corresponds to one of the four voltage output terminals (D1, D2, D3, and D4).
For example, the first data line S1 of the display panel 40 is connected to the first layer of trace M1 of the first wire 30, the second data line S2 of the display panel 40 is connected to the second layer of trace M2 of the first wire 30, and the third data line S3 of the display panel 40 is connected to the third layer of trace M3 of the first wire 30, and the connections of the remaining data lines are sequentially arranged. Accordingly, the four first pixel voltages or the four second pixel voltages may be further transmitted to the plurality of data lines through the plurality of wires 30, so that the pixels of the display panel 40 may display the corresponding first test images according to the first pixel voltages on the data lines, or may display the corresponding second test images according to the second pixel voltages on the data lines.
FIG. 5 is a timing diagram illustrating the polarity of the first pixel voltage according to the second embodiment of the present invention. Fig. 6 is a schematic diagram illustrating the polarity of each data line when the display panel 40 receives the first pixel voltage according to the second embodiment of the invention. When the display panel 40 displays the first test image, as shown in fig. 5, the test signal generating module 10 may output four first pixel voltages (D11, D21, D31, and D41) through four voltage output terminals (D1, D2, D3, and D4), respectively, and the four first pixel voltages (D11, D21, D31, and D41) may all be inverted once per frame, that is, the first pixel voltages have opposite polarities in odd and even frames, respectively. As shown in fig. 6, two adjacent data lines of the display panel 40 in each frame may respectively receive two first pixel voltages with opposite polarities, for example, a first pixel voltage received by the first data line S1 is opposite in polarity to a second first pixel voltage received by the second data line S2. Table 1 shows a first test image, and as shown in table 1, taking routing of each layer of the first to fourth wires 30 to 30 as an example, the pixel columns of the display panel 40 are made to have corresponding polarities by receiving corresponding first pixel voltages. Thus, by observing whether the first test image has a line defect, it can be determined whether a short circuit occurs in a corresponding trace of the wiring 30.
Table 1 testing of a first test image
As shown in fig. 6 and table 1, the first pixel voltages received by the adjacent data lines on the display panel 40 have opposite polarities, and are arranged in a cycle of polarities "positive", "negative", "positive", and "negative". Thus, two adjacent columns of pixels on the display panel 40 respectively receive two first pixel voltages with opposite polarities. When the display panel 40 displays the first test image and a line defect of a pixel row occurs, for example, one or more dark lines or bright lines occur in the first test image, whether a short circuit or a short circuit type occurs can be determined according to the line defect of the pixel row. In an embodiment, if two rows of pixel columns adjacent to each other have a line defect, a short circuit occurs and the short circuit type is that two adjacent layers of wires of the wire 30 are short-circuited, for example, the first layer wire M1 and the second layer wire M2 of the wire 30 are short-circuited or the second layer wire M2 and the third layer wire M3 of the wire 30 are short-circuited; if the line defect occurs in two columns of pixel columns which are separated by two columns of pixel columns, a short circuit occurs and the short circuit type is that the same layer of the two adjacent columns of wires 30 is short circuited, for example, the second layer of wires M2 of the first wire 30 is short circuited with the second layer of wires M2 of the second wire 30.
FIG. 7 is a timing diagram illustrating the polarity of the second pixel voltage according to the second embodiment of the present invention. Fig. 8 is a schematic diagram illustrating the polarity of each data line when the display panel 40 receives the second pixel voltage according to the second embodiment of the invention. When the display panel 40 displays the second test image, as shown in fig. 7, the test signal generating module 10 can output four second pixel voltages (D12, D22, D32, and D42) through four voltage output terminals, respectively, and the four pixel voltages can be inverted once per frame, that is, the second pixel voltages have opposite polarities in odd and even frames, respectively. As shown in fig. 8, every two adjacent data lines in the plurality of data lines of the display panel 40 form a plurality of groups, two data lines belonging to the same group respectively receive two pixel voltages with the same polarity, for example, in the first data line S1 and the second data line S2 belonging to the same group, the first and second pixel voltages received by the first data line S1 and the second and second pixel voltages received by the second data line S2 are the same in polarity, two data lines belonging to two adjacent groups respectively receive two pixel voltages with opposite polarities, for example, in the second data line S2 and the third data line S3 belonging to two adjacent groups, the second and third pixel voltages received by the second and third data lines S2 and S3 are opposite in polarity. Table 2 shows a second test image, and as shown in table 2, taking the routing of each layer of the first to fourth wires 30 to 30 as an example, the pixel columns of the display panel 40 are made to have corresponding polarities by receiving corresponding second pixel voltages. Thus, by observing whether the second test image has a line defect, it can be determined whether the corresponding trace of the wiring 30 is short-circuited.
Table 2 testing of a second test image
As shown in fig. 8 and table 2, the polarities of the second pixel voltages received by the two data lines belonging to the same group on the display panel are the same, and the polarities of the second pixel voltages received by the two data lines belonging to the two adjacent groups are opposite, so that the polarities of the second pixel voltages are "positive", "negative", and "negative" in a circular arrangement. Therefore, every two adjacent columns of pixel columns on the display panel form a group to form a plurality of groups, the two columns of pixel columns belonging to the same group respectively receive two second pixel voltages with the same polarity, and the two columns of pixel columns belonging to the two adjacent groups respectively receive two second pixel voltages with opposite polarities. When the display panel displays the second test image and line defects of the pixel rows occur, for example, one or more dark lines or bright lines occur in the second test image, whether short circuit or short circuit type occurs can be judged according to the line defects of the pixel rows. In one embodiment, if the line defect occurs in two pixel rows separated by one pixel row, the short circuit occurs and the short circuit type is that the first layer wire and the third layer wire of the wire are short-circuited.
The wiring test system provided by the embodiment of the invention can detect whether the wiring of the three layers of wires has short circuit among the wires by displaying two test images during testing, is simple and quick in test, and is beneficial to improving the productivity and the yield.
Third embodiment
FIG. 9 is a flowchart of a testing method according to a third embodiment of the present invention. The embodiment provides a test method, which includes:
s1, outputting corresponding switch signals to turn on the plurality of switch elements;
s2, outputting a plurality of first pixel voltages, which pass through the plurality of conductive switching elements to the plurality of wires and then pass through the plurality of layers of wires to the plurality of data lines of the display panel, wherein each wire of the plurality of wires is a stacked structure of three layers of wires;
in one embodiment, the plurality of first pixel voltages may be polarity-inverted once per frame.
In one embodiment, the plurality of first pixel voltages may be four first pixel voltages; the four voltage output terminals are connected to the first path terminals of the plurality of switching elements in a one-to-one correspondence.
S3, judging whether the line defect of the pixel row appears when the display panel displays the first test image, and if the line defect of the pixel row appears, judging whether a short circuit and a short circuit type occur, wherein two adjacent data lines of the display panel respectively receive two first pixel voltages with opposite polarities;
in one embodiment, the step of determining whether a line defect of a pixel row occurs when the display panel displays the first test image, and if the line defect of the pixel row occurs, determining whether a short circuit occurs and a type of the short circuit includes: if two adjacent pixel rows have line defects, short circuit occurs, and the short circuit type is that two adjacent layers of wiring of the wiring are short circuited; if the line defect occurs in two pixel rows which are separated by two pixel rows, the short circuit occurs and the short circuit type is that the same layer of wires of two adjacent rows of wires is short-circuited.
S4, outputting a plurality of second pixel voltages, which pass through the plurality of conductive switching elements to the plurality of wires and then pass through the plurality of layers of wires to the plurality of data lines of the display panel, wherein each wire of the plurality of wires is a stacked structure of three layers of wires;
in one embodiment, the plurality of second pixel voltages may be polarity-inverted once per frame.
In one embodiment, the plurality of second pixel voltages may be four second pixel voltages; the plurality of second pixel voltages are output through four voltage output terminals, and the four voltage output terminals are connected to the first path terminals of the plurality of switching elements in a one-to-one correspondence.
And S5, judging whether the line defects of the pixel rows appear when the display panel displays the second test image, and if the line defects of the pixel rows appear, judging whether the short circuit and the short circuit type occur, wherein every two adjacent data lines in the plurality of data lines form a group to form a plurality of groups, two data lines belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines belonging to two adjacent groups respectively receive two second pixel voltages with opposite polarities.
In one embodiment, the step of determining whether a line defect of a pixel row occurs when the display panel displays the second test image, and if the line defect of the pixel row occurs, determining whether a short circuit occurs and a type of the short circuit includes: if the line defect occurs in two pixel rows which are separated by one pixel row, the short circuit occurs, and the short circuit type is that the first layer wire and the third layer wire of the wire are short-circuited.
For the specific implementation of the testing method of this embodiment, please refer to the corresponding descriptions of the first embodiment and the second embodiment, which will not be described herein again.
The testing method of the wiring testing system provided by the embodiment of the invention can detect whether the wiring of the three layers of wires has short circuit between the wires by only displaying two testing images during testing, is simple and quick in testing, and is beneficial to improving the productivity and the yield.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A system for testing wiring (30), comprising:
a test signal generation module (10), the test signal generation module (10) outputting a switching signal, a plurality of first pixel voltages and a plurality of second pixel voltages;
a plurality of switching elements (20), each switching element (20) comprising a first control terminal, a first path terminal and a second path terminal, the first control terminal of each switching element (20) receiving the switching signal, the first path terminal of each switching element (20) receiving the corresponding first pixel voltage or the corresponding second pixel voltage;
a plurality of wires (30), wherein the plurality of wires of the plurality of wires (30) are correspondingly connected with the second path ends of the plurality of switch elements (20) one by one, and each wire (30) of the plurality of wires (30) is a laminated structure of three layers of wires;
the display panel (40), the multiple data lines (41) of the display panel (40) are correspondingly connected with the multiple layers of wiring lines of the multiple wires (30) one by one;
when the display panel (40) displays a first test image, two adjacent data lines (41) respectively receive two first pixel voltages with opposite polarities; when the display panel (40) displays a second test image, every two adjacent data lines (41) in the plurality of data lines (41) form a group to form a plurality of groups, two data lines (41) belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines (41) belonging to two adjacent groups respectively receive two second pixel voltages with opposite polarities.
2. The test system of claim 1, wherein the plurality of first pixel voltages are four first pixel voltages and the plurality of second pixel voltages are four second pixel voltages; the test signal generation module (10) outputs the first pixel voltages or the second pixel voltages through four voltage output ends, and the four voltage output ends are sequentially connected with the first path ends of the switch elements (20) in a corresponding and circulating mode by taking the four switch elements as a period.
3. The test system according to claim 1 or 2, wherein the plurality of first pixel voltages and the plurality of second pixel voltages are each polarity-inverted once per frame.
4. The test system of claim 2, wherein the four voltage output terminals are oppositely disposed at two ends of the test system in sequence.
5. The test system of claim 1, wherein a plurality of gate lines of the display panel (40) each receive the switching signal.
6. The test system according to claim 1, wherein the test signal generating module (10), the plurality of switching elements (20), and the plurality of wirings (30) are disposed in a non-display area of the display panel (40).
7. Test system according to claim 1, characterized in that the first layer trace, the second layer trace and the third layer trace of each wiring (30) have the same line width and overlap completely in projection on a plane perpendicular to the stacking direction.
8. A method for testing a test system for wiring (30), applied to a test system according to any one of claims 1 to 7, comprising:
outputting corresponding switching signals to turn on the plurality of switching elements (20);
outputting a plurality of first pixel voltages, wherein the plurality of first pixel voltages are routed to a plurality of wirings (30) through the plurality of switched elements (20) which are turned on, and then routed to a plurality of data lines (41) of a display panel (40) through a plurality of layers of the plurality of wirings (30), and each wiring (30) of the plurality of wirings (30) is a laminated structure of three layers of routing;
judging whether a line defect of a pixel column occurs when the display panel (40) displays a first test image, and if the line defect of the pixel column occurs, judging whether a short circuit and a short circuit type occur, wherein two adjacent data lines (41) of the display panel (40) respectively receive two first pixel voltages with opposite polarities;
outputting a plurality of second pixel voltages, wherein the plurality of second pixel voltages are routed to the plurality of wires (30) through the plurality of switched elements (20) which are switched on, and then are routed to a plurality of data lines (41) of the display panel (40) through a plurality of layers of the plurality of wires (30);
and judging whether the line defects of the pixel rows appear when the display panel (40) displays a second test image, and if the line defects of the pixel rows appear, judging whether short circuit and short circuit types occur, wherein every two adjacent data lines (41) in the plurality of data lines (41) form a plurality of groups, two data lines (41) belonging to the same group respectively receive two second pixel voltages with the same polarity, and two data lines (41) belonging to the two adjacent groups respectively receive two second pixel voltages with opposite polarities.
9. The method of claim 8, wherein the step of determining whether a line defect of a pixel column occurs when the first test image is displayed on the display panel (40), and if a line defect of a pixel column occurs, determining whether a short circuit occurs and a type of the short circuit comprises:
if two adjacent pixel rows are in line defect, short circuit occurs, and the short circuit type is that two adjacent layers of wires of the wiring (30) are in short circuit;
if the line defect occurs in two pixel columns which are separated by two pixel columns, the short circuit occurs and the short circuit type is that the short circuit occurs in the same layer of wiring of two adjacent columns of wiring (30).
10. The method of claim 8, wherein the step of determining whether the line defect of the pixel column occurs when the second test image is displayed on the display panel (40), and if the line defect of the pixel column occurs, determining whether the short circuit occurs and the type of the short circuit comprises:
if the line defect occurs in two pixel columns which are separated by one pixel column, the short circuit occurs and the short circuit type is that the first layer wire and the third layer wire of the wiring (30) are short-circuited.
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| CN1749813A (en) * | 2004-08-06 | 2006-03-22 | 东芝松下显示技术有限公司 | Display device, inspection method for display device, and inspection device for display device |
| CN102023444A (en) * | 2009-09-15 | 2011-04-20 | 乐金显示有限公司 | Liquid crystal display device and method of fabricating the same |
| CN104793419A (en) * | 2015-05-08 | 2015-07-22 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1749813A (en) * | 2004-08-06 | 2006-03-22 | 东芝松下显示技术有限公司 | Display device, inspection method for display device, and inspection device for display device |
| CN102023444A (en) * | 2009-09-15 | 2011-04-20 | 乐金显示有限公司 | Liquid crystal display device and method of fabricating the same |
| CN104793419A (en) * | 2015-05-08 | 2015-07-22 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
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