CN113571021B - Display panel and display device - Google Patents
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- CN113571021B CN113571021B CN202110745414.7A CN202110745414A CN113571021B CN 113571021 B CN113571021 B CN 113571021B CN 202110745414 A CN202110745414 A CN 202110745414A CN 113571021 B CN113571021 B CN 113571021B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a grid driving circuit, the grid driving circuit comprises N cascaded shift registers, and N is a positive integer greater than 1; the cascade routing comprises a plurality of first cascade routing and a plurality of second cascade routing, each first cascade routing is used for connecting the ith shift register and the ith-delta i shift register, each second cascade routing is used for connecting the ith shift register and the (i + delta i) shift register, i is an integer larger than 1 and smaller than N, and delta i is an integer; the plurality of first cascade wires and the plurality of second cascade wires are respectively positioned on different films of the display panel, and orthographic projections of the plurality of first cascade wires on a substrate of the display panel are at least partially overlapped with orthographic projections of the plurality of second cascade wires on the substrate of the display panel. The display device and the display panel can be beneficial to the design of a display panel or a narrow frame of the display device.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Active Matrix Driving organic light emitting diode (AMOLED) Display panels are increasingly used in the field of high performance Display due to their features of small size, low power consumption, no radiation, and relatively low manufacturing cost.
For the above display panel/display device, the pixel array of the display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines. For the driving of the gate lines, for example, a gate driving circuit formed by a plurality of shift registers connected by cascade routing may be used to provide switching-state voltage signals to a plurality of rows of gate lines, so as to control the plurality of rows of gate lines to be sequentially opened.
Although the use of the shift register enables the display panel/display device to realize a narrower frame, the current frame still cannot meet the consumer demand for a narrower frame.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can reduce the width of a frame area occupied by cascade wiring, and is beneficial to the design of a display panel or a narrow frame of the display device.
In a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a gate driving circuit, where the gate driving circuit includes N cascaded shift registers, where N is a positive integer greater than 1;
the cascade routing comprises a plurality of first cascade routing and a plurality of second cascade routing, each first cascade routing is used for connecting the ith shift register and the ith-delta i shift register, each second cascade routing is used for connecting the ith shift register and the (i + delta i) shift register, i is an integer larger than 1 and smaller than N, and delta i is an integer;
the plurality of first cascade wires and the plurality of second cascade wires are respectively positioned on different films of the display panel, and orthographic projections of the plurality of first cascade wires on a substrate of the display panel are at least partially overlapped with orthographic projections of the plurality of second cascade wires on the substrate of the display panel.
In a second aspect, embodiments of the present application provide a display device, which includes the display panel provided in the first aspect.
According to the display panel and the display device, the display panel comprises a grid driving circuit, the grid driving circuit comprises N cascaded shift registers, and N is a positive integer greater than 1; the cascade routing comprises a plurality of first cascade routing and a plurality of second cascade routing, wherein each first cascade routing is used for connecting an ith shift register and an ith-delta i shift register, each second cascade routing is used for connecting the ith shift register and an ith + delta i shift register, i is an integer larger than 1 and smaller than N, and delta i is an integer; many first cascade are walked line and many second cascade and are walked the line and be located the different retes of display panel respectively, and many first cascade are walked the orthographic projection of line on display panel's substrate and many second cascade and are walked the orthographic projection of line on display panel's substrate at least partial overlap. Since the plurality of first cascade wires and the plurality of second cascade wires are distributed in different film layers, for each film layer distributed with cascade wires, the number of the cascade wires of the film layer in the frame area is reduced by half compared with the related art. Therefore, the number of the cascade wires in each film layer is reduced, so that a plurality of first cascade wires and a plurality of second cascade wires which are overlapped with each other in orthographic projection on the substrate of the display panel only occupy a narrow frame area, the width of the frame area can be designed to be narrower, and the design of the display panel or the narrow frame of the display device is facilitated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings may be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit schematic of a plurality of cascaded shift registers;
fig. 2 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic top view of a display panel according to another embodiment of the present disclosure;
fig. 4 is a wiring diagram of the cascade wiring at different tilt angles;
fig. 5 is a schematic top view illustrating a display panel according to still another embodiment of the present disclosure;
fig. 6 is a schematic top view illustrating a display panel according to still another embodiment of the present disclosure;
FIG. 7 is a schematic top view illustrating a display panel according to still another embodiment of the present disclosure;
fig. 8 is a schematic diagram of a film layer of a display panel according to an embodiment of the present disclosure;
FIG. 9 isbase:Sub>A schematic cross-sectional view taken along line A-A' of FIG. 3 in an embodiment corresponding to FIG. 8;
FIG. 10 is a schematic cross-sectional view of the embodiment corresponding to FIG. 8 taken along line B-B' of FIG. 3;
fig. 11 is a schematic diagram of film layers of a display panel according to another embodiment of the present disclosure;
FIG. 12 isbase:Sub>A schematic cross-sectional view taken along line A-A' of FIG. 3 in an embodiment corresponding to FIG. 11;
FIG. 13 is a schematic cross-sectional view taken along line B-B' of FIG. 3 in an embodiment corresponding to FIG. 11;
FIG. 14 is a circuit diagram of a shift register according to an embodiment of the present application;
FIG. 15 is a schematic top view of the display panel shown in FIG. 14;
fig. 16 is a schematic top circuit diagram of a display panel corresponding to fig. 14 or 15;
FIG. 17 is a circuit diagram of a shift register according to another embodiment of the present application;
fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of, and not restrictive on, the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Before explaining the technical solutions provided in the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the prior art:
as described above, in the display panel, for the driving of the Gate lines, for example, a Gate driving circuit composed of a plurality of shift registers (ASGs) connected by cascade lines may be used to provide switching state voltage signals to a plurality of rows of Gate lines, so as to control the plurality of rows of Gate lines to be sequentially opened.
As shown in fig. 1, for the shift registers in the gate driving circuit except for the first stage shift register ASG and the last stage shift register ASG, each shift register ASG may be connected to the upper n stages of shift registers through an upward cascade trace L1', and at the same time, each shift register may be connected to the lower n stages of shift registers through a downward cascade trace L2', so as to implement signal transmission between the cascade shift registers ASG. Wherein n is a positive integer. For example, for a 4-bit (phase) shift register, n may be equal to 1, i.e. each shift register may be connected to a shift register of a previous stage by an upward cascaded trace L1', while each shift register may be connected to a shift register of a next stage by a downward cascaded trace L2'. For another example, for an 8-bit shift register, n may be equal to 2, that is, each shift register may be connected to two upper stages (upper and upper stages) of shift registers through an upward cascade trace L1', and each shift register may be connected to two lower stages (lower and lower stages) of shift registers through a downward cascade trace L2'. Similarly, for other bit numbers of shift registers, n may be flexibly changed according to the number of bits of the shift register, for example, for a 12-bit shift register, n may be equal to 3; for a 16-bit shift register, n may be equal to 4, which is not limited in the embodiments of the present application.
It should be noted that, in the following drawings of the embodiments of the present application, 12-bit shift registers are taken as examples, but it should be understood that this does not constitute a limitation to the embodiments of the present application, that is, the embodiments of the present application are not limited to that each shift register is connected to a shift register of the upper three levels and a shift register of the lower three levels respectively through a cascade trace. For example, for a 4-bit shift register, each shift register may be connected to a shift register of a previous stage and a shift register of a next stage respectively through cascade wirings. For example, for an 8-bit shift register, each shift register may be connected to an upper two-stage shift register and a lower two-stage shift register through a cascade trace. For example, for a 16-bit shift register, each shift register may be connected to an upper four-stage shift register and a lower four-stage shift register respectively through cascade wiring. Similarly, for the shift registers with other bits, the connection manner of the cascade routing is flexible according to the bits of the shift registers.
The inventor of the present application finds that, in the related art, both the upward cascade trace L1 'and the downward cascade trace L2' are disposed in the same film layer (such as the gate layer) of the display panel, so that the cascade trace arranged in the film layer where the cascade trace is located has a large number, and therefore the cascade trace arranged in the large number occupies a wide frame region, which is not favorable for the design of the display panel or the narrow frame of the display device.
In view of the above research of the inventor, the embodiments of the present application provide a display panel and a display device, which can reduce the width of the bezel area occupied by the cascade wires, and are beneficial to the design of a narrow bezel of the display panel or the display device.
The technical idea of the embodiment of the application is as follows: a plurality of first cascade wires and a plurality of second cascade wires in the cascade wires are distributed in different film layers of the display panel, and orthographic projections of the plurality of first cascade wires on a substrate of the display panel are at least partially overlapped with orthographic projections of the plurality of second cascade wires on the substrate of the display panel. In this way, since the plurality of first cascade wires and the plurality of second cascade wires are distributed among different film layers, for each film layer on which the cascade wires are distributed, the number of the cascade wires of the film layer in the frame area is reduced by half compared with the related art. Therefore, the number of the cascade wires in each film layer is reduced, so that a plurality of first cascade wires and a plurality of second cascade wires which are overlapped with each other in orthographic projection on the substrate of the display panel only occupy a narrow frame area, the width of the frame area can be designed to be narrower, and the design of the display panel or the narrow frame of the display device is facilitated.
The following first describes a display panel provided in an embodiment of the present application.
As shown in fig. 2, the display panel 10 provided in the embodiment of the present application includes a gate driving circuit 100, where the gate driving circuit 100 includes N cascaded shift registers 100a, where N is a positive integer greater than 1.
The plurality of cascaded shift registers 100a are electrically connected through the cascade traces L, each cascade trace L includes a plurality of first cascade traces L1 and a plurality of second cascade traces L2, each first cascade trace L1 is used to connect an ith-stage shift register and an i- Δ i-stage shift register, that is, each first cascade trace L1 is used to connect a current-stage shift register and an upper n-stage shift register. Each second cascade wire is used for connecting the ith shift register and the (i + Δ i) th shift register, that is, each first cascade wire L1 is used for connecting the shift register of the current stage and the shift register of the next n stages. Where i is an integer greater than 1 and less than N, and Δ i is an integer, for example Δ i may be 0,1,2, \8230;.
With continued reference to fig. 2, in the embodiment of the present application, the first cascade wires L1 and the second cascade wires L2 are respectively located on different film layers of the display panel (fig. 2 shows that the first cascade wires L1 and the second cascade wires L2 are located on different metal film layers), and an orthographic projection of the first cascade wires L1 on the substrate of the display panel and an orthographic projection of the second cascade wires L2 on the substrate of the display panel are at least partially overlapped.
In this way, since the plurality of first cascade wires L1 and the plurality of second cascade wires L2 are distributed among different film layers, the number of cascade wires of each film layer in the frame area is reduced by half compared to the related art for the film layer on which the cascade wires are distributed. Therefore, the number of the cascade wires in each film layer is reduced, so that a plurality of first cascade wires and a plurality of second cascade wires which are overlapped with each other in orthographic projection on the substrate of the display panel only occupy a narrow frame area, the width of the frame area can be designed to be narrower, and the design of the display panel or the narrow frame of the display device is facilitated.
Since the cascade trace usually needs to connect the elements/terminals of the shift registers located in different film layers, in order to implement cross-layer connection, a connection hole is usually formed in the display panel, and the connection hole connects different film layers. Thus, the cascade traces can connect the elements/terminals of the shift register located in different film layers by connecting with the connection holes.
However, it has been further found by the inventors of the present application that, in the related art, in the arrangement direction of the N shift registers (the column direction of the display panel), the display panel is generally provided with three or more columns of connection holes, each column including a plurality of connection holes. In the row direction (horizontal direction) of the display panel, the three or more rows of connection holes occupy a wider frame area, which is not favorable for the design of the display panel or the narrow frame of the display device.
In view of the above findings, the inventors of the present application have arrived at a wiring scheme with a reduced number of columns of connection holes, with inventive efforts. Specifically, as shown in fig. 3, the display panel 10 may include a display area AA and a non-display area NA located at least one side of the display area AA, and the gate driving circuit 100 is located in the non-display area NA.
In some embodiments, on a side of the gate driving circuit 100 away from the display area AA, the display panel 10 may further include a plurality of first connection holes 110 sequentially arranged along the first direction and a plurality of second connection holes 120 sequentially arranged along the first direction, the plurality of second connection holes 120 being located between the plurality of first connection holes 110 and the gate driving circuit 100. It should be noted that, in other embodiments, the gate driving circuit 100 may also be located at the outer side, and the plurality of first connection holes 110, the plurality of second connection holes 120, the first cascade line L1, the second cascade line L2 and other signal lines are located at the inner side (close to the display area AA). That is, the plurality of first connection holes 110 and the plurality of second connection holes 120 may also be located on a side of the gate driving circuit 100 close to the display area AA, which is not limited in the embodiment of the present invention.
With reference to fig. 3, the ith shift register 100a may be connected to the ith- Δ i shift register 100a sequentially through the first connection hole 110, the first cascade wire L1 and the second connection hole 120, and the ith shift register 100a is connected to the (i + Δ i) th shift register sequentially through the first connection hole 110 and the second cascade wire L2.
It can be seen from the above that, in the embodiments of the present application, the number of columns of the connection holes is reduced, and the cascade connection of the N-stage shift register is realized only through two columns of connection holes. Compared with three or more rows of connecting holes in the related art, the two rows of connecting holes can reduce the width of the occupied frame area, namely, the width of the occupied frame area is further reduced, which is more beneficial to the design of the narrow frame of the display panel or the display device.
With continued reference to fig. 3, in some embodiments, the cascade trace L may be located in an area with the plurality of first connection holes 110 as the first boundary B1 and the plurality of second connection holes 120 as the second boundary B2. Specifically, in the row direction (horizontal direction) of the display panel, the first cascade lines L1 and the second cascade lines L2 may be located in an area where the first connection holes 110 are the first boundary B1 and the second connection holes 120 are the second boundary B2.
Like this, because many first cascade are walked line L1 and many second cascade and are walked line L2 and all set up in two regional between the connecting hole, so cascade and walk the width that the line occupies the frame region and can reduce to two widths between the connecting hole to further reduce the width that occupies the frame region, be favorable to the design of display panel or display device narrow frame more.
As shown in fig. 4, the inventors of the present application further found that, in the related art, each of the upward cascade traces or the downward cascade traces includes a first sub line l1 extending along the column direction y and a second sub line l2 extending along the row direction x. The row direction x is perpendicular to the column direction y, i.e. the first sub-line l1 is perpendicular to the second sub-line l2. Compared with the situation that the first sub-line l1 and the second sub-line l2 are not perpendicular to each other, when the first sub-line l1 and the second sub-line l2 are perpendicular to each other, the width occupied by the second sub-line l2 in the x direction is the largest (x 3 > x2 > x1, and x1, x2, and x3 represent the width occupied in the x direction), that is, the cascade routing occupies a larger width of the frame area, which is not favorable for the design of the display panel or the narrow frame of the display device.
In view of the above research findings, some embodiments of the present application provide a solution to further reduce the width of the bezel area occupied by the cascaded traces. Specifically, as shown in fig. 5, in some embodiments, each of the first cascaded trace L1 and the second cascaded trace L2 may include at least one inclined trace X, an angle between an extending direction of the inclined trace X and a first direction is a preset angle, the first direction may include an arrangement direction of the N cascaded shift registers, and the preset angle includes an acute angle or an obtuse angle.
Like this, compare the mode of first sub-line L1 and the mutually perpendicular of second sub-line L2 who takes among the prior art, because the first cascade of this application embodiment is walked line L1 and second cascade and is walked at least some in line L2 and be the slope line (and be acute angle or obtuse angle between the first direction), and the width that the slope line took on the horizontal direction is less, so can reduce the cascade line and can occupy the regional great width of frame, be favorable to the design of display panel or display device narrow frame.
Returning to fig. 3, in some specific embodiments, each of the first cascade wires L1 may extend along a first preset direction f1, each of the second cascade wires L2 may extend along a second preset direction f2, and the first preset direction f1 and the second preset direction f2 are mutually crossed and are not perpendicular. That is, when viewed along the thickness direction of the display panel, the projection of the first cascade wires L1 and the projection of the second cascade wires L2 form a crossed mesh structure. The first preset direction and the second preset direction can be flexibly adjusted according to actual conditions, and the first preset direction and the second preset direction are not limited in the embodiment of the application.
In this way, since the whole lines of the first cascade line L1 and the second cascade line L2 are inclined, and the width occupied by the inclined lines in the horizontal direction is smaller, compared with the related art, the width occupied by the cascade lines in the frame area can be reduced to a greater extent, which is beneficial to the design of a display panel or a narrow frame of a display device.
As shown in fig. 5, in some specific embodiments, the first cascaded trace L1 may include a first trace L11 extending along the first direction and a second trace L12 connected to the first trace L11, and the second cascaded trace L2 may include a third trace L21 extending along the first direction and a fourth trace L22 connected to the third trace L21. The second trace L12 may be an inclined trace, and a first preset angle may be formed between the extending direction of the second trace L12 and the first direction; the fourth trace L22 may be an inclined trace, and the extending direction of the fourth trace L22 may have a second predetermined angle with the first direction. The first preset angle and the second preset angle can be flexibly adjusted according to actual conditions, and the first preset angle and the second preset angle are not limited in the embodiment of the application.
In this way, since the second line L12 in the first cascade line L1 and the fourth line L22 in the second cascade line L2 are inclined lines, and the inclined lines occupy a smaller width in the horizontal direction, compared with the related art, the width of the frame area occupied by the cascade lines can be reduced to a greater extent, which is beneficial to the design of a narrow frame of a display panel or a display device.
With continued reference to fig. 5, in some alternative embodiments, the orthographic projection of the first routing lines L11 on the substrate of the display panel completely overlaps with the orthographic projection of the third routing lines L21 on the substrate.
In this way, since the projection of the first trace L11 and the projection of the third trace L21 are completely overlapped, the gap between the first traces L11 (or the third traces L21) is the largest, and light can pass through the gap and pass through the frame region. Therefore, when the frame sealing glue is cured by ultraviolet irradiation, the frame sealing glue has better curing effect because the transmittance of the frame of the display panel is high.
As shown in fig. 6, in some alternative embodiments, the orthographic projection of the first routing lines L11 on the substrate of the display panel partially overlaps with the orthographic projection of the third routing lines L21 on the substrate.
In this way, although the light transmittance is smaller than that of the embodiment shown in fig. 5, since the overlapping area of the projection of the first trace L11 and the projection of the third trace L21 is smaller, the signal interference between the first trace L11 and the third trace L21 can be reduced.
As shown in fig. 7, in some alternative embodiments, an orthographic projection of the first routing lines L11 on the substrate of the display panel does not overlap with an orthographic projection of the third routing lines L21 on the substrate.
In this way, since the projection of the first trace L11 and the projection of the third trace L21 are not overlapped, the signal interference degree between the first trace L11 and the third trace L21 is very small, thereby ensuring the accuracy of signal transmission.
As shown in fig. 8, in some embodiments, the display panel 10 may further include: the light-emitting diode comprises a gate layer 12, a source-drain metal layer 13 and a transparent electrode layer 14 which are positioned on one side of a substrate 11, a first insulating layer 15 positioned between the gate layer 12 and the source-drain metal layer 13, and a second insulating layer 16 positioned between the source-drain metal layer 13 and the transparent electrode layer 14. The transparent electrode layer 14 may be made of indium tin oxide ITO, for example.
In some optional embodiments, the plurality of first cascade wires L1 may be located on the gate layer 12 or the source-drain metal layer 13, and the plurality of second cascade wires L2 may be located on the transparent electrode layer 14.
In other alternative embodiments, the plurality of first cascade wires L1 may be located on the transparent electrode layer 14, and the plurality of second cascade wires L2 may be located on the gate layer 12 or the source-drain metal layer 13.
In the display area AA, a gate electrode of the transistor TFT may be formed in the gate electrode layer 12, and a source and a drain electrode of the transistor TFT may be formed in the source-drain metal layer 13. The display panel 10 may further include another transparent electrode layer 17, and the other transparent electrode layer 17 may be referred to as a first transparent electrode layer and the transparent electrode layer 14 may be referred to as a second transparent electrode layer in the order of arrangement. In the embodiment shown in fig. 8, a first transparent electrode layer (another transparent electrode layer 17) may be located on a side of the first insulating layer 15 away from the substrate 11, and directly connected to the source-drain metal layer 13.
In the embodiment of the present application, the transparent electrode layer 14 in the non-display area NA may be prepared in the same layer as the second transparent electrode layer in the display area AA. In the embodiment shown in fig. 8, the second transparent electrode layer (the transparent electrode layer 14 located in the display area AA) may be a common electrode layer. That is, the transparent electrode layer 14 in the non-display area NA may be prepared by the same process as the common electrode, which is advantageous for process simplification. In other embodiments, the pixel electrode may be located on a side of the common electrode away from the substrate 11 (i.e., the common electrode is located below, and the pixel electrode is located above), and therefore, the second transparent electrode layer (the transparent electrode layer 14 located in the display area AA) may also be a pixel electrode layer, in which case, an insulating layer is disposed between the first transparent electrode layer serving as the common electrode layer and the source/drain metal layer. That is, the transparent electrode layer 14 in the non-display area NA may be prepared by the same process as the pixel electrode, which is beneficial to process simplification.
As shown in fig. 9, in some specific embodiments, the first connection hole 110 may be a cross-line connection hole, i.e., the first connection hole 110 may span multiple film layers. Specifically, the first connection hole 110 may expose the gate layer 12, the source-drain metal layer 13, and the transparent electrode layer 14, for connecting an output terminal (not shown in the figure) of the shift register located in the source-drain metal layer 13, and connecting the first cascade wire located in one of the gate layer 12 and the transparent electrode layer 14 and the second cascade wire located in the other one.
As shown in fig. 10, in some specific embodiments, the second connection hole 120 may expose the gate layer 12 and the transparent electrode layer 14 for connecting a gate electrode (not shown) of a transistor located in the gate layer 12 and a first or second cascade wire located in the transparent electrode layer. The transistors may be transistors in a shift register.
As shown in fig. 11, in other embodiments, different from the embodiment shown in fig. 8, another transparent electrode layer 17 may not be disposed on the same layer as the source/drain metal layer 13, but on a side of the second insulating layer 16 away from the substrate 11. In this way, the other transparent electrode layer 17 may be electrically connected to the source or drain of the transistor TFT in the source-drain metal layer 13 through the via hole. Accordingly, the display panel 10 may further include a third insulating layer 18 between the transparent electrode layer 14 and the second insulating layer 16, and the third insulating layer 18 may serve as a dielectric layer between the pixel electrode and the common electrode.
In the embodiment shown in fig. 11, the plurality of first cascade wires L1 may be located on the gate layer 12 or the source-drain metal layer 13, and the plurality of second cascade wires L2 may be located on the transparent electrode layer 14; alternatively, the plurality of first cascade wires L1 may be located on the transparent electrode layer 14, and the plurality of second cascade wires L2 may be located on the gate layer 12 or the source-drain metal layer 13.
As shown in fig. 12 and 13, compared to the embodiment shown in fig. 9 and 10, the first connection hole 110 and the second connection hole 120 both penetrate through the third insulating layer 18, and other parts are the same as those in fig. 9 and 10, and are not described again.
As shown in fig. 14 and 15, in some embodiments, each shift register 100a may include:
a first node charging module 1001, a first terminal of the first node charging module 1001 is electrically connected to a first control potential terminal FW, and a second terminal of the first node charging module 1001 is electrically connected to a first node P;
a first node discharge module 1002, a first end of the first node discharge module 1002 being electrically connected to the second control potential end BW, a second end of the first node discharge module 1002 being electrically connected to the first node P;
each first cascade wire L1 is specifically configured to connect the output end OUT of the ith shift register 100a and the control end Gn +1 of the first node discharging module 1002 of the i- Δ i shift register 100a, and each second cascade wire L2 is specifically configured to connect the output end OUT of the ith shift register 100a and the control end Gn-1 of the first node charging module 1001 of the i + Δ i shift register 100 a.
In this way, since the plurality of first cascade wires L1 and the plurality of second cascade wires L2 are distributed among different film layers, the number of cascade wires of each film layer in the frame area is reduced by half compared to the related art for the film layer on which the cascade wires are distributed. Like this, because the quantity of cascade line reduces in every rete, so a plurality of first cascade lines and a plurality of second cascade lines that orthographic projection on display panel's substrate overlapped each other just can occupy narrower frame region, and then the width in frame region can design narrower, is favorable to the design of display panel or display device narrow frame.
Corresponding to the embodiment shown in fig. 15, in combination with fig. 14 and 16, in some specific embodiments, the first node charging module 1001 may include a first transistor T1, and the first node discharging module 1002 may include a second transistor T2, where:
a control electrode of the first transistor T1 of the i-th stage shift register 100a is electrically connected to the output end OUT of the i- Δ i-th stage shift register through the second cascade trace L2, a first electrode of the first transistor T1 of the i-th stage shift register 100a is electrically connected to the first control potential terminal FW, and a second electrode of the first transistor T1 of the i-th stage shift register 100a is electrically connected to the first node P;
the control electrode of the second transistor T2 of the i-th shift register 100a is electrically connected to the output end OUT of the i + Δ i-th shift register 100a through the first cascade trace L1, the first electrode of the second transistor T2 of the i-th shift register 100a is electrically connected to the second control potential end BW, and the second electrode of the second transistor T2 of the i-th shift register 100a is electrically connected to the first node P.
In the embodiment of the present application, the first control potential terminal FW and the second control potential terminal BW mainly control the forward scan and the reverse scan, the forward scan is turned on one by one from G1 to Gn, and the reverse scan is turned on one by one from Gn to G1. When scanning in the forward direction, the first transistor T1 is used for charging the first node P, and the second transistor T2 is used for discharging the first node P; when scanning in the reverse direction, the first transistor T1 is used to discharge the first node P, and the second transistor T2 is used to charge the first node P.
In a specific implementation, the gate of each transistor is used as the control electrode, and the first electrode of each transistor may be used as the source and the second electrode may be used as the drain, or the first electrode may be used as the drain and the second electrode may be used as the source, depending on the signal of the gate of each transistor and the type of the gate, which is not distinguished herein.
With continued reference to fig. 14-16, in some embodiments, each shift register 100a may further include: the first output module 1003, a control end of the first output module 1003 is electrically connected to the first node P, a first end of the first output module 1003 is electrically connected to the first clock signal end CKB, and a second end of the first output module 1003 is electrically connected to the output end Gout of the shift register, and is configured to transmit the first clock signal of the first clock signal end CKB to the output end Gout of the shift register under the control of the first node P.
It is easy to understand that the output end Gout of each stage of shift register can be connected with a row of scanning lines corresponding to the stage of shift register, and meanwhile, the output end Gout of each stage of shift register can also be connected with n stages of shift registers and n stages of shift registers below the shift register through cascade routing.
It should be noted that the dotted box f indicates that transistors, capacitors, and traces are not listed, that is, the shift register 100a in the embodiment of the present application may include other transistors, capacitors, and traces besides the first node charging module 1001, the first node discharging module 1002, and the first output module 1003, which is not limited in the embodiment of the present application.
As shown in fig. 17, in some specific embodiments, the first output module 1003 may include a third transistor T3, a control electrode of the third transistor T3 is electrically connected to the first node P, a first electrode of the third transistor T3 is electrically connected to the first clock signal terminal CKB, and a second electrode of the third transistor T3 is electrically connected to the output terminal Gout of the shift register. The third transistor T3 transmits the first clock signal output from the first clock signal terminal CKB to the output terminal Gout of the shift register under the control of the first node P.
Fig. 17 schematically shows an 11T2C circuit. As shown in fig. 17, the shift register 100a in the embodiment of the present application may include other transistors and capacitors in addition to the first transistor T1, the second transistor T2, and the third transistor T3. In addition to the 11T2C circuit shown in fig. 17, the shift register 100a may be another type of circuit, such as a 9T2C circuit, that is, including 9 transistors and 2 capacitors; for example, an 11T1C circuit may also be used, i.e., including 11 transistors and 1 capacitor. It is to be understood that the 11T2C circuit shown in fig. 17 is merely an example, and the shift register according to the embodiment of the present application is not limited thereto.
As shown in fig. 17, the first transistor T1 in the embodiment of the present application may be a transistor T1 in an 11T2C circuit, which is used to charge the first node P during the forward scan, i.e. to input positive electricity FW to raise the potential at point P. The second transistor T2 in the embodiment of the present application may be a transistor T2 in an 11T2C circuit, which is used to discharge the first node P during the forward scan, i.e. to input negative FW and pull down the potential at point P. The third transistor T3 in the embodiment of the present application may be a transistor T3 in an 11T2C circuit, and is used for transmitting the first clock signal from the first clock signal terminal CKB to the output terminal Gout of the shift register under the control of the first node P.
Based on the display panel provided in the foregoing embodiment, correspondingly, the present application also provides a display apparatus, as shown in fig. 18, the display apparatus 1000 may include an apparatus body 20 and the display panel 10 in the foregoing embodiment, and the display panel 10 is covered on the apparatus body 20. The apparatus body 20 may be provided with various devices, such as a sensing device, a processing device, and the like, but is not limited thereto. The display device 1000 may be a device having a display function, such as a mobile phone, a computer, a tablet computer, a digital camera, a television, and electronic paper, and is not limited herein.
It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts between the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. For the display panel embodiment and the display device embodiment, relevant points can be referred to the description parts of the pixel driving circuit embodiment and the array substrate embodiment. The present application is not limited to the particular structures described above and shown in the figures. Those skilled in the art may make various changes, modifications and additions after comprehending the spirit of the present application. Also, a detailed description of known techniques is omitted herein for the sake of brevity.
It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first", "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.
Claims (13)
1. The display panel is characterized by comprising a grid driving circuit, wherein the grid driving circuit comprises N cascaded shift registers, and N is a positive integer greater than 1;
the plurality of cascaded shift registers are electrically connected through cascaded wires, each cascaded wire comprises a plurality of first cascaded wires and a plurality of second cascaded wires, each first cascaded wire is used for connecting an ith shift register and an i-Delta i shift register, each second cascaded wire is used for connecting the ith shift register and an i + Delta i shift register, i is an integer larger than 1 and smaller than N, and Delta i is an integer;
the plurality of first cascade wires and the plurality of second cascade wires are respectively positioned on different film layers of the display panel, and orthographic projections of the plurality of first cascade wires on a substrate of the display panel are at least partially overlapped with orthographic projections of the plurality of second cascade wires on the substrate of the display panel;
the first cascade wiring and the second cascade wiring both comprise at least one section of inclined wiring, the angle between the extending direction of the inclined wiring and a first direction is a preset angle, the first direction comprises the arrangement direction of the N cascaded shift registers, and the preset angle comprises an acute angle or an obtuse angle;
the display panel comprises a display area and a non-display area positioned on at least one side of the display area, and the grid drive circuit is positioned in the non-display area;
the display panel further comprises a plurality of first connecting holes and a plurality of second connecting holes, wherein the plurality of first connecting holes are sequentially arranged along a first direction, the plurality of second connecting holes are sequentially arranged along the first direction, and the plurality of second connecting holes are located between the plurality of first connecting holes and the gate driving circuit;
the ith level shift register is connected with the ith-delta i level shift register sequentially through the first connecting hole, the first cascade wire and the second connecting hole, and the ith level shift register is connected with the (i + delta i) level shift register sequentially through the first connecting hole and the second cascade wire.
2. The display panel of claim 1, wherein the cascade trace is located in an area with the first connection holes as a first boundary and the second connection holes as a second boundary.
3. The display panel according to claim 1, wherein the first cascade wires extend along a first preset direction, and the second cascade wires extend along a second preset direction;
the first preset direction and the second preset direction are mutually crossed and not perpendicular.
4. The display panel according to claim 1, wherein the first cascade trace comprises a first trace extending along the first direction and a second trace connected to the first trace, and the second cascade trace comprises a third trace extending along the first direction and a fourth trace connected to the third trace;
the second routing is an inclined routing, and a first preset angle is formed between the extending direction of the second routing and the first direction;
the fourth wire is an inclined wire, and a second preset angle is formed between the extending direction of the fourth wire and the first direction.
5. The display panel according to claim 4,
and the orthographic projection of the first routing wire on the substrate of the display panel is overlapped with the orthographic projection of the third routing wire on the substrate.
6. The display panel according to claim 4,
the orthographic projection of the first routing wire on a substrate of the display panel is not overlapped with the orthographic projection of the third routing wire on the substrate.
7. The display panel according to claim 1, wherein the display panel further comprises: the substrate comprises a substrate, a grid layer, a source drain metal layer, a transparent electrode layer, a first insulating layer and a second insulating layer, wherein the grid layer, the source drain metal layer and the transparent electrode layer are positioned on one side of the substrate;
the plurality of first cascade wires are positioned on the gate electrode layer or the source drain electrode metal layer, and the plurality of second cascade wires are positioned on the transparent electrode layer;
or,
the first cascade wires are located on the transparent electrode layer, and the second cascade wires are located on the gate electrode layer or the source drain metal layer.
8. The display panel according to claim 1, wherein the first connection hole exposes a gate layer, a source-drain metal layer, and a transparent electrode layer, for connecting an output end of the shift register in the source-drain metal layer, and connecting the first cascade wire in one of the gate layer and the transparent electrode layer and the second cascade wire in the other one;
the shift register comprises at least one transistor, and the second connecting hole exposes the gate layer and the transparent electrode layer and is used for connecting the gate of the transistor in the gate layer with the first cascade wiring or the second cascade wiring in the transparent electrode layer.
9. The display panel according to claim 1, wherein each of the shift registers comprises:
the first node charging module is electrically connected with a first control potential end at a first end and a first node at a second end;
a first node discharge module, a first end of the first node discharge module being electrically connected to a second control potential end, a second end of the first node discharge module being electrically connected to the first node;
each first cascade wire is specifically used for connecting the output end of the i-th shift register and the control end of the first node discharging module of the i- Δ i shift register, and each second cascade wire is specifically used for connecting the output end of the i-th shift register and the control end of the first node charging module of the i + Δ i shift register.
10. The display panel of claim 9, wherein the first node charging module comprises a first transistor and the first node discharging module comprises a second transistor, wherein:
a control electrode of the first transistor of the ith-stage shift register is electrically connected with an output end of the ith- Δ i-stage shift register through the second cascade wire, a first electrode of the first transistor of the ith-stage shift register is electrically connected with the first control potential end, and a second electrode of the first transistor of the ith-stage shift register is electrically connected with the first node;
the control electrode of the second transistor of the ith-stage shift register is electrically connected with the output end of the (i + Deltai) -th-stage shift register through the first cascade wiring, the first electrode of the second transistor of the ith-stage shift register is electrically connected with the second control potential end, and the second electrode of the second transistor of the ith-stage shift register is electrically connected with the first node.
11. The display panel according to claim 9, wherein each of the shift registers further comprises:
the control end of the first output module is electrically connected with the first node, the first end of the first output module is electrically connected with the first clock signal end, the second end of the first output module is electrically connected with the output end of the shift register, and the first output module is used for transmitting the first clock signal of the first clock signal end to the output end of the shift register under the control of the first node.
12. The display panel according to claim 11, wherein the first output module comprises a third transistor, a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first clock signal terminal, and a second electrode of the third transistor is electrically connected to an output terminal of the shift register.
13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.
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| CN115206997A (en) * | 2022-07-01 | 2022-10-18 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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