CN108873521B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN108873521B CN108873521B CN201810700405.4A CN201810700405A CN108873521B CN 108873521 B CN108873521 B CN 108873521B CN 201810700405 A CN201810700405 A CN 201810700405A CN 108873521 B CN108873521 B CN 108873521B
- Authority
- CN
- China
- Prior art keywords
- display area
- dummy
- shift register
- array substrate
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention provides an array substrate, a display panel and a display device, wherein the array substrate provided by the embodiment of the invention comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a special-shaped non-display area and is positioned between a special-shaped boundary of the display area and a special-shaped edge of the array substrate; the dummy scanning lines of the array substrate are positioned in the special-shaped non-display area, so that the occupied space of the dummy scanning lines in the non-display area can be reduced, the area of the non-display area of the array substrate is reduced, and the narrow frame of the display device is facilitated.
Description
Technical Field
The invention relates to the technical field of display, and in particular relates to an array substrate, a display panel and a display device comprising the array substrate and the display panel.
Background
In a conventional display device, the display panel has a rectangular structure. However, with the continuous development of display technology and the diversified demands of users for the appearance of display devices, the special-shaped display panels are more and more widely used.
Taking a liquid crystal display panel as an example, a liquid crystal display panel and a liquid crystal display device are one of the mainstream display technologies at present, and the liquid crystal display panel comprises a plurality of pixel units, and each pixel unit comprises a scanning line, a data line and a thin film transistor which are crossed in an insulating manner. The data lines receive data signals and control the driving voltage of each sub-pixel, so that the rotation angle of the liquid crystal is controlled, and different light transmittance is realized. The scanning signal is provided by the gate driving device. The grid driving device generates a plurality of scanning signals and transmits the scanning signals to the scanning lines according to a certain sequence so as to sequentially start the thin film transistor elements.
The grid driving device mainly comprises a shift register (ASG) and other components, wherein a dummy shift register (dum ASG) is arranged at the front end and the rear end of each shift register, the dummy shift register does not provide scanning signals for the grid, and the dummy shift register is used for preventing the grid from repeatedly outputting and high-temperature shaking. However, the dummy shift registers occupy a certain layout space, and two dummy shift registers are generally arranged in the vertical direction due to the need for panel wiring, which increases the width of the upper and lower frames of the liquid crystal panel. For example: the 8 phase shift registers and the 16 phase shift registers need 8 dummy shift registers, and the 16 phase shift registers need 16 dummy shift registers, which is not beneficial to narrow frame, thereby affecting the narrow frame of the liquid crystal display panel.
Disclosure of Invention
The invention aims to provide an array substrate, a display panel and a display device comprising the same, so as to solve the problem that a frame is wide due to the existence of a dummy shift register.
First, the present invention provides an array substrate, including a display area and a non-display area surrounding the display area, the display area including a first boundary extending in a column direction, a second boundary extending in a row direction, and a shaped boundary connected between the first boundary and the second boundary, the array substrate including a first edge extending in the column direction, a second edge extending in the row direction, and a shaped edge connected between the first edge and the second edge, the non-display area including a shaped non-display area between the shaped boundary and the shaped edge; the array substrate further includes: the scanning lines and the data lines are positioned in the display area, the scanning lines extend along the row direction and are arranged along the column direction, the data lines extend along the column direction and are arranged along the row direction, and the scanning lines and the data lines are arranged in a crossed and insulated mode; a gate driving circuit located in the non-display region, the gate driving circuit including a plurality of shift registers including at least one dummy shift register, the shift registers except the dummy shift register being electrically connected to the scan lines and supplying scan signals to the scan lines; at least one dummy scanning line located in the special-shaped non-display area, wherein one end of the dummy scanning line is electrically connected to the dummy shift register.
In an embodiment of the present invention, the array substrate further includes a plurality of data signal leads electrically connected to the plurality of data lines in a one-to-one correspondence, and configured to provide data signals to the data lines; the plurality of data signal leads comprise a plurality of first data signal leads, the plurality of first data signal leads penetrate through the special-shaped non-display area, and the dummy scanning lines are arranged in an insulating and overlapping mode with at least part of the first data signal leads.
In an embodiment of the invention, the array substrate includes a first metal layer and a second metal layer stacked in sequence, the dummy scan lines and the scan lines are formed on the first metal layer, and the data signal leads and the data lines are formed on the second metal layer.
In one embodiment of the present invention, the dummy scan line is located between the display area and the dummy shift register, the dummy scan line includes a second portion close to the display area and a first portion far from the display area, the second portion is electrically connected to the dummy shift register through the first portion; the second portion is arranged to be insulated and overlapped with at least a part of the first data signal lead, and the width of the second portion in the column direction is larger than that of the first portion in the column direction.
In one embodiment of the present invention, the dummy scan line is located between the display area and the dummy shift register, the dummy scan line includes a second portion close to the display area and a first portion far from the display area, the second portion is electrically connected to the dummy shift register through the first portion; the second part is arranged to be insulated and overlapped with at least part of the first data signal lead, and the second part is S-shaped.
In one embodiment of the present invention, the dummy scan line is located between the display area and the dummy shift register, the dummy scan line includes a second portion close to the display area and a first portion far from the display area, the second portion is electrically connected to the dummy shift register through the first portion; the second part is arranged to be insulated and overlapped with at least one part of the first data signal lead, wherein the second part comprises a plurality of branches extending along the row direction, and one end of all the branches is electrically connected to one end of the first part far away from the dummy shift register.
In one embodiment of the present invention, the gate driving circuit includes at least two shift register groups, each of the shift register groups includes a plurality of shift registers electrically connected to each other, and the array substrate includes at least two dummy scan lines electrically connected to the at least two shift register groups, respectively.
In one embodiment of the invention, the array substrate comprises two special-shaped non-display areas which are respectively positioned at two sides of the display area in the row direction; the at least two shift register groups are respectively positioned at the left side and the right side of the display area, and the at least two dummy scanning lines are respectively positioned in the two special-shaped non-display areas.
Secondly, the invention also provides a display panel comprising the array substrate.
In addition, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the technical scheme provided by the invention has the following advantages: the array substrate provided by the invention comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a special-shaped non-display area and is positioned between a special-shaped boundary of the display area and a special-shaped edge of the array substrate; the dummy scanning lines of the array substrate are positioned in the special-shaped non-display area, so that the occupied space of the dummy scanning lines in the non-display area can be reduced, the area of the non-display area of the array substrate is reduced, and the narrow frame of the display device is facilitated.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a partial structure of a gate driving circuit on the array substrate shown in fig. 1;
FIG. 3 is a schematic diagram of a portion of a gate driving circuit on the array substrate shown in FIG. 1;
FIG. 4 is a schematic view of a partial structure of the array substrate shown in FIG. 1;
FIG. 5 is a schematic view of another partial structure of the array substrate shown in FIG. 1;
FIG. 6 is a schematic view of another partial structure of the array substrate shown in FIG. 1;
FIG. 7 is a schematic view of another partial structure of the array substrate shown in FIG. 1;
fig. 8 is a schematic diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The invention discloses an array substrate, which comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a special-shaped non-display area and is positioned between a special-shaped boundary of the display area and a special-shaped edge of the array substrate; the dummy scanning lines of the array substrate are positioned in the special-shaped non-display area, so that the occupied space of the dummy scanning lines in the non-display area can be reduced, the area of the non-display area of the array substrate is reduced, and the narrow frame of the display device is facilitated.
First, an array substrate according to an embodiment of the present invention is provided, as shown in fig. 1, fig. 1 is a schematic structural diagram of the array substrate according to the embodiment of the present invention, and the array substrate 01 is provided with a display area AA and a non-display area BB disposed around the display area AA. Wherein the display area AA includes a first boundary L11 extending in the column direction D1, a second boundary L12 extending in the row direction D2, and a shaped boundary L13 connected between the first boundary L11 and the second boundary L12; the array substrate 01 includes a first edge L21 extending along a column direction D1, a second edge L22 extending along a row direction D2, and a shaped edge L23 connected between the first edge L21 and the second edge L22, wherein the first edge L21, the second edge L22, and the shaped edge L23 are cut edges of the array substrate 01, the first boundary L11, the second boundary L12, and the shaped edge L13 are boundaries between a display area AA and a non-display area BB, and the non-display area BB is located between the display area AA and the cut edges of the array substrate. Further, the non-display region BB includes a normal non-display region BB0 and a shaped non-display region BB1, wherein a portion of the non-display region BB located between the first boundary L11 and the first edge L21, and a portion located between the second boundary L12 and the second edge L22 are a normal non-display region BB 0; the portion of the non-display region BB located between the shaped boundary L13 and the shaped edge L23 is a shaped non-display region BB 1.
In this embodiment, the array substrate 01 has a rounded rectangle, or the display area AA of the array substrate 01 has a rounded rectangle. The array substrate 01 comprises an upper end and a lower end which are positioned in the column direction D1, and a left side and a right side which are positioned in the row direction D2, wherein the regular non-display regions BB0 of the array substrate 01 are respectively positioned at the left side, the right side, the upper end and the lower end of the array substrate 01, and the irregular non-display regions BB1 are arranged adjacent to four cutting angles of the array substrate 01 and are respectively positioned between two adjacent regular non-display regions BB 0.
The array substrate 01 further includes a pixel array disposed in the display area AA, wherein the pixel array includes a plurality of data lines DL and a plurality of scan lines GL, the data lines DL and the scan lines GL are arranged in parallel to define a plurality of pixels, each pixel includes a display driving switch (not shown), for example, a thin film transistor having three terminals, i.e., a gate terminal, a source terminal and a drain terminal, and a pixel electrode (not shown), and the pixel electrode is connected to the source terminal (or the drain terminal) of the thin film transistor. The pixel array may include, for example, a plurality of rows and a plurality of columns of pixels, the drain (or source) of the thin film transistor in each column of pixels may be connected to, for example, the same data line DL, from which the data signal is provided to the pixels in the corresponding column, and the gate of the thin film transistor in each row of pixels may be connected to, for example, the same scan line GL, from which the scan signal is provided to the pixels in the corresponding row.
In the present embodiment, each data line DL extends in the column direction D1 and is arranged in the row direction D2, and each scan line GL is arranged in the column direction D1 and extends in the row direction D2. The gate driving circuit 10 is located in the non-display area BB on one side of the array substrate 01, and each of the scanning lines GL is electrically connected to a corresponding interface in the gate driving circuit 10. As to the specific structure of the gate driving circuit 10, please refer to fig. 2 and 3, which can be, for example: the gate driving circuit 10 includes a plurality of shift registers including a plurality of normal shift registers 11 and at least one dummy shift register Dum ASG, wherein each normal shift register 11 is connected to one row of scanning lines GL, so that scanning signals can be sequentially input to the scanning lines GL to realize progressive scanning of the scanning lines GL.
Unlike the conventional shift register 11, the dummy shift register Dum ASG does not connect the scan lines GL of the display area AA and does not supply the scan signals to the scan lines GL of the display area AA. In the gate driving circuit 10, a plurality of shift registers are electrically connected to each other, and in the present embodiment, the plurality of conventional shift registers 11 include a plurality of stages of shift registers, for example: ASG 1 is the first stage shift register, ASG 2 is the second stage shift register, ASG 3 is the third stage shift register, ASG 4 is the fourth stage shift register, and so on. The first stage shift register ASG 1 is electrically connected to the dummy shift register Dum ASG, and receives the signal transmitted from the dummy shift register Dum ASG, and the first stage shift register ASG 1 is electrically connected to the second stage shift register ASG 2, and transmits the signal to the second stage shift register ASG 2. When a termination signal is given to the dummy shift register Dum ASG, the second shift register ASG 2 receives the signal sent from the first shift register ASG 1, transmits the signal to the next shift register (i.e., the third shift register ASG 3), and gives a termination signal to the previous shift register (i.e., the first shift register ASG 1), and so on.
In an embodiment of the present invention, two dummy shift registers Dum ASG, which are the first dummy shift register 111 and the second dummy shift register 112, respectively, may be included. The input end of the first dummy shift register 111 is connected to an integrated driving circuit (not shown in the figure) and receives a start pulse signal transmitted from the integrated driving circuit, the output end of the first dummy shift register 111 is connected to one end of the first stage shift register G1, and the output end of the second dummy shift register 112 is connected to one end of the nth stage shift register. For example, if there are N shift registers in the gate driving circuit 10, the end of the gate driving circuit 10 is connected as shown in fig. 3, and one end of the gate driving circuit 10 is connected to the output end of the second dummy shift register. In fig. 3, two nth stage shift registers (ASG N and ASG N-1) are connected to the output terminal of the second dummy shift register 112, and the output terminal of the second dummy shift register 112 is connected to the driving ic for receiving the start pulse signal transmitted from the driving ic. This way can compromise the forward scanning and the reverse scanning of array substrate.
In general, the plurality of scan lines GL connected to the gate driving circuit 10 are uniformly distributed in the entire display area AA, the lengths of the plurality of scan lines GL are substantially equal, and the number of pixels connected to each scan line GL is substantially equal, so that the resistances and coupling capacitances of the plurality of scan lines GL are substantially equal, the loads of the regular shift registers 11 in the gate driving circuit 10 are also substantially equal, and in order to match the loads of the dummy shift registers Dum ASG with the loads of the regular shift registers 11, in this embodiment, the array substrate 01 further includes at least one dummy scan line Dum G connected to the corresponding dummy shift register Dum ASG.
In the embodiment of the invention, the gate driving circuit 10 is located in the non-display area BB on one side of the array substrate 01, the dummy shift register Dum ASG and the dummy scan line Dum G are all located in the special-shaped non-display area BB1, and the dummy scan line Dum G is located between the display area AA and the dummy shift register Dum ASG.
The dummy scan lines Dum G may be configured as S-shaped traces as shown in fig. 4, for example, so that all the traces may be routed in the special-shaped non-display area BB1 without extending into the normal non-display area BB0 at the upper and lower ends of the array substrate 01 under the condition that the traces have a sufficient length or sufficient resistance and coupling capacitance, so as to reduce the area of the non-display areas BB at the upper and lower ends of the array substrate 01, which is beneficial for implementing a narrow bezel design. The S-shaped wiring comprises a plurality of sections of wiring which are connected with each other, the length of each section of wiring can be set according to the shape of the special-shaped non-display area BB1, or can be set according to the boundary shape of the display area AA, which is adjacent to the special-shaped non-display area BB1, so that the space of the special-shaped non-display area BB1 is fully utilized, the space area occupied by the dummy scanning line Dum G is reduced, and the narrow frame is facilitated.
Taking the second dummy shift register 112 as an example, in the present embodiment, the second dummy shift register 112 is routed in an S-shape and is entirely located in the irregular non-display area BB1 at the lower left corner of the array substrate 01. Further, the array substrate 01 further includes a plurality of data signal leads Dx located in the non-display area, and respectively electrically connected to the plurality of data lines DL in a one-to-one correspondence, and providing data signals to the data lines DL. The plurality of data signal leads Dx1, which pass through the non-display BB1 and are electrically connected to the data driving circuit, are provided. The dummy scan line Dum G is disposed to be insulated and overlapped with at least a portion of the first data signal lead Dx1, and a coupling capacitance is generated between the dummy scan line Dum G and the first data signal lead Dx1 overlapped therewith. By increasing the length of the dummy scan line Dum G, the resistance of the dummy scan line Dum G can be increased, and the overlapping area between the dummy scan line Dum G and the data signal lead Dx can be increased, thereby increasing the coupling capacitance between the dummy scan line Dum G and the data signal lead Dx. Since the load is proportional to the resistance and the coupling capacitance, the load of the dummy scan line Dum G increases accordingly. Since the dummy scan line Dum G is connected to the dummy shift register, increasing the load of the dummy scan line Dum G is equivalent to increasing the load of the dummy shift register, so that the load of the dummy shift register matches the load of the conventional shift register. The charging state of the pixels in the display area of the data line can be ensured to be consistent, and the display effect is improved.
In an embodiment of the invention, the array substrate 01 includes a first metal layer M1 and a second metal layer M2 stacked in sequence, wherein the dummy scan lines Dum G and GL are formed on the first metal layer M1, and the data signal leads Dx and DL are formed on the second metal layer M2.
Fig. 5 is another routing manner of the dummy scan lines according to an embodiment of the present invention, in this embodiment, each dummy scan line Dum G includes a second portion Dum Gy close to the display area AA and a first portion Dum Gx far away from the display area AA, and the second portion Dum Gy is connected to the corresponding dummy shift register Dum ASG through the first portion Dum Gx. The second portion Dum Gy is disposed to be insulated and overlapped with at least a portion of the first data signal lead Dx1, and the width of the second portion Dum Gy in the column direction D1 is greater than the width of the first portion Dum Gx in the column direction.
By increasing the width of the portion of the dummy scan line Dum G overlapping the data signal lead Dx, the overlapping area between the dummy scan line Dum G and the data signal lead Dx can be increased, and the coupling capacitance between the dummy scan line Dum G and the data signal lead Dx is increased, so that the load of the dummy scan line Dum G is correspondingly increased. Because the dummy scanning line Dum G is connected with the dummy shift register, the load of the dummy scanning line Dum G is increased, which is equivalent to the increase of the load of the dummy shift register, so that the load of the dummy shift register is consistent with the load of the conventional shift register, the charging state of the data line to the pixels in the display area can be further ensured to be consistent, and the display effect is improved.
Fig. 6 is another routing manner of the dummy scan line according to the embodiment of the present invention, in this embodiment, the dummy scan line Dum G includes a second portion Dum Gy close to the display area AA and a first portion Dum Gx far away from the display area AA, and the second portion Dum Gy is electrically connected to the corresponding dummy shift register through the first portion Dum Gx. Wherein the second portion Dum Gy is disposed to be insulated and overlapped with at least a portion of the first data signal lead Dx1, wherein the second portion Dum Gy includes a plurality of branches extending in the row direction D2, and one end of all the branches is electrically connected to one end of the first portion Dum Gx away from the dummy shift register. Therefore, the length of the dummy scan line Dum G and the overlapping area between the dummy scan line Dum G and the data signal lead Dx can be increased, and the resistance of the dummy scan line Dum G and the coupling capacitance between the dummy scan line Dum G and the data signal lead Dx are increased, which is equivalent to increasing the load of the dummy shift register, so that the load of the dummy shift register is matched with the load of the conventional shift register.
Alternatively, the gate driving circuit 10 may include at least two shift register groups, each shift register group includes a plurality of shift registers electrically connected to each other, and the array substrate includes at least two dummy scan lines electrically connected to the at least two shift register groups, respectively. The at least two dummy scan lines are all located in the irregular non-display area BB1 of the array substrate 01. For example, when the gate driving circuit is a multiphase shift register, all the dummy scan lines connected to a plurality of required dummy shift registers are located in the irregular non-display area BB1, which can greatly reduce the area of the non-display area and is beneficial to narrow the frame compared with a conventional non-display area where all the dummy scan lines penetrate through the upper and lower ends of the array substrate.
Alternatively, as shown in fig. 7, two shift register groups (a first shift register group 101 and a second shift register group 102) of the gate driving circuit 10 are located on the left and right sides of the display area AA in the row direction D2, and the number of shift registers in the two shift register groups (the first shift register group 101 and the second shift register group 102) is equal, which may be: the gate driving circuit 10 is located at the left and right sides of the display area AA in the row direction D2, and each side includes a plurality of shift register sets. Optionally, the shift register groups on the same side are connected to the same dummy shift register Dum ASG, the shift register groups on different sides are connected to different dummy shift registers Dum ASGs, and the dummy scan lines connected to the two different dummy shift registers Dum ASGs are respectively located in the irregular non-display areas BB1 on both sides of the array substrate. The dummy scanning lines can be completely wired in the special-shaped non-display area without extending to the conventional non-display areas at the upper end and the lower end of the array substrate under the condition that the dummy shift register is ensured to have enough load, so that the area of the non-display areas at the upper end and the lower end of the array substrate can be reduced, and the narrow-frame design is favorably realized.
Secondly, the invention further provides a display panel comprising the array substrate provided by any one of the embodiments. The display panel may be a liquid crystal display panel, an OLED or electrophoretic display panel, or the like. Taking the liquid crystal display panel as an example, when the display panel is a liquid crystal display panel, the display panel further includes a color film substrate arranged opposite to the array substrate, and a liquid crystal layer sealed between the array substrate and the color film substrate, and the array substrate and the color film substrate are sealed into a box by a frame sealing adhesive arranged in the peripheral non-display area.
In addition, an embodiment of the present invention further provides a display device, including any one of the display panels provided in the above embodiments. Referring to fig. 8, fig. 8 is a schematic diagram of a display device according to an embodiment of the present invention, and the display device 100 includes any one of the display panels according to the embodiment of the present invention. The display device 100 provided by the embodiment of the invention can be any electronic product with a display function, including but not limited to the following categories: the mobile terminal comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a mobile phone, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like.
By the embodiment, the display panel and the display device provided by the embodiment of the invention have the following beneficial effects: the array substrate comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises a special-shaped non-display area and is positioned between a special-shaped boundary of the display area and a special-shaped edge of the array substrate; the dummy scanning lines of the array substrate are positioned in the special-shaped non-display area, so that the occupied space of the dummy scanning lines in the non-display area can be reduced, the area of the non-display area of the array substrate is reduced, and the narrow frame of the display device is facilitated.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (9)
1. An array substrate, comprising a display area and a non-display area surrounding the display area,
the display area comprises a first boundary extending along a column direction, a second boundary extending along a row direction and a special-shaped boundary connected between the first boundary and the second boundary, the array substrate comprises a first edge extending along the column direction, a second edge extending along the row direction and a special-shaped edge connected between the first edge and the second edge, and the non-display area comprises a special-shaped non-display area positioned between the special-shaped boundary and the special-shaped edge;
the array substrate further includes:
the scanning lines and the data lines are positioned in the display area, the scanning lines extend along the row direction and are arranged along the column direction, the data lines extend along the column direction and are arranged along the row direction, and the scanning lines and the data lines are arranged in a crossed and insulated mode;
a gate driving circuit located in the non-display region, the gate driving circuit including a plurality of shift registers including at least one dummy shift register, the shift registers except the dummy shift register being electrically connected to the scan lines and supplying scan signals to the scan lines;
at least one dummy scan line between the display area and the dummy shift register, one end of the dummy scan line being electrically connected to the dummy shift register;
the array substrate further comprises a plurality of data signal leads which are respectively and correspondingly electrically connected with the data lines one by one and provide data signals for the data lines;
the plurality of data signal leads comprise a plurality of first data signal leads, the plurality of first data signal leads penetrate through the special-shaped non-display area, and the dummy scanning lines are arranged in an insulating and overlapping mode with at least part of the first data signal leads.
2. The array substrate of claim 1, wherein the array substrate comprises a first metal layer and a second metal layer stacked in sequence, the dummy scan lines and the scan lines are formed on the first metal layer, and the data signal leads and the data lines are formed on the second metal layer.
3. The array substrate of claim 1, wherein the dummy scan line is located between the display area and the dummy shift register, the dummy scan line comprising a second portion proximate to the display area and a first portion distal from the display area, the second portion being electrically connected to the dummy shift register through the first portion;
the second portion is arranged to be insulated and overlapped with at least a part of the first data signal lead, and the width of the second portion in the column direction is larger than that of the first portion in the column direction.
4. The array substrate of claim 1, wherein the dummy scan line is located between the display area and the dummy shift register, the dummy scan line comprising a second portion proximate to the display area and a first portion distal from the display area, the second portion being electrically connected to the dummy shift register through the first portion;
the second part is arranged to be insulated and overlapped with at least part of the first data signal lead, and the second part is S-shaped.
5. The array substrate of claim 1, wherein the dummy scan line is located between the display area and the dummy shift register, the dummy scan line comprising a second portion proximate to the display area and a first portion distal from the display area, the second portion being electrically connected to the dummy shift register through the first portion;
the second part is arranged to be insulated and overlapped with at least one part of the first data signal lead, wherein the second part comprises a plurality of branches extending along the row direction, and one end of all the branches is electrically connected to one end of the first part far away from the dummy shift register.
6. The array substrate of claim 1, wherein the gate driving circuit comprises at least two shift register groups, each shift register group comprising a plurality of shift registers electrically connected to each other,
the array substrate comprises at least two dummy scanning lines which are respectively and electrically connected with the at least two shift register groups.
7. The array substrate of claim 6, wherein the array substrate comprises two irregular non-display areas respectively located at two sides of the display area in the row direction;
the at least two shift register groups are respectively positioned at the left side and the right side of the display area, and the at least two dummy scanning lines are respectively positioned in the two special-shaped non-display areas.
8. A display panel comprising the array substrate according to any one of claims 1 to 7.
9. A display device characterized by comprising the display panel according to claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810700405.4A CN108873521B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810700405.4A CN108873521B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108873521A CN108873521A (en) | 2018-11-23 |
| CN108873521B true CN108873521B (en) | 2021-06-18 |
Family
ID=64297386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810700405.4A Active CN108873521B (en) | 2018-06-29 | 2018-06-29 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108873521B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111192545B (en) * | 2019-02-27 | 2022-09-13 | 京东方科技集团股份有限公司 | Gate driving circuit, gate driving method, folding display panel and display device |
| EP4148489A4 (en) * | 2020-05-07 | 2023-05-17 | BOE Technology Group Co., Ltd. | Array substrate and display device |
| US11415854B2 (en) * | 2020-06-29 | 2022-08-16 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| CN113341600B (en) * | 2021-05-25 | 2022-05-06 | 厦门天马微电子有限公司 | Display panel and display device |
| EP4339935A1 (en) * | 2021-12-31 | 2024-03-20 | BOE Technology Group Co., Ltd. | Display panel and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489178A (en) * | 2015-12-31 | 2016-04-13 | 上海中航光电子有限公司 | Grid drive structure, display panel and display device |
| CN106448587A (en) * | 2016-10-08 | 2017-02-22 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array base palte, special-shaped display and display device |
| CN107610636A (en) * | 2017-10-30 | 2018-01-19 | 武汉天马微电子有限公司 | A kind of display panel and display device |
| CN107611142A (en) * | 2017-09-11 | 2018-01-19 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7643003B2 (en) * | 2005-06-30 | 2010-01-05 | Lg Display Co., Ltd. | Liquid crystal display device having a shift register |
-
2018
- 2018-06-29 CN CN201810700405.4A patent/CN108873521B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105489178A (en) * | 2015-12-31 | 2016-04-13 | 上海中航光电子有限公司 | Grid drive structure, display panel and display device |
| CN106448587A (en) * | 2016-10-08 | 2017-02-22 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN107221536A (en) * | 2017-05-25 | 2017-09-29 | 上海天马微电子有限公司 | Array base palte, special-shaped display and display device |
| CN106991990A (en) * | 2017-05-27 | 2017-07-28 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107611142A (en) * | 2017-09-11 | 2018-01-19 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
| CN107610636A (en) * | 2017-10-30 | 2018-01-19 | 武汉天马微电子有限公司 | A kind of display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108873521A (en) | 2018-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108873521B (en) | Array substrate, display panel and display device | |
| US10559604B2 (en) | Array substrate, gate driving circuit and display panel | |
| CN107992229B (en) | Touch display panel and touch display device | |
| CN108182921B (en) | Array substrate, display panel and display device | |
| CN107633812B (en) | Display panel and display device | |
| JP6847501B2 (en) | Display with auxiliary load structure | |
| US9886115B2 (en) | Touch display substrate | |
| CN107611142B (en) | Display panel and display device | |
| US20170123506A1 (en) | Flexible array substrate, display panel having the same, keyboard assembly, and electronic device thereof | |
| CN111624827B (en) | Array substrate, display panel and display device | |
| US11687193B2 (en) | Display substrate and display device | |
| CN107863374A (en) | A kind of OLED display panel and display device | |
| US10902809B2 (en) | Scan driver circuit, array substrate and display panel | |
| CN107121853B (en) | Liquid crystal display panel and liquid crystal display device | |
| CN110599898A (en) | Grid driving array type display panel | |
| US20210327903A1 (en) | Array substrate, method of fabricating array substrate, display device, and method of fabricating display device | |
| US20200349876A1 (en) | Array substrate and display device | |
| CN107300794B (en) | Liquid crystal display panel driving circuit and liquid crystal display panel | |
| CN115497410A (en) | Display panel and display device | |
| CN109061972B (en) | Display panel | |
| CN111948859A (en) | Display substrate and display device | |
| JP4163611B2 (en) | Liquid crystal display | |
| CN113571021A (en) | Display panel and display device | |
| CN113495638A (en) | Touch display screen and display device | |
| US20220350189A1 (en) | Display module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |