KR20130117215A - Gate shift register and display device using the same - Google Patents

Abstract

PURPOSE: A gate shift register and a display device using the same are provided to reduce a leakage current flowed into a Q node by setting a forward voltage or a reverse voltage to have a voltage of pulse type in which a gate high voltage and a gate low voltage are repeated. CONSTITUTION: A number of stages output a scan pulse sequentially in a forward shift mode, and outputs the scan pulse reverse-sequentially in a reverse shift mode. A scan direction control unit (12) controls scan direction by outputting a forward voltage or a reverse voltage in response to a carry signal of a prior stage and a carry signal of a next stage. A node control unit (4) controls the voltage of a first node through a third node according to an output voltage of the scan direction control unit. An output unit (16) outputs the scan pulse according to the voltage state of the first node through the third node. [Reference numerals] (14,AA,CC,EE,GG) Node control unit; (16,BB,DD,FF,HH) Node control unit

Description

Gate shift register and display device using the same {GATE SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a gate shift register and a display device using the same, which can prevent malfunctions and increase operation reliability.

Recently, a gate shift register capable of bidirectional shift operation has been proposed. The plurality of stages provided in the bidirectional gate shift register output scan pulses in the direction of the first stage to the last stage in the forward shift mode, and output scan pulses in the direction of the first stage from the last stage in the reverse shift mode.

Each of the plurality of stages includes a pull-up thin film transistor (hereinafter referred to as TFT) TU for outputting a clock signal CLK as a scan pulse VOUT according to the voltage state of the Q node Q, as shown in FIG. A first TFT T1 for supplying the forward voltage VDD_F to the Q node Q in response to the forward gate start pulse GSP_F or the carry signal provided from the previous stage, and the reverse gate start pulse GSP_R or the next stage. And a second TFT T2 for supplying the reverse voltage VDD_R to the Q node Q in response to the carry signal provided from the stage. Here, the forward voltage VDD_F and the reverse voltage VDD_R are voltages that vary depending on whether the mode is in the forward shift mode or the reverse shift mode, and has a fixed value during the shift mode period. That is, the forward voltage VDD_F is set to the gate high voltage VGH in the forward shift mode and to the gate low voltage VGL in the reverse shift mode. The reverse voltage VDD_R is set to the gate low voltage VGL in the forward shift mode and to the gate high voltage VGH in the reverse shift mode.

However, the bidirectional gate shift register as described above has the following problems. The first and second TFTs T1 and T2 are turned off for most of the period except for a period in which the Q node Q is precharged in one frame period, so that gate bias stress is accumulated. do. The first and second TFTs T1 and T2 in which the gate bias stress is accumulated form a leakage current path between the source and drain electrodes. That is, the first TFT T1 forms a leakage current path as the voltage difference between the source and drain electrodes becomes about 25V in the forward shift mode, and the voltage difference between the source and drain electrodes when the second TFT T2 is in the reverse shift mode. As it is about 25V, it forms a leakage current path. The leakage current path between the source and drain electrodes in the first and second TFTs T1 and T2 affects the voltage level of the Q node Q, resulting in malfunction of the bidirectional shift register, and consequently deteriorating operation reliability. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a gate shift register and a display device using the same, which can prevent malfunctions and increase operation reliability.

In order to achieve the above object, the gate shift register according to the first embodiment of the present invention sequentially outputs a scan pulse in a forward shift mode, and a plurality of stages outputting the scan pulse in reverse order in a reverse shift mode. It includes; The plurality of stages may include: a scan direction controller configured to control a scan direction by outputting a forward voltage or a reverse voltage in response to a carry signal of a previous stage and a carry signal of a next stage; A node controller configured to control voltages of the first to third nodes according to the output voltage of the scan direction controller; An output unit configured to output the scan pulse in accordance with the voltage states of the first to third nodes; The forward voltage and the reverse voltage are phase inverted with each other and are in a pulsed voltage in which a gate high voltage and a gate low voltage are repeated; In the plurality of stages, the forward voltage and the reverse voltage are alternately applied.

The forward voltage and the reverse voltage are characterized in that the gate high voltage and the gate low voltage is repeated every one horizontal period.

The scan direction controller may include: a first switching element configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the previous stage; And a second switching device configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the next stage.

The node controller may further include: a third switching element configured to discharge the voltage of the first node to a base voltage according to the voltage state of the second node; A fourth switching element for supplying the first alternating voltage to the second node in accordance with the voltage state of the first alternating voltage; A fifth switching element for discharging the voltage of the second node to the base voltage according to the voltage state of the first node; A sixth switching element for discharging the second AC voltage to the base voltage according to the voltage state of the second AC voltage; A seventh switching element configured to discharge the voltage of the first node to the base voltage according to the voltage state of the third node; An eighth switching element for supplying the second alternating voltage to the third node in accordance with the voltage state of the second alternating voltage; A ninth switching element configured to discharge the voltage of the third node to the base voltage according to the voltage state of the first node; And a tenth switching device configured to discharge the voltage of the third node to the base voltage according to the first AC voltage state.

The output unit and a pull-up switching element for supplying the clock pulse input to the output terminal in accordance with the voltage state of the first node; A first pull-down switching element for discharging the voltage at the output terminal to a base voltage according to the voltage state of the second node; And a second pull-down switching element for discharging the voltage at the output terminal to the base voltage according to the voltage state of the third node.

In addition, in order to achieve the above object, the gate shift register according to the second embodiment of the present invention includes a plurality of stages, the first gate shift register for supplying a scan pulse to the odd-numbered gate line, and even A second gate shift register for supplying the scan pulse to a first gate line; The plurality of stages may include: a scan direction controller configured to control a scan direction by outputting a forward voltage or a reverse voltage in response to a carry signal of a previous stage and a carry signal of a next stage; A node controller configured to control voltages of the first to third nodes according to the output voltage of the scan direction controller; An output unit configured to output the scan pulse in accordance with the voltage states of the first to third nodes; The forward voltage and the reverse voltage are phase inverted with each other and are in a pulsed voltage in which a gate high voltage and a gate low voltage are repeated; In the plurality of stages, the forward voltage and the reverse voltage are alternately applied.

The forward voltage includes a first forward voltage for driving the first gate shift register and a second forward voltage for driving the second gate shift register; The reverse voltage may include a first reverse voltage for driving the first gate shift register and a second reverse voltage for driving the second gate shift register.

The first and second forward voltages, the first and second reverse voltages, the forward voltage and the reverse voltage are characterized in that the gate high voltage and the gate low voltage is repeated every two horizontal periods.

The scan direction controller may include: a first switching element configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the previous stage; And a second switching device configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the next stage.

The node controller may further include: a third switching element configured to discharge the voltage of the first node to a base voltage according to the voltage state of the second node; A fourth switching element for supplying the first alternating voltage to the second node in accordance with the voltage state of the first alternating voltage; A fifth switching element for discharging the voltage of the second node to the base voltage according to the voltage state of the first node; A sixth switching element for discharging the second AC voltage to the base voltage according to the voltage state of the second AC voltage; A seventh switching element configured to discharge the voltage of the first node to the base voltage according to the voltage state of the third node; An eighth switching element for supplying the second alternating voltage to the third node in accordance with the voltage state of the second alternating voltage; A ninth switching element configured to discharge the voltage of the third node to the base voltage according to the voltage state of the first node; And a tenth switching device configured to discharge the voltage of the third node to the base voltage according to the first AC voltage state.

The output unit and a pull-up switching element for supplying the clock pulse input to the output terminal in accordance with the voltage state of the first node; A first pull-down switching element for discharging the voltage at the output terminal to a base voltage according to the voltage state of the second node; And a second pull-down switching element for discharging the voltage at the output terminal to the base voltage according to the voltage state of the third node.

In the bidirectional gate shift register, the forward voltage or the reverse voltage is set to have a voltage in the form of a pulse in which the gate high voltage and the gate low voltage are repeated, thereby reducing leakage current flowing into the Q node and improving operation reliability.

1 is a schematic circuit diagram of a stage provided in a conventional bidirectional gate shift register.
2 is a block diagram of a display device according to a first embodiment of the present invention.
3 is a block diagram of the gate shift register 10 according to the first embodiment of the present invention.
FIG. 4 is a configuration circuit diagram of the first stage ST1 shown in FIG. 3.
FIG. 5 is a configuration circuit diagram of the second stage ST2 shown in FIG. 3.
FIG. 6 is a waveform diagram illustrating an operation in the forward shift mode of the gate shift register 10 shown in FIG. 3.
FIG. 7 is a waveform diagram illustrating an operation in the reverse shift mode of the gate shift register 10 shown in FIG. 3.
8 is a configuration diagram of a display device according to a second exemplary embodiment of the present invention.
9 is a configuration diagram of the first gate shift register 20 according to the second embodiment.
10 is a configuration diagram of the second gate shift register 30 according to the second embodiment.
FIG. 11 is a waveform diagram illustrating an operation in a forward shift mode of the first and second gate shift registers 20 and 30 illustrated in FIGS. 9 and 10.
FIG. 12 is a waveform diagram illustrating an operation in the reverse shift mode of the first and second gate shift registers 20 and 30 illustrated in FIGS. 9 and 10.

Hereinafter, a gate shift register and a display device using the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

2 is a block diagram of a display device according to a first embodiment of the present invention.

The display device shown in FIG. 2 includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8.

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL that cross each other, and a plurality of pixels P are provided in the crossing regions of the GL and DL. The plurality of pixels P display an image using the scan pulse VOUT supplied from the gate line GL and the data voltage supplied from the data line DL.

The gate driver 4 includes a gate shift register 10 for supplying scan pulses VOUT to the plurality of gate lines GL according to the plurality of gate control signals GCS provided from the timing controller 8. The gate shift register 10 of the present invention can perform a bidirectional shift operation and can increase reliability by being designed to prevent a malfunction. The gate shift register 10 will be described later in detail.

The data driver 6 converts the digital image data RGB input from the timing controller 8 into a data voltage using a reference gamma voltage according to a plurality of data control signals DCS provided from the timing controller 8. The converted data voltage is supplied to the plurality of data lines DL.

The timing controller 8 arranges the image data RGB, which is input from the outside, to the data driver 6 in alignment with the size and resolution of the display panel 2. The timing controller 8 uses a plurality of synchronization signals input from the outside, for example, using a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and the like. Gate and data control signals GCS and DCS are generated and supplied to the gate driver 4 and the data driver 6, respectively. Here, the plurality of gate control signals GCS includes a plurality of clock pulses CLK, forward gate start pulses and reverse gate start pulses GSP_F, GSP_R, etc., which indicate driving start of the gate driver 4. The plurality of data control signals DCS includes a source output enable for controlling the output period of the data driver 6, a source start pulse for instructing the start of data sampling, and a sampling of data. And a source shift clock for controlling timing.

Hereinafter, the gate shift register 10 of the present invention will be described in detail.

3 is a block diagram of the gate shift register 10 according to the first embodiment of the present invention. 4 is a configuration circuit diagram of the first stage ST1 illustrated in FIG. 3, and FIG. 5 is a configuration circuit diagram of the second stage ST2 illustrated in FIG. 3.

The gate shift register 10 shown in FIG. 3 sequentially outputs the scan pulse VOUT in the forward shift mode, and outputs the scan pulse VOUT in the reverse order in the reverse shift mode, where n is a positive integer. Stages ST1 to STn. In particular, the first embodiment sets the forward voltage VDD_F and the reverse voltage VDD_R to pulse-type voltages, and alternates the forward voltage VDD_F and the reverse voltage VDD_R to the plurality of stages ST1 to STn. By supplying the current to the Q node Q, leakage current flowing into the Q node Q is reduced, and driving reliability is increased.

The plurality of stages ST1 to STn are provided with a clock pulse CLK, first and second alternating voltages VDD_O and VDD_E, and a base voltage VSS. The plurality of stages ST1 to STn are provided with any one voltage selected from the forward voltage VDD_F and the reverse voltage VDD_R. For reference, the first and second AC voltages VDD_O and VDD_E are voltages 180 degrees out of phase with each other with a specific period. In addition, the clock pulse CLK is a clock signal of two or more phases repeated in a phase delayed form by one horizontal period (1H) period. In addition, the forward voltage VDD_F and the reverse voltage VDD_R have a specific period, and the gate high voltage VGH and the gate low voltage VGL are repeated, and they are pulse voltages 180 degrees out of phase with each other. In addition, the forward voltage VDD_F and the reverse voltage VDD_R are 180 degrees phase inverted when the shift mode is switched.

Hereinafter, each stage ST will be described in detail with reference to FIGS. 3 to 5.

The plurality of stages ST1 to STn control the scan direction by outputting a forward voltage VDD_F or a reverse voltage VDD_R in response to a carry signal of a previous stage and a carry signal of a next stage. And a node control unit 14 for controlling the voltages of the Q node Q or the QB nodes QB_odd and QB_even according to the output voltage of the scan direction control unit 12, and the Q node Q and the QB nodes QB_odd and QB_even. And an output unit 16 for outputting a scan pulse VOUT according to the voltage state.

The scan direction controller 12 determines the scan direction in response to the carry signal of the previous stage and the carry signal of the next stage. For this purpose, the scan direction controller 12 includes first and second TFTs T1 and T1.

The first TFT T1 supplies the forward voltage VDD_F or the reverse voltage VDD_R to the Q node Q in response to the carry signal of the previous stage.

The second TFT T2 supplies the forward voltage VDD_F or the reverse voltage VDD_R to the Q node Q in response to the carry signal of the next stage.

However, the first TFT T1 provided in the first stage ST1 operates in response to the forward gate start pulse GSP_F instead of the carry signal of the previous stage. The second TFT T2 provided in the nth stage STn operates in response to the reverse gate start pulse GSP_R instead of the carry signal of the next stage.

In particular, the scan direction controllers 12 provided in each stage ST are alternately provided with the forward voltage VDD_F and the reverse voltage VDD_R. For example, as illustrated in FIG. 4, the first and second TFTs T1 and T2 provided in the odd-numbered stages ST2n−1 receive the forward voltage VDD_F. As shown in FIG. 5, the first and second TFTs T1 and T2 provided in the even-numbered stage ST2n receive the reverse voltage VDD_R. The first embodiment can reduce the leakage charge flowing into the Q node Q due to the leakage current path of the scan direction controller 12 in the remaining periods except for some periods in which each stage ST is precharged. The shaking of the node Q can be reduced and the operation reliability can be improved.

The node control unit 14 controls the voltages of the Q node Q and the QB nodes QB_odd and QB_even in response to the output voltage of the scan direction control unit 12. To this end, the node controller 14 includes third to tenth TFTs T3 to T10.

The third TFT T3 discharges the voltage of the Q node Q to the ground voltage VSS according to the voltage state of the first QB node QB_odd.

The fourth TFT T4 supplies the first AC voltage VDD_O to the first QB node QB_odd according to the voltage state of the first AC voltage VDD_O provided from the first AC voltage supply line.

The fifth TFT T5 discharges the voltage of the first QB node QB_odd to the base voltage VSS according to the voltage state of the Q node Q.

The sixth TFT T6 discharges the voltage of the first QB node QB_odd to the base voltage VSS in accordance with the voltage state of the second AC voltage VDD_E provided from the second AC voltage supply line.

The seventh TFT T7 discharges the voltage of the Q node Q to the base voltage VSS in accordance with the voltage state of the second QB node QB_even.

The eighth TFT T8 supplies the second AC voltage VDD_E to the second QB node QB_even in accordance with the voltage state of the second AC voltage VDD_E provided from the second AC voltage supply line.

The ninth TFT T9 discharges the voltage of the second QB node QB_even to the base voltage VSS in accordance with the voltage state of the Q node Q.

The tenth TFT T10 discharges the voltage of the second QB node QB_even to the base voltage VSS in accordance with the voltage state of the first AC voltage VDD_O provided from the first AC voltage supply line.

The output unit 16 supplies the input clock pulse CLK to the output terminal in accordance with the voltage state of the Q node Q and the QB nodes QB_odd and QB_even by the node control unit 14, and also supplies the voltage of the output terminal to the output terminal. Discharge to voltage VSS. For this purpose, the output unit 16 includes pull-up TFTs (TU) and first and second pull-down TFTs (TD1, TD2).

The pull-up TFT TU supplies an input clock pulse to an output terminal according to the voltage state of the Q node Q.

The first pull-down TFT TD1 discharges the voltage at the output terminal to the base voltage VSS in accordance with the voltage state of the first QB node QB_odd.

The second pull-down TFT TD2 discharges the voltage at the output terminal to the base voltage VSS in accordance with the voltage state of the second QB node QB_even.

FIG. 6 is a waveform diagram illustrating an operation in the forward shift mode of the gate shift register 10 shown in FIG. 3.

Referring to FIG. 6 and FIGS. 3 to 5, the operation in the forward shift mode will be described below.

The clock pulse CLK includes a cyclic clock delayed by one horizontal period 1H from the first clock pulse CLK1 to the fourth clock pulse CLK4. Each of the forward voltage VDD_F and the reverse voltage VDD_R is a pulse type voltage in which the gate high voltage VGH and the gate low voltage VGL are repeated by one horizontal period 1H. The forward voltage VDD_F and the reverse voltage VDD_R are inverted in phase with each other. The first AC voltage VDD_O is in a gate high voltage VGH state in an odd frame period and in a gate low voltage VGL state in an even frame period. The second AC voltage VDD_E is in a gate low voltage VGL state in an odd frame period and in a gate high voltage VGH state in an even frame period.

First, when the first period Z1 is described, a forward gate start pulse GSP_F is generated in an odd frame in the forward shift mode, which turns on the first TFT T1 of the first stage ST1. -Turn it on. The turned-on first TFT T1 supplies the Q node Q1 with the forward voltage VDD_F in the gate high voltage VGH state. Accordingly, the Q node Q1 provided in the first stage ST1 is precharged to the gate high voltage VGH. The fifth and ninth TFTs T5 and T9 are turned on due to the voltage state of the precharged Q node Q1, and the first and second QB nodes QB_odd and QB_even are connected to the base voltage VSS. Discharged.

Referring to the second period Z2, the first clock pulse CLK1 having the gate high voltage VGH is input to the drain electrode of the pull-up TFT TU provided in the first stage ST1. Then, the Q node Q1 is bootstrapped by the parasitic capacitance between the gate and drain electrodes of the pull-up TFT TU to turn on the pull-up TFT TU while rising to a voltage level higher than the gate high voltage VGH. Accordingly, the first stage ST1 outputs the first scan pulse VOUT1 having the gate high voltage VGH state. At this time, the first scan pulse VOUT1 of the first stage ST1 turns on the first TFT T1 of the second stage ST2 as a carry signal. In the second stage ST2, the Q node Q2 is precharged to the gate high voltage VGH similarly to the first stage ST1 of the first period Z1 described above.

Referring to the third period Z3, the second clock pulse CLK2 in the gate high voltage VGH state is input to the drain electrode of the pull-up TFT TU provided in the second stage ST2. Then, the Q node Q2 is bootstrapped by the parasitic capacitance between the gate and drain electrodes of the pull-up TFT TU, thereby raising the voltage level higher than the gate high voltage VGH to turn on the pull-up TFT TU. Accordingly, the second stage ST2 outputs the second scan pulse VOUT2 in the gate high voltage VGH state. At this time, the second scan pulse VOUT2 of the second stage ST2 turns on the first TFT T1 of the third stage ST3 as a carry signal. In the third stage ST3, the Q node Q3 is precharged to the gate high voltage VGH similarly to the first stage ST1 of the first period Z1 described above.

Meanwhile, in the third period Z3, the second scan pulse VOUT2 of the second stage ST2 turns on the second TFT T2 of the first stage ST1 as a carry signal. The turned-on second TFT T2 supplies the Q node Q1 with the forward voltage VDD_F having the gate high voltage VGH and the gate high voltage VGH. Although the pull-up TFT TU is turned on because the Q node Q1 is in the gate-high voltage VGH state, the first stage ST1 has the gate-low voltage VGL at the drain electrode of the pull-up TFT TU. As the first clock pulse CLK1 is input, the output terminal of the first stage ST1 is discharged to the gate low voltage VGL, that is, the base voltage VSS. That is, in the third period Z3, the first stage ST1 outputs the first scan pulse VOUT1 in the state of the base voltage VSS.

Referring to the fourth period Z4, the second stage ST1 operates in the same manner as the first stage ST1 of the third period Z3 described above to perform the second scan pulse VOUT2 in the ground voltage VSS state. Outputs Accordingly, the second and fifth TFTs T2 and T5 provided in the first stage ST1 are turned off. Then, the first QB node QB_odd of the first stage ST1 is supplied with the first AC voltage VDD_O having the gate high voltage VGH state through the turned-on fourth TFT T4. The first QB node QB_odd of the first stage ST1 in the gate high voltage VGH state turns on the third TFT T3 and the first pull-down TFT TD1. The turned-on third TFT T3 discharges the Q node Q1 to the base voltage VSS, and the turned-on first pull-down TFT TD1 uses the output terminal voltage of the first stage ST1 as the base voltage VSS. Keep).

The operation of the odd frame in the forward shift mode is as described above, and each of the first to nth stages ST1 to STn has the first to fourth periods Z1 to Z4 in sequence to scan pulses. VOUT) is output sequentially.

On the other hand, in the forward shift mode, the operation of the even frame is performed by the seventh TFT (T7) instead of the third TFT (T3), the eighth TFT (T8) instead of the fourth TFT (T4), A ninth TFT (T9) operates in place of the fifth TFT (T5), a tenth TFT (T10) operates in place of the sixth TFT (T6), and a second pull-down TFT (TD2) operates in place of the first pull-down TFT (TD1). The only difference is that the operation is the same as for an odd frame.

FIG. 7 is a waveform diagram illustrating an operation in the reverse shift mode of the gate shift register 10 shown in FIG. 3.

Referring to FIG. 7 and FIGS. 3 to 5, the operation in the reverse shift mode will be described below.

The clock pulse CLK includes a cyclic clock delayed by one horizontal period 1H from the first clock pulse CLK1 to the fourth clock pulse CLK4. Each of the forward voltage VDD_F and the reverse voltage VDD_R is a pulse type voltage in which the gate high voltage VGH and the gate low voltage VGL are repeated by one horizontal period 1H. The forward voltage VDD_F and the reverse voltage VDD_R are inverted in phase with each other. On the other hand, the forward voltage VDD_F and the reverse voltage VDD_R in the reverse shift mode are phase inverted with the forward voltage VDD_F and the reverse voltage VDD_R in the forward shift mode. The first AC voltage VDD_O is in a gate high voltage VGH state in an odd frame period and in a gate low voltage VGL state in an even frame period. The second AC voltage VDD_E is in a gate low voltage VGL state in an odd frame period and in a gate high voltage VGH state in an even frame period.

First, when the first period Z1 is described, the reverse gate start pulse GSP_R is generated in the odd frame in the reverse shift mode, which turns on the first TFT T1 of the nth stage STn. -Turn it on. The turned-on first TFT T1 supplies the Q node Qn with the forward voltage VDD_F in a gate high voltage VGH state. Accordingly, the Q node Qn provided in the nth stage STn is precharged to the gate high voltage VGH. The fifth and ninth TFTs T5 and T9 are turned on due to the voltage state of the precharged Q node Qn, and the first and second QB nodes QB_odd and QB_even are connected to the base voltage VSS. Discharged.

Referring to the second period Z2, the fourth clock pulse CLK4 of the gate high voltage VGH state is input to the drain electrode of the pull-up TFT TU provided in the n-th stage STn. Then, the Q node Qn is bootstrapped by the parasitic capacitance between the gate and drain electrodes of the pull-up TFT TU, and thus is turned on at a voltage level higher than the gate high voltage VGH, thereby turning on the pull-up TFT TU. Accordingly, the nth stage STn outputs the nth scan pulse VOUTn having the gate high voltage VGH state. At this time, the n th scan pulse VOUTn of the n th stage STn turns on the first TFT T1 of the n th -th stage STn-1 as a carry signal. In the n-th stage STn-1, the Q node Q2 is precharged to the gate high voltage VGH similarly to the n-th stage STn of the first period Z1 described above.

Referring to the third period Z3, the third clock pulse CLK3 having the gate high voltage VGH is input to the drain electrode of the pull-up TFT TU provided in the n-1 stage STn-1. . Then, the Q node Qn-1 is bootstrapped by the parasitic capacitance between the gate and drain electrodes of the pull-up TFT TU, thereby rising to a voltage level higher than the gate high voltage VGH, thereby turning on the pull-up TFT TU. Let's do it. Accordingly, the n-th stage STn-1 outputs the n-th scan pulse VOUTn-1 having the gate high voltage VGH state. At this time, the n-th scan pulse VOUTn-1 of the n-th stage STn-1 turns on the first TFT T1 of the n-th stage STn-2 as a carry signal. . In the n-th stage STn-2, the Q node Qn-2 is precharged to the gate high voltage VGH similarly to the n-th stage STn of the first period Z1 described above.

On the other hand, in the third period Z3, the n-th scan pulse VOUTn-1 of the n-th stage STn-1 turns the second TFT T2 of the n-th stage STn as a carry signal. -Turn it on. The turned-on second TFT T2 supplies the Q node Qn with the forward voltage VDD_F having the gate high voltage VGH and the gate high voltage VGH. Although the pull-up TFT TU is turned on because the Q node Qn is in the gate-high voltage VGH state, the nth stage STn is the gate-low voltage VGL at the drain electrode of the pull-up TFT TU. As the fourth clock pulse CLK4 is input, the output terminal of the nth stage STn is discharged to the gate low voltage VGL, that is, the base voltage VSS. That is, in the third period Z3, the nth stage STn outputs the nth scan pulse VOUTn in the ground voltage VSS state.

Referring to the fourth period Z4, the n-th stage STn-1 operates in the same manner as the n-th stage STn of the third period Z3 described above, whereby the n-th stage of the ground voltage VSS state is maintained. Output one scan pulse (VOUTn-1). Accordingly, the second and fifth TFTs T2 and T5 provided in the nth stage STn are turned off. Then, the first QB node QB_odd of the nth stage STn is supplied with the first AC voltage VDD_O having the gate high voltage VGH state through the turned-on fourth TFT T4. The first QB node QB_odd of the nth stage STn in the gate high voltage VGH state turns on the third TFT T3 and the first pull-down TFT TD1. The turned-on third TFT T3 discharges the Q node Q1 to the base voltage VSS, and the turned-on first pull-down TFT TD1 uses the output terminal voltage of the nth stage STn as the base voltage VSS. Keep).

The operation of the odd frame in the reverse shift mode is as described above, and each of the nth stage STn to the first stage ST1 scans with the first to fourth periods Z1 to Z4 sequentially. The pulse VOUT is output in reverse order.

On the other hand, in the reverse shift mode, the operation of the even frame is performed by the seventh TFT (T7) instead of the third TFT (T3), the eighth TFT (T8) instead of the fourth TFT (T4), A ninth TFT (T9) operates in place of the fifth TFT (T5), a tenth TFT (T10) operates in place of the sixth TFT (T6), and a second pull-down TFT (TD2) operates in place of the first pull-down TFT (TD1). The only difference is that the operation is the same as for an odd frame.

As described above, in the gate shift register 10 according to the first embodiment of the present invention, the first to nth stages ST1 to STn have the first to fourth periods Z1 to Z4, and the scan pulse VOUT. ) In particular, the first embodiment needs to pay attention to the fourth period Z4 in which the Q node Q is maintained at the gate low voltage VGH after the first to third periods Z1 to Z3. That is, in the conventional gate shift register, either the forward voltage VDD_F or the reverse voltage VDD_R connected to the drain electrodes of the first and second TFTs T1 and T2 during the fourth period Z4 is the gate high voltage. By continuously maintaining the (VGH) state, leakage current is generated due to the gate bias stresses of the first and second TFTs T1 and T2, and there is a problem of shaking the Q node Q. However, in the first exemplary embodiment, the forward voltage VDD_F or the reverse voltage VDD_R connected to the drain electrodes of the first and second TFTs T1 and T2 may have a gate high voltage VGH and a gate low voltage VGL. By having a voltage in the form of a repeating pulse, it is possible to reduce the leakage current and improve the operation reliability.

≪ Embodiment 2 >

Unlike the first embodiment, the second embodiment includes two gate drivers 4 and 5. In the description of the second embodiment, the rest of the configuration except for the gate drivers 4 and 5 is the same as in the first embodiment, and the description thereof is replaced with the description in the first embodiment.

8 is a configuration diagram of a display device according to a second exemplary embodiment of the present invention. 9 is a configuration diagram of the first gate shift register 20 according to the second embodiment. 10 is a configuration diagram of the second gate shift register 30 according to the second embodiment.

The display device illustrated in FIG. 8 includes a display panel 2, first and second gate drivers 4 and 5, a data driver 6, and a timing controller 8.

The first gate driver 4 supplies a first gate shift register 20 that supplies a scan pulse VOUT to an odd-numbered gate line GL according to a plurality of gate control signals GCS provided from the timing controller 8. Include. The second gate driver 5 supplies a scan pulse VOUT to the even-numbered gate line GL according to the plurality of gate control signals GCS provided from the timing controller 8. It includes.

As shown in FIG. 9, the first gate shift register 20 sequentially outputs the scan pulse VOUT in the forward shift mode, and outputs the scan pulse VOUT in the reverse order in the reverse shift mode. (n is a positive integer) and includes stages ST1 to STn / 2. Similarly, as shown in FIG. 10, the second gate shift register 30 sequentially outputs the scan pulse VOUT in the forward shift mode, and outputs the scan pulse VOUT in the reverse order in the reverse shift mode. / 2 (n is a positive integer) includes stages ST1 to STn / 2. The stages ST provided in the first and second shift registers 20 and 30 operate with the same configuration as the stages ST in the first embodiment.

Unlike the first embodiment, the second embodiment sets two forward voltages, two reverse voltages, two forward gate start pulses, and two reverse gate start pulses. Although their number increased to two, the role is the same as in the first embodiment. That is, the first gate start pulse GSP1, the first forward voltage VDD_F1, and the first reverse voltage VDD_R1 are provided to the first gate shift register 20 to provide the first gate shift register 20. Operate. The second gate start pulse GSP2, the second forward voltage VDD_F2, and the second reverse voltage VDD_R2 are provided to the second gate shift register 30 to operate the second gate shift register 30. Let's do it. This will be described in detail as follows.

9, the stages ST1 to STn / 2 of the first gate shift register 20 may include first and second alternating voltages VDD_O and VDD_E, a base voltage VSS, and a first forward voltage. Any one selected from VDD_F1 or the first reverse voltage VDD_R1 is provided. In addition, the first stage ST1 included in the first gate shift register 20 receives a first forward gate start pulse GSP_F1 instead of the carry signal of the previous stage. The last stage STn / 2 of the second gate shift 2 register 20 receives the first reverse gate start pulse GSP_R1 instead of the carry signal of the next stage. Here, the stages ST1 to STn / 2 of the first gate shift register 20 are alternately provided with the first forward voltage VDD_F1 and the first reverse voltage VDD_R1, thereby providing respective stages ST1 to STn /. It reduces the leakage charge flowing into the Q node provided in 2), and improves the driving reliability.

Referring to FIG. 10, the stages ST1 to STn / 2 of the second gate shift register 30 may include first and second AC voltages VDD_O and VDD_E, a base voltage VSS, and a second forward voltage. Any one selected from VDD_F2 or the second reverse voltage VDD_R2 is provided. In addition, the first stage ST1 included in the second gate shift register 30 receives a second forward gate start pulse GSP_F2 instead of the carry signal of the previous stage. The last stage STn / 2 of the second gate shift 2 register 30 receives the second reverse gate start pulse GSP_R2 instead of the carry signal of the next stage. Here, the stages ST1 to STn / 2 of the second gate shift register 30 are alternately provided with the second forward voltage VDD_F2 and the second reverse voltage VDD_R2, thereby providing respective stages ST1 to STn /. It reduces the leakage charge flowing into the Q node provided in 2), and improves the driving reliability.

FIG. 11 is a waveform diagram illustrating an operation in a forward shift mode of the first and second gate shift registers 20 and 30 illustrated in FIGS. 9 and 10.

Referring to FIG. 11, the operation in the forward shift mode will be described below.

The first and second forward voltages VDD_F1 and VDD_F2 and the first and second reverse voltages VDD_R1 and VDD_R2 each have a high voltage VGH and a gate low voltage VGL repeated for two horizontal periods 2H. Voltage in pulse form. In addition, the second forward voltage VDD_F2 and the second reverse voltage VDD_R2 are delayed by one horizontal period from the first forward voltage VDD_F1 and the first reverse voltage VDD_R1.

First, when the first forward gate start pulse GSP_F1 is generated, the first gate shift register 20 sequentially scans the scan pulse VOUT from the first stage ST1 to the n / 2th stage STn / 2. And generate and supply the odd-numbered gate lines GL2n-1.

Subsequently, when the second forward gate start pulse GSP_F2 is generated, the second gate shift register 30 sequentially scans the scan pulse VOUT from the first stage ST1 to the n / 2th stage STn / 2. It generates and supplies to even-numbered gate lines GL2n. In this case, the second forward gate start pulse GSP_F2 has a phase delayed by one horizontal period (1H) than the first forward gate start pulse GSP_F1.

In this case, the stages provided in the first and second gate shift registers 20 and 30 generate the scan pulse VOUT sequentially with the first to fourth periods Z1 to Z4 as in the first embodiment. . As a result, the first and second gate shift registers 20 and 30 sequentially supply scan pulses VOUT to the n gate lines GL.

FIG. 12 is a waveform diagram illustrating an operation in the reverse shift mode of the first and second gate shift registers 20 and 30 illustrated in FIGS. 9 and 10.

Referring to FIG. 12, the operation in the reverse shift mode will be described below.

The first and second forward voltages VDD_F1 and VDD_F2 and the first and second reverse voltages VDD_R1 and VDD_R2 each have a high voltage VGH and a gate low voltage VGL repeated for two horizontal periods 2H. Voltage in pulse form. In addition, the first forward voltage VDD_F1 and the first reverse voltage VDD_R1 are delayed by one horizontal period from the second forward voltage VDD_F2 and the second reverse voltage VDD_R2.

First, when the second reverse gate start pulse GSP_R2 is generated, the second gate shift register 30 reversely scans the scan pulse VOUT from the n / 2 stage STn / 2 to the first stage ST1. Is generated and supplied to the even-numbered gate lines GL2n.

Subsequently, when the first reverse gate start pulse GSP_R1 is generated, the first gate shift register 20 performs a scan pulse VOUT in reverse order from the n / 2 stage STn / 2 to the first stage ST1. Is generated and supplied to odd-numbered gate lines GL2n-1. In this case, the first reverse gate start pulse GSP_R1 has a phase delayed by one horizontal period (1H) than the second forward gate start pulse GSP_R2.

In this case, the stages provided in the first and second gate shift registers 20 and 30 generate the scan pulse VOUT sequentially with the first to fourth periods Z1 to Z4 as in the first embodiment. . As a result, the first and second gate shift registers 20 and 30 supply the scan pulse VOUT in reverse order to the n gate lines GL.

As described above, in the bidirectional gate shift register, the forward voltage VDD_F or the reverse voltage VDD_R is set to have a voltage in the form of a pulse in which the gate high voltage VGH and the gate low voltage VGL are repeated. This reduces leakage current into the Q node and improves operating reliability.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

12: scan control unit 14: node control unit
16: Output section

Claims (12)

A plurality of stages for sequentially outputting scan pulses in a forward shift mode and outputting the scan pulses in reverse order in a reverse shift mode;
The plurality of stages may include: a scan direction controller configured to control a scan direction by outputting a forward voltage or a reverse voltage in response to a carry signal of a previous stage and a carry signal of a next stage; A node controller configured to control voltages of the first to third nodes according to the output voltage of the scan direction controller; An output unit configured to output the scan pulse in accordance with the voltage states of the first to third nodes;
The forward voltage and the reverse voltage are phase inverted with each other and are in a pulsed voltage in which a gate high voltage and a gate low voltage are repeated;
And the plurality of stages are alternately applied with the forward voltage and the reverse voltage. The method of claim 1,
And the gate high voltage and the gate low voltage are repeated every one horizontal period. The method of claim 1,
The scan direction control unit
A first switching element configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the previous stage;
And a second switching device configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the next stage. The method of claim 1,
The node controller
A third switching element for discharging the voltage of the first node to a base voltage according to the voltage state of the second node;
A fourth switching element for supplying the first alternating voltage to the second node in accordance with the voltage state of the first alternating voltage;
A fifth switching element for discharging the voltage of the second node to the base voltage according to the voltage state of the first node;
A sixth switching element for discharging the second AC voltage to the base voltage according to the voltage state of the second AC voltage;
A seventh switching element configured to discharge the voltage of the first node to the base voltage according to the voltage state of the third node;
An eighth switching element for supplying the second alternating voltage to the third node in accordance with the voltage state of the second alternating voltage;
A ninth switching element configured to discharge the voltage of the third node to the base voltage according to the voltage state of the first node;
And a tenth switching element discharging the voltage of the third node to the base voltage according to the first alternating voltage state. The method of claim 1,
The output
A pull-up switching element configured to supply a clock pulse input to an output terminal according to the voltage state of the first node;
A first pull-down switching element for discharging the voltage at the output terminal to a base voltage according to the voltage state of the second node;
And a second pull-down switching element for discharging the voltage at the output terminal to the base voltage according to the voltage state of the third node. A plurality of stages, comprising: a first gate shift register for supplying scan pulses to odd-numbered gate lines, and a second gate shift register for supplying said scan pulses to even-numbered gate lines;
The plurality of stages may include: a scan direction controller configured to control a scan direction by outputting a forward voltage or a reverse voltage in response to a carry signal of a previous stage and a carry signal of a next stage; A node controller configured to control voltages of the first to third nodes according to the output voltage of the scan direction controller; An output unit configured to output the scan pulse in accordance with the voltage states of the first to third nodes;
The forward voltage and the reverse voltage are phase inverted with each other and are in a pulsed voltage in which a gate high voltage and a gate low voltage are repeated;
And the plurality of stages are alternately applied with the forward voltage and the reverse voltage. The method according to claim 6,
The forward voltage includes a first forward voltage for driving the first gate shift register and a second forward voltage for driving the second gate shift register;
And the reverse voltage includes a first reverse voltage for driving the first gate shift register and a second reverse voltage for driving the second gate shift register. The method of claim 7, wherein
And the gate high voltage and the gate low voltage are repeated for each of the first and second forward voltages, the first and second reverse voltages, the forward voltage and the reverse voltage every two horizontal periods. The method according to claim 6,
The scan direction control unit
A first switching element configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the previous stage;
And a second switching device configured to supply the forward voltage or the reverse voltage to the first node in response to a carry signal of the next stage. The method according to claim 6,
The node controller
A third switching element for discharging the voltage of the first node to a base voltage according to the voltage state of the second node;
A fourth switching element for supplying the first alternating voltage to the second node in accordance with the voltage state of the first alternating voltage;
A fifth switching element for discharging the voltage of the second node to the base voltage according to the voltage state of the first node;
A sixth switching element for discharging the second AC voltage to the base voltage according to the voltage state of the second AC voltage;
A seventh switching element configured to discharge the voltage of the first node to the base voltage according to the voltage state of the third node;
An eighth switching element for supplying the second alternating voltage to the third node in accordance with the voltage state of the second alternating voltage;
A ninth switching element configured to discharge the voltage of the third node to the base voltage according to the voltage state of the first node;
And a tenth switching element discharging the voltage of the third node to the base voltage according to the first alternating voltage state. The method according to claim 6,
The output
A pull-up switching element configured to supply a clock pulse input to an output terminal according to the voltage state of the first node;
A first pull-down switching element for discharging the voltage at the output terminal to a base voltage according to the voltage state of the second node;
And a second pull-down switching element for discharging the voltage at the output terminal to the base voltage according to the voltage state of the third node. A display device comprising the gate shift register according to any one of claims 1 to 11.

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