KR20090113738A - Shift register - Google Patents

Abstract

PURPOSE: A shift register is provided to control an output order of a scan pulse of stages according to a forward voltage and a reverse voltage by a node controller, so changing an output order of the stages. CONSTITUTION: In a shift register, a plurality of stages successively output an output signal after receiving clock pulses. Each stage includes a node controller, a pull-up switching element, a first noise elimination unit, and a second noise elimination unit. The node controller(NC) controls a signal of a set node and controls an output order of a scan pulse of stages according to a forward voltage and a reverse voltage of which phases are inverse each other. A pull-up switching element(Trpu) is turned on/off according to a signal of a set node, and outputs one of clock pulses to the scan pulse through an output terminal when it is turned on. A first noise elimination unit(TrE1) is turned on/off according to one of clock pulses and output the scan pulse to the set node from a start pulse and previous state.

Description

Shift register {SHIFT REGISTER}

The present invention relates to a shift register, and more particularly to a shift register that can change the output order of the stages.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. Here, the gate driver includes a shift register to sequentially output the scan pulses as described above.

The conventional shift register includes a plurality of stages which in turn output a scan pulse. The stages output scan pulses in one direction, i.e., from the topmost stage to the bottommost stage. That is, the conventional shift register outputs scan pulses in only one direction. Accordingly, the conventional shift registers exhibit many problems to be used in liquid crystal display devices of various models.

The present invention has been made to solve the above problems, and an object thereof is to provide a shift register that can control the output order of scan pulses.

The shift register according to the present invention for achieving the above object, at least two clock transmission lines for transmitting at least two clock pulses having a different phase difference, and receiving the clock pulses from each clock transmission line sequentially It includes a plurality of stages for outputting the output signal, each stage controls the signal state of the set node, and the output order of the scan pulse of the stages according to the forward voltage and the reverse voltage having a phase inverted with each other A node controller; A pull-up switching element which is turned on / off according to the signal state of the set node, and outputs any one of the clock pulses as a scan pulse through an output terminal at turn-on, and a turn-on / turn according to any one clock pulse. A first noise canceling unit which is turned off and supplies a start pulse from outside or a scan pulse from a front end stage to the set node at turn-on; And a second noise canceling unit which is turned on / off according to any one of the clock pulses, and supplies a start pulse from the outside or an output signal from a next stage to the set node when the clock pulse is turned on. .

The shift register according to the present invention has the following effects.

In the present invention, the shift register may change the output order of stages through the scan direction controller. Accordingly, the shift register according to the present invention can be applied to display devices of various models.

1 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, FIG. 2 is a timing diagram of various signals supplied to the shift register of FIG. 1 in forward driving, and FIG. 3 is a timing diagram of the shift register of FIG. 1 in reverse driving. It is a timing chart of the various signals supplied.

The shift register according to the embodiment of the present invention includes n stages and two dummy stages ST0 and STn + 1 as shown in FIG. 1. Here, each stage ST1 to STn outputs one scan pulse for one frame period.

Each stage ST1 to STn drives the gate line connected to itself by using the scan pulse, and controls the operation of the stage located at the rear end from the stage and the stage located at the front end from the stage.

The entire stages ST0 to STn + 1 including the upper dummy stage ST0 and the lower dummy stage STn + 1 sequentially output scan pulses Vout0 to Voutn + 1.

At this time, the entire stages ST0 to STn + 1 are driven in the forward direction or in the reverse direction according to the signal states of the forward voltage V_F and the reverse voltage V_R.

First, in the forward driving, the stages ST0 to STn + 1 output scan pulses in order from the upper dummy stage ST0 to the lower dummy stage STn + 1.

That is, the upper dummy stage ST0 outputs the first dummy scan pulse Vout0, and then the first stage ST1 outputs the first scan pulse Vout1, and then the second stage ST2 outputs the first dummy scan pulse Vout0. The third scan pulse Vout3 is output, the third stage ST3 outputs the fifth scan pulse Vout5, and the nth stage STn is the nth scan pulse Voutn), and finally, the lower dummy stage STn + 1 outputs the second dummy scan pulse Voutn + 1.

In the reverse driving, the stages ST0 to STn + 1 output scan pulses in order from the lower dummy stage STn + 1 to the upper dummy stage ST0.

That is, the lower dummy stage STn + 1 outputs the second dummy scan pulse Voutn + 1, and the nth stage STn sequentially outputs the nth scan pulse Voutn, and then n−−. The first stage STn-1 outputs the n-1th scan pulse Voutn-1, and the n-2th stage then outputs the n-2th scan pulse, ..., the first stage ST1 Outputs the first scan pulse Vout1, and finally, the upper dummy stage ST0 outputs the first dummy scan pulse Vout0.

Scan pulses Vout1 to Vout2n output from the stages ST1 to STn except for the upper and lower dummy stages ST0 and STn + 1 are sequentially supplied to gate lines of a liquid crystal panel (not shown). The gate lines are sequentially scanned.

Such a shift register may be embedded in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

As illustrated in FIGS. 2 and 3, the stages ST1 to STn included in the shift register configured as described above are among the first to sixth clock pulses CLK1 to CLK6 having a sequential phase difference with each other. Four clock pulses, a forward voltage V_F, a reverse voltage V_R, and a low potential voltage VSS are supplied.

The upper and lower dummy stages ST0 and STn + 1 may include four clock pulses among the first to sixth clock pulses CLK1 to CLK4, a start pulse Vst, and a forward voltage V_F. The reverse voltage V_R and the low potential voltage VSS are supplied.

The first to sixth clock pulses CLK1 to CLK6 are output with phase differences from each other. The second clock pulse CLK2 is output after being phase-delayed than the first clock pulse CLK1, and the third clock pulse CLK3 is output by being phase-delayed than the second clock pulse CLK2. The fourth clock pulse CLK4 is output after being phase-delayed than the third clock pulse CLK3, and the fifth clock pulse CLK5 is output by being phase-delayed than the fourth clock pulse CLK4, and the sixth clock is output. The pulse CLK6 is delayed in phase than the fifth clock pulse CLK5 and output.

The first to sixth clock pulses CLK1 to CLK6 are sequentially output, and are also output while cycling. That is, after the first clock pulse CLK1 to the sixth clock pulse CLK6 are sequentially output, the first clock pulse CLK1 to the sixth clock pulse CLK6 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the sixth clock pulse CLK6 and the second clock pulse CLK2.

Each of the clock pulses CLK1 to CLK6 is output several times during one frame period, but the start pulse Vst is output only once during one frame period. In other words, each clock pulse CLK1 to CLK6 exhibits several active states (high states) periodically during one frame period, while the start pulse Vst represents only one active state during one frame period. This start pulse Vst is output earlier than any of the clock pulses CLK1 to CLK6 in one frame period.

In the present invention, an example of using six types of clock pulses having different phase differences is shown. However, any number of clock pulses can be used as long as four or more.

In the forward driving, as shown in FIG. 2, the clock pulses CLK1 to CLK6 are output in order from the first clock pulse CLK1 to the sixth clock pulse CLK6. On the other hand, in reverse driving, as shown in FIG. 3, the clock pulses CLK1 to CLK6 are output in order from the sixth clock pulse CLK6 to the first clock pulse CLK1.

In the present invention, as shown in FIGS. 2 and 3, the first to sixth clock pulses CLK1 to CLK6 in which the pulse width sections are overlapped may be used. In other words, the clock pulses output in the adjacent period among the clock pulses CLK1 to CLK6 supplied to each stage are simultaneously active for a certain period of time.

That is, as shown in FIG. 2, the first half of the pulse width section of the i th clock pulse (i is a natural number of 2 or more) overlaps with the second half of the pulse width section of the i-1 clock pulse. The second half half of the pulse width of the i th clock pulse overlaps the first half half of the pulse width of the i + 1 th clock pulse.

In other words, as shown in FIG. 3, the first half of the pulse width of the i th clock pulse overlaps the second half of the pulse width of the i + 1 th clock pulse. The second half half of the pulse width of the i clock pulse is overlapped with the second half half of the pulse width of the i + 1 clock pulse.

For example, as shown in FIGS. 2 and 3, if the first to sixth clock pulses CLK1 to CLK6 each have a pulse width section corresponding to two horizontal periods (2H), adjacent ones may be adjacent. The clock pulses overlap each other by an interval corresponding to one horizontal period.

The length of the section of the pulse width to be filled is not limited to the length corresponding to the 1/2 section and can be adjusted to any number.

When the overlapped clock pulses CLK1 to CLK6 are used, as shown in FIGS. 2 and 3, pulses of the scan pulses Vout0 to Voutn + 1 output from the stages ST0 to STn + 1 are used. The widths also overlap each other.

The upper and lower dummy stages ST0 and STn + 1 and the stages ST1 to STn shown in FIG. 1 operate by receiving various signals having the above-described characteristics.

In order for each stage ST1 to STn to output a scan pulse, an enable operation of each stage ST1 to STn must be preceded. The stage being enabled means that the stage is set to a state capable of outputting, that is, a state capable of outputting a clock pulse supplied thereto as a scan pulse.

In the forward driving, each stage ST1 to STn is enabled by receiving scan pulses from the stage located in front of it. For example, the j th stage is enabled in response to the scan pulse from the j-2 stage.

However, in the forward driving, the uppermost first and second stages ST1 and ST2 are enabled in response to the first dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage ST0 is enabled by receiving the start pulse Vst from the start transmission line.

On the other hand, during the reverse driving, each stage ST1 to STn is enabled by receiving scan pulses from the stage located next to it. For example, the j th stage is enabled in response to the scan pulse from the j + 2 stage.

However, in the reverse driving, the nth and n-1th stages STn and STn-1 located at the lowermost positions are in response to the second dummy scan pulse Vout2n + 1 from the lower dummy stage STn + 1. Is enabled. The lower dummy stage STn + 1 is enabled by receiving the start pulse Vst from the start transmission line.

On the other hand, each stage (ST1 to STn) is disabled after the scan pulse output, which means that the stage is disabled, the stage can not output, that is, the clock pulse supplied to itself can not output as a scan pulse Means reset to state.

In the forward driving, each stage ST1 to STn is disabled by receiving scan pulses from the stage located at the rear end thereof. For example, the j th stage is disabled in response to the scan pulse from the j + 2 stage.

However, in the forward driving, the nth stage STn and the n-1th stage STn-1 located at the bottom side respond to the second dummy scan pulse Voutn + 1 from the lower dummy stage STn + 1. Are disabled. The lower dummy stage STn + 1 is disabled by receiving the start pulse Vst from the start transmission line.

On the other hand, in the reverse driving, each stage ST1 to STn is disabled by receiving scan pulses from the stage located at the front end thereof. For example, the j th stage is disabled in response to the scan pulse from the j-2 stage.

However, in the reverse driving, the uppermost first and second stages ST1 and ST2 are disabled in response to the first dummy scan pulse Vout0 from the upper dummy stage ST0. The upper dummy stage STn0 is disabled by receiving the start pulse Vst from the start transmission line.

Here, the configuration of each stage in more detail as follows.

4 is a diagram illustrating a circuit configuration of an arbitrary stage of FIG. 1.

The kth stage ST0 to STn + 1 includes a set node Q; In addition to controlling the signal state of the set node Q, scan pulses Vout0 to Voutn of the stages ST0 to STn + 1 according to the forward voltage V_F and the reverse voltage V_R having inverted phases. A node controller NC for controlling the output order of +1); A pull-up switching device Trpu which is turned on / off according to the signal state of the set node Q and outputs any one of the clock pulses CLK1 to CLK6 as a scan pulse through an output terminal at turn-on time; ; The first noise removing unit TrE1 which is turned on / off according to any one of the clock pulses and supplies the start node Vst from the outside or the scan pulse from the previous stage to the set node Q at turn-on. Wow; And a second noise canceling unit which is turned on / off according to any one of the clock pulses, and supplies a start pulse Vst from the outside or an output signal from a next stage to the set node Q at turn-on. (TrE2).

The first noise removing unit TrE1 provided in the k-th stage is turned on / off according to any one of the clock pulses, and is scanned from the external start pulse Vst or the k-th stage at turn-on. Supply a pulse to the set node (Q); The second noise removing unit TrE2 provided in the k-th stage is turned on / off according to any one of the clock pulses, and is turned on by the start pulse Vst from the outside or the scan pulse from the k + 1th stage. Is supplied to the set node Q.

The node controller NC of the k-th stage includes first and second switching devices Tr1 and Tr2.

The first switching device Tr1 is turned on / off according to the scan pulse from the k-2 stage, and supplies the forward voltage V_F to the set node Q at turn-on.

The second switching device Tr2 is turned on / off according to the scan pulse from the k + 2th stage, and supplies the reverse voltage V_R to the set node Q at turn-on.

In addition, the k-th stage further includes a pull-down switching device Trpd that is turned on / off according to any one of the clock pulses and outputs a low potential voltage VSS through the output terminal 111 at turn-on. .

The pull-up switching device Trpu of the 6k + 1 stage is supplied with the first clock pulse CLK1; The pull-up switching device Trpu of the 6k + 2 stage is supplied with the second clock pulse CLK2; The pull-up switching device Trpu of the 6k + 3 stage is supplied with the third clock pulse CLK3; The pull-up switching device Trpu of the 6k + 4 stage is supplied with the fourth clock pulse CLK4; The pull-up switching device Trpu of the 6k + 5 stage is supplied with the fifth clock pulse CLK5; The pull-up switching device Trpu of the 6k + 6 stage is supplied with the sixth clock pulse CLK6.

The first noise canceller TrE1 of the 6k + 1 stage is supplied with the sixth clock pulse CLK6; The first noise canceller TrE1 of the 6k + 2 stage is supplied with the first clock pulse CLK1; The first noise canceller TrE1 of the 6k + 3 stage is supplied with the second clock pulse CLK2; The first noise canceller TrE1 of the 6k + 4 stage is supplied with the third clock pulse CLK3; The first noise canceller TrE1 of the 6k + 5 stage is supplied with the fourth clock pulse CLK4; The first noise remover TrE1 of the 6k + 6 stage is supplied with the fifth clock pulse CLK5.

The second noise removing part TrE2 of the 6k + 1 stage is supplied with the second clock pulse CLK2; The second noise canceller TrE2 of the 6k + 2 stage is supplied with the third clock pulse CLK3; The second noise canceller TrE2 of the 6k + 3 stage is supplied with the fourth clock pulse CLK4; The second noise canceller TrE2 of the 6k + 4th stage is supplied with the fifth clock pulse CLK5; The second noise canceller TrE2 of the 6k + 5 stage is supplied with the sixth clock pulse CLK6; The second noise removing unit TrE2 of the 6k + 6 stage receives the first clock pulse CLK1.

The pull-down switching device Trpd of the 6k + 1 stage is supplied with the fourth clock pulse CLK4; The pull-down switching device Trpd of the 6k + 2 stage is supplied with the fifth clock pulse CLK5; The pull-down switching device Trpd of the 6k + 3 stage is supplied with the sixth clock pulse CLK6; The pull-down switching device Trpd of the 6k + 4 stage is supplied with the first clock pulse CLK1; The pull-down switching device Trpd of the 6k + 5 stage is supplied with the second clock pulse CLK2; The pull-down switching device Trpd of the 6k + 6 stage is supplied with the third clock pulse CLK3.

The pull-up switching device Trpu of the upper dummy stage ST0 receives the sixth clock pulse CLK6; The first noise canceller TrE1 of the upper dummy stage ST0 receives the fifth clock pulse CLK5; The second noise removing part TrE2 of the upper dummy stage ST0 receives the first clock pulse CLK1; The pull-down switching device Trpd of the upper dummy stage ST0 receives the third clock pulse CLK3.

The pull-up switching device Trpu of the lower dummy stage STn + 1 receives the first clock pulse CLK1; The first noise canceller TrE1 of the lower dummy stage STn + 1 receives the sixth clock pulse CLK6; The second noise removing part TrE2 of the lower dummy stage STn + 1 receives the second clock pulse CLK2; The pull-down switching device Trpd of the lower dummy stage STn + 1 receives the fourth clock pulse CLK4.

The operation of the shift register configured as described above will be described in detail as follows.

An operation of the shift register according to the forward driving will be described with reference to FIGS. 1, 2, and 4.

As shown in FIG. 2, the clock pulses CLK1 to CLK6 are output in order from the first clock pulse CLK1 to the sixth clock pulse CLK6, and the forward voltage V_F is high. The reverse voltage V_R is low.

During the first initial period Ts, as shown in FIG. 2, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is supplied to the upper dummy stage ST0 and the lower dummy stage STn + 1.

That is, as shown in FIG. 4, the start pulse Vst includes the gate terminal of the first switching element Tr1 provided in the upper dummy stage ST0, and the drain of the first noise removing unit TrE1. Supplied to the terminal. Accordingly, both the first switching device Tr1 and the first noise removing unit TrE1 are turned on, and the forward voltage V_F of the high state is set through the turned-on first switching device Tr1. Supplied to node Q. In addition, a start pulse Vst of a high state is supplied to the set node Q through the turned-on first noise removing unit TrE1. Then, the set node Q is charged, and the pull-up switching device Trpu connected to the charged set node Q through the gate terminal is turned on.

In this way, the set node Q of the upper dummy stage ST0 is charged in the first initial period Ts, so that the dummy stage ST0 is set.

On the other hand, the lower dummy stage STn + 1 that is supplied with the start pulse Vst in the first initial period Ts is reset. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the second switching element Tr2 of the lower dummy stage STn + 1 and the drain terminal of the second noise removing unit TrE2. Accordingly, the second switching device Tr2 is turned on, and the reverse voltage V_R in a low state is supplied to the set node Q through the turned-on second switching device Tr2 to provide the set node Q. (Q) is discharged. The pull-up switching device Trpu connected to the discharged set node Q through the gate terminal is turned off. As described above, the lower dummy stage STn + 1 is reset in the first initial period Ts.

Thereafter, the sixth clock pulse CLK6 is supplied to the drain terminal of the pull-up switching device Trpu provided in the upper dummy stage ST0 in the second initial period T0. At this time, since the set node Q of the upper dummy stage ST0 is maintained in the floating state in the second initial period T0, the sixth clock pulse CLK6 supplied to the pull-up switching device Trpu is maintained. As a result, the voltage held at the set node Q is bootstrapped. The pull-up switching device Trpu outputs the sixth clock pulse CLK6 as a first dummy scan pulse Vout0.

The first dummy scan pulse Vout0 is supplied to the first and second stages ST1 and ST2 to set the first and second stages ST1 and ST2.

That is, the first dummy scan pulse Vout0 output from the upper dummy stage ST0 may be formed by the gate terminal of the first switching element Tr1 and the first noise removing unit TrE1 of the first stage ST1. It is supplied to the drain terminal. In addition, the sixth clock pulse CLK6 is supplied to the gate terminal of the first noise removing unit TrE1 provided in the first stage ST1. Accordingly, the first switching device Tr1 and the first noise removing unit TrE1 of the first stage ST1 are turned on. The high voltage forward voltage V_F is supplied to the set node Q of the first stage ST1 through the turned-on first switching device Tr1 and the turned-on first noise removing unit The first dummy scan pulse Vout0 in a high state is supplied to the set node Q of the first stage ST1 through TrE1. Accordingly, the set node Q of the first stage ST1 is charged, and the pull-up switching device Trpu connected to the charged set node Q through the gate terminal is turned on.

In this manner, the first stage ST1 is set in the second initial period T0.

Meanwhile, in the second initial period T0, the second stage ST2 is also set together with the first stage ST1 in response to the first dummy scan pulse Vout0. That is, although not shown in the drawing, the first dummy scan pulse Vout0 is supplied to the gate terminal of the first switching element Tr1 provided in the second stage ST2. Accordingly, the set node N of the second stage ST2 is charged to set the second stage ST2.

Next, the operation during the first period T1 will be described.

In this first period T1, as shown in Fig. 2, only the sixth and first clock pulses CLK6 and CLK1 are in a high state, and the remaining clock pulses including the start pulse Vst remain low. do.

By the sixth clock pulse CLK6, the first and second stages ST1 and ST2 repeat the above-described set operation once more.

In addition, as the first clock pulse CLK1 is supplied to the pull-up switching device Trpu of the first stage ST1 in the first period T1, the pull-up switching device Trpu is connected to the first clock pulse (Trpu). CLK1 is output as the first scan pulse Vout1 and is supplied to the first gate line and the third stage ST3. At this time, since the set node Q of the first stage ST1 is maintained in the floating state in the first period T1, the first clock pulse CLK1 is supplied to the pull-up switching device Trpu. The voltage held at the set node Q is bootstrapping.

Meanwhile, the first clock pulse CLK1 output in the first period T1 is also supplied to the second noise removing unit TrE2 of the upper dummy stage ST0, and accordingly, the second noise removing unit TrE2 is provided. Is turned on. The first scan pulse Vout1 having a high state is supplied to the set node Q of the upper dummy stage ST0 through the turned-on second noise removing unit TrE2.

Next, the operation during the second period T2 will be described.

In this second period T2, only the first and second clock pulses CLK1 and CLK2 are in a high state, and the remaining clock pulses including the start pulse Vst remain low.

The pull-up switching device Trpu provided in the first stage ST1 by the first clock pulse CLK1 outputs the first scan pulse Vout1 in a complete form. In this second period T2, the third stage ST3 is set by the first scan pulse Vout1.

In addition, the pull-up switching device Trpu provided in the second stage ST2 is started to output the second scan pulse Vout2 by the second clock pulse CLK2. That is, the pull-up switching device Trpu outputs the second clock pulse CLK2 as the second scan pulse Vout2, and this is the second gate line, the fourth stage ST4, and the upper dummy stage ST0. To feed. At this time, since the set node Q of the second stage ST2 is maintained in the floating state in the second period T2, the second clock pulse CLK2 is supplied to the pull-up switching device Trpu. The voltage held at the set node Q is bootstrapping.

On the other hand, the second clock pulse CLK2 output in the second period T2 is also supplied to the second noise removing unit TrE2 of the first stage ST1, and accordingly, the second noise removing unit TrE2 is provided. ) Is turned on. The high scan second scan pulse Vout2 is supplied to the set node Q of the first stage ST1 through the turned-on second noise removing unit TrE2.

Here, the second scan pulse Vout2 from the second stage ST2 resets the upper dummy stage ST0.

The reset operation of the upper dummy stage ST0 will now be described in detail.

That is, the second scan pulse Voutn2 is supplied to the gate terminal of the second switching device Tr2 provided in the upper dummy stage STn + 1. Accordingly, the second switching device Tr2 is turned on, and the reverse voltage V_R in the low state is supplied to the set node Q through the turned-on second switching device Tr2. Then, the set node Q is discharged, and the pull-up switching device Trpu of the upper dummy stage ST0 connected to the discharged set node Q through the gate terminal is turned off. That is, in the second period T2, the upper dummy stage STn0 is reset.

Next, the operation during the third period T3 will be described.

In the third period T3, only the second and third clock pulses CLK3 indicate a high state, and the remaining clock pulses including the start pulse Vst remain low.

The pull-up switching device Trpu provided in the second stage ST1 by the second clock pulse CLK2 outputs a complete second scan pulse Vout2 and supplies it to the second gate line. The pull-up switching device Trpu provided in the third stage ST3 is started to output the third scan pulse Vout3 by the third clock pulse CLK3.

In this third period T3, the third scan pulse Vout3 from the third stage ST3 is supplied to the third gate line to start driving the third gate line, and further, the fifth stage ST5. Supplied to the second stage ST5 and set to the fifth stage ST5, and supplied to the first stage ST1 to reset the first stage ST1.

Meanwhile, in the third period T3, the third scan pulse Vout3 from the third stage ST3 is supplied to the third gate line, the fifth stage ST5, and the first stage ST1. At this time, the first stage ST1 is reset by the third scan pulse Voutn3. In addition, the third clock pulse CLK3 is supplied to the gate terminal of the third switching device Tr3 provided in the upper dummy stage ST0 to turn on the third switching device Tr3. The low potential voltage VSS in the low state discharges the output terminal of the upper dummy stage ST0 through the turned-on third switching element Tr3.

Thereafter, in the fourth period T4, the fourth scan pulse Vout4 from the fourth stage ST4 is supplied to the fourth gate line, the sixth stage ST6, and the second stage ST2. In this case, the second stage ST2 is reset by the fourth scan pulse Voutn4.

Subsequently, in the fifth period T5, the fifth scan pulse Vout5 from the fifth stage ST5 is supplied to the fifth gate line, the seventh stage ST7, and the third stage ST3. At this time, the third stage ST3 is reset by the fifth scan pulse Voutn5. At this time, the fifth clock pulse CLK5 output in the fifth period is supplied to the gate terminal of the first noise removing unit TrE1 provided in the upper dummy stage ST0. Accordingly, the first noise removing unit TrE1 is turned on, and a start pulse having a low state is set through the turned-on first noise removing unit TrE1. Supplied to. Accordingly, the set node Q of the upper dummy stage ST0 is discharged. The first noise removing unit TrE1 periodically discharges the set node Q of the upper dummy stage ST0 whenever the fifth clock pulse CLK5 of the high state is supplied to its gate terminal. By preventing unwanted voltages from accumulating on the set node Q, the multi-output phenomenon can be prevented.

Here, a noise voltage is generated at the set node Q of the upper dummy stage ST0 by the sixth clock pulse CLK6. The moment the sixth clock pulse CLK6 is changed from the low state to the high state, 5 The clock noise CLK5 is already in a high state and the first noise removing unit TrE1 should be in an on state. To do this, it is necessary for each neighboring clock pulse to go high simultaneously for a period of time.

The first noise removing unit TrE1 provided with the remaining stages ST1 through STn and the lower dummy stage STn + 1 also performs the same operation as that provided with the upper dummy stage ST0 described above.

Next, the operation of the shift register according to the reverse driving will be described with reference to FIGS. 3 and 4.

As shown in FIG. 3, the clock pulses are output in the order of the sixth clock pulse CLK6 to the first clock pulse CLK1, and the forward voltage V_F is in the low state and the reverse voltage V_R. Is high.

During the first initial period Ts, as shown in FIG. 3, only the start pulse Vst output from the timing controller is kept high and the remaining clock pulses are kept low.

The start pulse Vst output from the timing controller is supplied to the upper dummy stage ST0 and the lower dummy stage STn + 1.

That is, as shown in FIG. 4, the start pulse Vst is the gate terminal of the second switching element Tr2 and the gate of the second noise removing unit TrE2 provided in the lower dummy stage STn + 1. Supplied to terminal and drain terminal. Accordingly, the second switching device Tr2 and the second noise removing unit TrE2 are turned on.

The high voltage reverse voltage V_R is supplied to the set node Q through the turned-on second switching element Tr2, and the high-state start is performed through the turned-on second noise canceller TrE2. A pulse is supplied to the set node Q. Then, the set node Q is charged, and the pull-up switching device Trpu of the lower dummy stage STn + 1 connected to the charged set node Q through the gate terminal is turned on.

Thus, the set node Q of the lower dummy stage STn + 1 is charged in the first initial period Ts. That is, the lower dummy stage STn + 1 is set in the first initial period Ts.

On the other hand, the upper dummy stage ST0 supplied with the start pulse Vst in this first initial period Ts is reset. If this is explained in more detail as follows.

That is, the start pulse Vst is supplied to the gate terminal of the first switching element Tr1 of the upper dummy stage ST0 and the drain terminal of the first noise removing unit TrE1. Accordingly, all of the first switching devices Tr1 are turned on, and the forward voltage V_F in a low state is supplied to the set node Q through the turned-on first switching devices Tr1 to supply the set node Q. Q is discharged, and the pull-up switching device Trpu connected to the discharged set node Q through the gate terminal is turned off, and thus, in the first initial period Ts, the upper dummy stage ST0) is reset.

Thereafter, in the second initial period T0, the first clock pulse CLK1 is supplied to the drain terminal of the pull-up switching device Trpu provided in the lower dummy stage STn + 1. In this case, since the set node Q of the lower dummy stage STn + 1 is maintained in the floating state in the second initial period T0, the first clock pulse CLK1 supplied to the pull-up switching device Trpu. ), The voltage held at the set node Q is bootstrapd. The pull-up switching device Trpu outputs the first clock pulse CLK1 as a second dummy scan pulse Voutn + 1.

The second dummy scan pulse Voutn + 1 is supplied to the n-th and n-th stages STn and STn-1 to set the n-th and n-th stages STn and STn-1.

That is, the second dummy scan pulse Voutn + 1 output from the lower dummy stage STn + 1 is the gate terminal and the second noise removing unit of the second switching element Tr2 provided in the nth stage STn. It is supplied to the drain terminal of (TrE2). In addition, the first clock pulse CLK1 is supplied to the gate terminal of the second noise removing unit TrE2 provided in the nth stage STn. Accordingly, the second switching device Tr2 and the second noise removing unit TrE2 of the nth stage STn are turned on. The high voltage reverse voltage V_R is supplied to the set node Q of the nth stage STn through the turned-on second switching element Tr2 and the turned-on second noise removing unit The second dummy scan pulse Voutn + 1 in the high state is supplied to the set node N of the nth stage STn through TrE2. Accordingly, the set node Q of the nth stage STn is charged, and the pull-up switching device Trpu connected to the charged set node Q through the gate terminal is turned on.

In this manner, the first stage ST1 is set in the second initial period T0.

On the other hand, in the second initial period T0, the n-th stage STn-1 is also set as the n-th stage STn in response to the second dummy scan pulse Voutn + 1. That is, although not shown in the drawing, the second dummy scan pulse Voutn + 1 is supplied to the gate terminal of the second switching element Tr2 provided in the n-th stage STn-1. Accordingly, the set node Q of the n-th stage STn-1 is charged to set the n-th stage STn-1.

Next, the operation during the first period T1 will be described.

In this first period T1, as shown in Fig. 3, only the sixth and first clock pulses CLK6 and CLK1 are in a high state, and the remaining clock pulses including the start pulse Vst remain low. do.

By the first clock pulse CLK1, the n-th and n-th stages STn and STn-1 repeat the above-described set operation once more.

In addition, as the sixth clock pulse CLK6 is supplied to the pull-up switching device Trpu of the nth stage STn in the first period T1, the pull-up switching device Trpu receives the sixth clock pulse. CLK6 is output as the nth scan pulse Voutn, and is supplied to the nth gate line and the n-2th stage STn-2. In this case, since the set node Q of the nth stage STn is maintained in the floating state in the first period T1, the sixth clock pulse CLK6 is supplied to the pull-up switching device Trpu. The voltage held at the set node Q is bootstrapping.

On the other hand, the sixth clock pulse CLK6 output in the first period T1 is also supplied to the first noise removing unit TrE1 of the lower dummy stage STn + 1. TrE1) is turned on. The n th scan pulse Voutn in a high state is supplied to the set node Q of the lower dummy stage STn + 1 through the turned-on first noise removing unit TrE1.

Next, the operation during the second period T2 will be described.

In the second period T2, only the sixth and fifth clock pulses CLK6 and CLK5 are in a high state, and the remaining clock pulses including the start pulse Vst remain low.

The pull-up switching device Trpu provided in the nth stage STn by the sixth clock pulse CLK6 outputs a complete nth scan pulse Voutn. In the second period T2, the n-th stage STn-2 is set by the n-th scan pulse Voutn.

In addition, the pull-up switching device Trpu provided in the n-th stage STn-1 starts outputting the n-th scan pulse Voutn-1 by the fifth clock pulse CLK5. That is, the pull-up switching device Trpu outputs the fifth clock pulse CLK5 as the n−1 th scan pulse Voutn−1, and the n−1 th gate line, the n−3 stage, and Supply to the lower dummy stage STn + 1. In this case, since the set node Q of the n-th stage STn-1 is maintained in the floating state in the second period T2, the second clock pulse supplied to the pull-up switching device Trpu ( The voltage held at the set node Q is bootstrapd by the CLK2.

On the other hand, the fifth clock pulse CLK5 output in the second period T2 is also supplied to the first noise removing unit TrE1 of the nth stage STn, and thus the first noise removing unit TrE1. Is turned on. The n-th scan pulse Voutn-1 having a high state is supplied to the set node Q of the n-th stage STn through the turned-on first noise removing unit TrE1.

 Here, the n-th scan pulse from the n-th stage STn-1 resets the lower dummy stage STn + 1.

The reset operation of the lower dummy stage STn + 1 will be described in detail as follows.

That is, the n-1 th scan pulse Voutn-1 is supplied to the gate terminal of the first switching device Tr1 provided in the lower dummy stage STn + 1. Accordingly, the first switching device Tr1 is turned on, and the forward voltage V_F in the low state is supplied to the set node Q through the turned-on first switching device Tr1. Then, the set node Q is discharged, and the pull-up switching device Trpu of the lower dummy stage STn + 1 connected to the discharged set node Q through the gate terminal is turned off. That is, the lower dummy stage STn + 1 is reset in the second period T2.

Next, the operation during the third period T3 will be described.

In the third period T3, only the fifth and fourth clock pulses CLK5 and CLK4 are in a high state, and the remaining clock pulses including the start pulse Vst remain in a low state.

The pull-up switching device Trpu provided in the n-th stage STn-1 by the fifth clock pulse CLK5 outputs the n-th scan pulse Voutn-1 of the full form to n-th- Supply to one gate line. The pull-up switching device Trpu provided in the n-th stage STn-2 begins to output the n-th scan pulse Voutn-2 by the fourth clock pulse CLK4.

In this third period T3, the n-th-2th scan pulse Voutn-2 from the nth-2th stage STn-2 is supplied to the nth-2th gate line to supply the nth-2th gate line. It starts to drive, is also supplied to the nth-4th stage to set the nth-4th stage, and is supplied to the nth stage STn to reset the nth stage STn.

Meanwhile, in the third period T3, the n-2 th scan pulse Voutn-2 from the n-2 th stage STn-2 receives the n-2 th gate line, the n-4 th stage, and the n th stage. It is supplied to (STn). At this time, the n-th stage STn is reset by the n-th scan pulse Voutnn-2. In addition, the fourth clock pulse CLK4 is supplied to the gate terminal of the third switching device Tr3 provided in the lower dummy stage STn + 1 to turn on the third switching device Tr3. The low potential voltage VSS in a low state discharges the output terminal 111 of the lower dummy stage STn + 1 through the turned-on third switching element Tr3.

Thereafter, in the fourth period T4, the n-3 scan pulses from the n-3 stage are supplied to the n-3 gate line, the n-5 stage, and the n-1 stage STn-1. . At this time, the n-th stage STn-1 is reset by the n-th scan pulse.

Subsequently, in the fifth period T5, the n-4th scan pulse from the n-4th stage is supplied to the n-4th gate line, the n-6th stage, and the n-2th stage. At this time, the n-th stage is reset by the n-th scan pulse. At this time, the second clock pulse CLK2 output in the fifth period T5 is supplied to the gate terminal of the second noise removing unit TrE2 provided in the lower dummy stage STn + 1. Accordingly, the second noise removing unit TrE2 is turned on, and a low start pulse Vst of the lower dummy stage STn + 1 is turned on through the turned-on second noise removing unit TrE2. It is supplied to the set node Q. Accordingly, the set node Q of the lower dummy stage STn + 1 is discharged. The second noise removing unit TrE2 periodically discharges the set node Q of the lower dummy stage STn + 1 whenever the second clock pulse CLK2 of the high state is supplied to its gate terminal. By preventing the unwanted voltage from accumulating at the set node Q, the multi-output phenomenon can be prevented.

The second noise removing unit TrE2 provided with the remaining stages ST1 to STn and the upper dummy stage ST0 also performs the same operation as that provided for the lower dummy stage STn + 1 described above.

As described above, in the forward driving, the first noise removing unit TrE1 of each of the stages ST0 to STn + 1 operates to periodically discharge the voltage of the set node Q, and in the reverse driving, the stages ST0 to STn. The second noise removing unit TrE2 of STn + 1 operates to periodically discharge the voltage of the set node Q to prevent the multi output phenomenon.

Here, a noise voltage is generated at the set node Q of the upper dummy stage ST0 by the sixth clock pulse CLK6. The moment the sixth clock pulse CLK6 is changed from the low state to the high state, 5 The clock noise CLK5 is already in a high state and the first noise removing unit TrE1 should be in an on state. To do this, it is necessary for each neighboring clock pulse to go high simultaneously for a period of time.

Meanwhile, each stage ST0 to STn + 1 may have a circuit configuration as follows.

FIG. 5 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration shown in FIG. 5 is almost the same as that of FIG. 4 and includes only the third switching element Tr3 instead of the pull-down switching element Trpd.

There is a difference in the connection relationship of the pull-down switching element Trpd.

The third switching device Tr3 is turned on / off according to the signal state of the output terminal, and connects the drain terminal and the source terminal of the pull-up switching device Trpd at turn-on.

FIG. 6 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration shown in Fig. 6 is almost the same as that of Fig. 4, and further includes only a third switching element. The description of this third switching device Tr3 is the same as that of FIG. 5.

FIG. 7 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration shown in FIG. 7 is almost the same as that of FIG. 4, and further includes only the third switching element Tr3.

The third switching device Tr3 is turned on / off according to the start pulse Vst, and supplies the low potential voltage VSS to the set node Q to discharge the set node Q at turn-on. .

In particular, the third switching device Tr3 is installed only in the remaining stages ST1 to STn except for the upper and lower dummy stages ST0 and STn + 1.

8 is a timing diagram of the first to sixth clock pulses CLK1 to CLK6 supplied to the shift register of the present invention, and FIG. 9 is an output of the k-th and k + 1 stages to receive the clock pulses of FIG. It is a diagram showing.

In FIG. 9, G1 is a graph showing the voltage of the set node Q of the k-th stage, G2 is a graph showing the scan pulse from the k-th stage, and G3 is a graph showing the scan pulse from the k + 1th stage. .

Meanwhile, the shift register described above may operate by receiving the first to eighth clock pulses instead of the first to sixth clock pulses CLK1 to CLK6.

In this case, the kth stage is set according to the scan pulse from the k-3rd stage and reset according to the scan pulse from the k + 3th stage. That is, the first switching device Tr1 provided in the k-th stage is supplied with the scan pulse from the k-3 stage, and the second switching device Tr2 provided in the k-th stage is supplied from the k + 3 stage. The scan pulse is supplied.

In addition, the upper dummy stage ST0 supplies the first dummy scan pulses Vout0 to the first to third stages ST1 to ST3 to set the first to third stages ST1 to ST3, and the lower dummy. The stage STn + 1 supplies the second dummy scan pulses Voutn + 1 to the nth-2nd to nth stages STn-2 to STn to supply the nth to nth stages STn-2 to nth. STn) is set.

At this time, the clock pulses supplied to each stage are as follows.

The pull-up switching device of the 8k + 1 stage is supplied with a first clock pulse;

The pull-up switching device of the 8k + 2 stage is supplied with the second clock pulse;

The pull-up switching device of the 8k + 3 stage is supplied with a third clock pulse;

The pull-up switching device of the 8k + 4 stage is supplied with a fourth clock pulse;

The pull-up switching element of the 8k + 5 stage is supplied with the fifth clock pulse;

The pull-up switching element of the 8k + 6 stage is supplied with the sixth clock pulse;

The pull-up switching device of the 8k + 7 stage is supplied with the seventh clock pulse;

The pull-up switching device of the 8k + 8 stage is supplied with the eighth clock pulse;

The first noise canceling unit of the 8k + 1 stage is supplied with the eighth clock pulse;

The first noise canceling unit of the 8k + 2 stage is supplied with the first clock pulse;

The first noise canceling unit of the 8k + 3 stage is supplied with the second clock pulse;

The first noise canceling portion of the 8k + 4 stage is supplied with a third clock pulse;

The first noise canceling section of the 8k + 5 stage is supplied with a fourth clock pulse;

The first noise canceling unit of the 8k + 6 stage is supplied with the fifth clock pulse;

The first noise canceling section of the 8k + 7 stage is supplied with the sixth clock pulse;

The first noise canceling unit of the 8k + 8 stage is supplied with the seventh clock pulse;

The second noise canceling unit of the 8k + 1 stage is supplied with the second clock pulse;

The second noise canceling unit of the 8k + 2 stage is supplied with a third clock pulse;

The second noise canceling unit of the 8k + 3 stage is supplied with the fourth clock pulse;

The second noise canceling unit of the 8k + 4 stage is supplied with the fifth clock pulse;

The second noise canceling unit of the 8k + 5 stage is supplied with the sixth clock pulse;

The second noise canceling unit of the 8k + 6 stage is supplied with the seventh clock pulse;

The second noise canceling unit of the 8k + 7 stage is supplied with the eighth clock pulse;

The second noise canceling unit of the 8k + 8 stage is supplied with the first clock pulse;

The pull-down switching device of the 8k + 1 stage is supplied with the fifth clock pulse;

The pull-down switching device of the 8k + 2 stage is supplied with the sixth clock pulse;

The pull-down switching device of the 8k + 3 stage is supplied with the seventh clock pulse;

The pull-down switching element of the 8k + 4 stage is supplied with the eighth clock pulse;

The pull-down switching device of the 8k + 5 stage is supplied with the first clock pulse;

The pull-down switching device of the 8k + 6 stage is supplied with the second clock pulse;

A pull-down switching element of the 8k + 7 stage is supplied with a third clock pulse;

The pull-down switching device of the 8k + 8 stage is supplied with the fourth clock pulse.

In another way,

The pull-down switching device of the 8k + 1 stage is supplied with a fourth clock pulse;

The pull-down switching device of the 8k + 2 stage is supplied with the fifth clock pulse;

The pull-down switching device of the 8k + 3 stage is supplied with the sixth clock pulse;

The pull-down switching element of the 8k + 4 stage is supplied with the seventh clock pulse;

The pull-down switching element of the 8k + 5 stage is supplied with the eighth clock pulse;

The pull-down switching device of the 8k + 6 stage is supplied with the first clock pulse;

The pull-down switching device of the 8k + 7 stage is supplied with the second clock pulse;

The pull-down switching device of the 8k + 8 stage may receive the third clock pulse.

In another way,

The pull-down switching device of the 8k + 1 stage is supplied with a sixth clock pulse;

The pull-down switching element of the 8k + 2 stage is supplied with the seventh clock pulse;

The pull-down switching device of the 8k + 3 stage is supplied with the eighth clock pulse;

The pull-down switching element of the 8k + 4 stage is supplied with the first clock pulse;

The pull-down switching device of the 8k + 5 stage is supplied with the second clock pulse;

The pull-down switching device of the 8k + 6 stage is supplied with a third clock pulse;

The pull-down switching device of the 8k + 7 stage is supplied with the fourth clock pulse;

The pull-down switching device of the 8k + 8 stage may receive the fifth clock pulse.

Meanwhile, in order to prevent a circuit malfunction due to leakage current, the stage illustrated in FIGS. 4 to 7 may have a structure as follows.

FIG. 10 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration in FIG. 10 is almost the same as that in FIG. 4, and only the configuration of the node control unit NC will be described. Therefore, only the configuration of the node control unit NC will be described.

As shown in FIG. 10, the node controller NC includes a first A switching element Tr1_A, a first B switching element Tr1_B, a second A switching element Tr2_A, and a second B switching element Tr2_B. It includes.

The first A switching device Tr1_A is turned on / off according to the scan pulse from the k-2 stage, and outputs the forward voltage V_F at turn-on.

The first B switching element Tr1_B is turned on / off according to the scan pulse from the k-2 stage, and the forward node V_F from the first A switching element Tr1_A is turned on when the turn-on is turned on. Supply to (Q).

The second A switching element Tr2_A is turned on / off according to the scan pulse from the k + 2th stage and outputs the reverse voltage V_R at turn-on.

The second B switching element Tr2_B is turned on / off according to the scan pulse from the k + 2 stage, and sets the reverse voltage V_R from the second A switching element Tr2_A at turn-on. Supply to node Q.

The pair of first A and first B switching elements Tr1_A and Tr1_B provided in the k-th stage are simultaneously turned on by the k-th scan pulse, and the pair of second A provided in the k-th stage And the second B switching elements Tr2_A and Tr2_B are simultaneously turned on by the k + 2th scan pulse.

On the other hand, the k-th stage may be set according to the scan pulse from the k-3rd stage and may be reset according to the scan pulse from the k + 3th stage. That is, the first A switching device Tr1_A and the first B switching device Tr1_B provided in the kth stage receive the scan pulse from the k-3th stage, and the second A switching device provided in the kth stage. The Tr2_A and the second B switching element Tr2_B may receive the scan pulse from the k + 3th stage.

FIG. 11 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration in FIG. 11 is almost the same as that in FIG. 5, and only the configuration of the node controller has the structure in FIG. 10 described above.

FIG. 12 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration in FIG. 12 is almost the same as that in FIG. 6, and only the configuration of the node controller has the structure in FIG. 10 described above.

FIG. 13 is a diagram illustrating another circuit configuration of any stage of FIG. 1.

The circuit configuration in Fig. 13 is almost the same as in Fig. 7, except that the configuration of the node control section has the structure in Fig. 10 described above.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 illustrates a shift register according to an embodiment of the present invention.

2 is a timing diagram of various signals supplied to the shift register of FIG. 1 during forward driving;

3 is a timing diagram of various signals supplied to the shift register of FIG. 1 during reverse driving;

4 is a diagram showing the circuit configuration of an arbitrary stage of FIG.

FIG. 5 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

FIG. 6 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

FIG. 7 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

8 is a timing diagram of first to sixth clock pulses supplied to a shift register of the present invention;

FIG. 9 is a diagram illustrating an output of a k-th and k + 1th stages supplied with a clock pulse in FIG. 8; FIG.

FIG. 10 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

FIG. 11 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

12 illustrates another circuit configuration of an arbitrary stage of FIG. 1.

FIG. 14 shows another circuit arrangement of an arbitrary stage of FIG. 1. FIG.

Claims (10)

At least two clock transmission lines for transmitting at least two clock pulses having different phase differences, and a plurality of stages sequentially receiving output clock pulses from each clock transmission line and sequentially outputting an output signal; Each stage, A node controller for controlling the signal state of the set node and controlling the output order of the scan pulses of the stages according to the forward voltage and the reverse voltage having phases inverted from each other; A pull-up switching device which is turned on / off according to a signal state of a set node, and outputs any one of the clock pulses as a scan pulse through an output terminal at turn-on; A first noise canceling unit which is turned on / off according to any one of the clock pulses, and supplies a start pulse from the outside or a scan pulse from a front end stage to the set node upon turn-on; And, A shift register which is turned on / off according to any one of the clock pulses and includes a second noise canceling unit which supplies an external start pulse or an output signal from a next stage to the set node when the clock pulse is turned on . The method of claim 1, The node controller of the kth stage is A first switching device turned on / off according to a scan pulse from a k-2 or k-3 stage and supplying the forward voltage to the set node when turned on; And a second switching device which is turned on / off according to the scan pulse from the k + 2 or k + 3 stages, and supplies the reverse voltage to the set node when turned on. The method of claim 2, The first noise canceling unit provided in the k-th stage is turned on / off according to any one of the clock pulses, and supplies a start pulse from the outside or a scan pulse from the k-th stage to the set node during turn-on. ; And, The second noise canceling unit provided in the k-th stage is turned on / off according to any one of the clock pulses, and supplies a start pulse from the outside or a scan pulse from the k + 1 stage to the set node when the turn-on is turned on. A shift register characterized by the above-mentioned. The method of claim 3, wherein Each stage, And a pull-down switching device which is turned on / off according to any one of the clock pulses and outputs a low potential voltage through the output terminal at turn-on. The method of claim 3, wherein Each stage, And a third switching device which is turned on / off according to the signal state of the output terminal and connects between the drain terminal and the source terminal of the pull-up switching device at turn-on. The method of claim 3, wherein Each stage, A pull-down switching device which is turned on / off according to any one of the clock pulses and outputs a low potential voltage through the output terminal when turned on; And, And a third switching device which is turned on / off according to the signal state of the output terminal and connects between the drain terminal and the source terminal of the pull-up switching device at turn-on. The method according to any one of claims 4 to 6, The clock pulses include first to sixth clock pulses having a phase difference from each other; The pull-up switching device of the 6k + 1 stage is supplied with a first clock pulse; The pull-up switching device of the 6k + 2 stage is supplied with a second clock pulse; The pull-up switching device of the 6k + 3 stage is supplied with a third clock pulse; The pull-up switching device of the 6k + 4 stage is supplied with a fourth clock pulse; The pull-up switching element of the 6k + 5 stage is supplied with the fifth clock pulse; The pull-up switching element of the 6k + 6 stage is supplied with the sixth clock pulse; The first noise canceling unit of the 6k + 1 stage is supplied with the sixth clock pulse; The first noise canceling unit of the 6k + 2 stage is supplied with the first clock pulse; The first noise canceling unit of the 6k + 3 stage is supplied with the second clock pulse; The first noise canceling section of the 6k + 4 stage is supplied with a third clock pulse; The first noise canceling section of the 6k + 5 stage is supplied with a fourth clock pulse; The first noise canceling unit of the 6k + 6 stage is supplied with the fifth clock pulse; The second noise canceling unit of the 6k + 1 stage is supplied with a second clock pulse; The second noise canceling unit of the 6k + 2 stage is supplied with a third clock pulse; The second noise canceling unit of the 6k + 3 stage is supplied with a fourth clock pulse; The second noise canceling unit of the 6k + 4 stage is supplied with the fifth clock pulse; The second noise canceling unit of the 6k + 5 stage is supplied with the sixth clock pulse; The second noise canceling unit of the 6k + 6 stage is supplied with the first clock pulse; The pull-down switching device of the 6k + 1 stage is supplied with a fourth clock pulse; The pull-down switching element of the 6k + 2 stage is supplied with the fifth clock pulse; The pull-down switching device of the 6k + 3 stage is supplied with the sixth clock pulse; The pull-down switching element of the 6k + 4 stage is supplied with the first clock pulse; The pull-down switching element of the 6k + 5 stage is supplied with the second clock pulse; And, The shift register of the 6k + 6 stage is supplied with a third clock pulse. The method according to any one of claims 4 to 6, The clock pulses include first to eighth clock pulses having a phase difference from each other; The pull-up switching device of the 8k + 1 stage is supplied with a first clock pulse; The pull-up switching device of the 8k + 2 stage is supplied with the second clock pulse; The pull-up switching device of the 8k + 3 stage is supplied with a third clock pulse; The pull-up switching device of the 8k + 4 stage is supplied with a fourth clock pulse; The pull-up switching element of the 8k + 5 stage is supplied with the fifth clock pulse; The pull-up switching element of the 8k + 6 stage is supplied with the sixth clock pulse; The pull-up switching device of the 8k + 7 stage is supplied with the seventh clock pulse; The pull-up switching device of the 8k + 8 stage is supplied with the eighth clock pulse; The first noise canceling unit of the 8k + 1 stage is supplied with the eighth clock pulse; The first noise canceling unit of the 8k + 2 stage is supplied with the first clock pulse; The first noise canceling unit of the 8k + 3 stage is supplied with the second clock pulse; The first noise canceling portion of the 8k + 4 stage is supplied with a third clock pulse; The first noise canceling section of the 8k + 5 stage is supplied with a fourth clock pulse; The first noise canceling unit of the 8k + 6 stage is supplied with the fifth clock pulse; The first noise canceling section of the 8k + 7 stage is supplied with the sixth clock pulse; The first noise canceling unit of the 8k + 8 stage is supplied with the seventh clock pulse; The second noise canceling unit of the 8k + 1 stage is supplied with the second clock pulse; The second noise canceling unit of the 8k + 2 stage is supplied with a third clock pulse; The second noise canceling unit of the 8k + 3 stage is supplied with the fourth clock pulse; The second noise canceling unit of the 8k + 4 stage is supplied with the fifth clock pulse; The second noise canceling unit of the 8k + 5 stage is supplied with the sixth clock pulse; The second noise canceling unit of the 8k + 6 stage is supplied with the seventh clock pulse; The second noise canceling unit of the 8k + 7 stage is supplied with the eighth clock pulse; The second noise canceling unit of the 8k + 8 stage is supplied with the first clock pulse; The pull-down switching device of the 8k + 1 stage is supplied with the fifth clock pulse; The pull-down switching device of the 8k + 2 stage is supplied with the sixth clock pulse; The pull-down switching device of the 8k + 3 stage is supplied with the seventh clock pulse; The pull-down switching element of the 8k + 4 stage is supplied with the eighth clock pulse; The pull-down switching device of the 8k + 5 stage is supplied with the first clock pulse; The pull-down switching device of the 8k + 6 stage is supplied with the second clock pulse; A pull-down switching element of the 8k + 7 stage is supplied with a third clock pulse; The shift register of the 8k + 8th stage is supplied with the fourth clock pulse. The method of claim 1, A shift register, wherein clock pulses output in adjacent periods among clock pulses supplied to each stage are simultaneously active for a predetermined period. The method of claim 1, The node controller of the kth stage is A first A switching element which is turned on / off in response to a scan pulse from a k-2 or k-3 stage and outputs the forward voltage when turned on; A first B switching element which is turned on / off according to a scan pulse from the k-2 or k-3 stage and supplies a forward voltage from the first A switching element to the set node when turned on; A second A switching device which is turned on / off in response to a scan pulse from a k + 2 or k + 3 stage and outputs the reverse voltage at turn-on; And, A second B switching element which is turned on / off according to a scan pulse from the k + 2 or k + 3 stages and supplies a reverse voltage from the second A switching element to the set node at turn-on; A shift register.

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