KR101319356B1 - A shift register of a liquid crystal display device and a method for driving the same - Google Patents

Abstract

The present invention relates to a shift register of a liquid crystal display device capable of minimizing a size by reducing the number of the node controllers by allowing one node controller provided in the stage to control at least two output units. In a shift register of a liquid crystal display device having four stages, each stage sequentially outputs at least two scan pulses by using at least two overlapping clock pulses and sequentially supplies them to each gate line of the liquid crystal panel. It is characterized by.

LCD, shift register, node control section, output section

Description

Shift register of a liquid crystal display device and a method for driving the same

1 is a block diagram of a conventional shift register.

2 is a block diagram of a shift register of a liquid crystal display according to a first embodiment of the present invention.

FIG. 3 is a schematic view illustrating a second stage shown in FIG. 2.

4 is a timing diagram of clock pulses supplied to a shift register of FIG. 2; FIG.

5 is a timing diagram of yet another clock pulses supplied to the shift register of FIG. 2; FIG.

6 is a circuit diagram illustrating a node controller and first to second output units of FIG. 3.

7 is a timing diagram of yet another clock pulses supplied to the shift register of FIG. 3; FIG.

8 is a waveform diagram illustrating a simulation result using the start pulse and the clock pulses shown in FIG. 5.

FIG. 9 is a waveform diagram illustrating a simulation result using the start pulse and the clock pulses shown in FIG. 8. FIG.

10 is a view showing a shift register for a liquid crystal display according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating a node controller provided in the second stage of FIG. 10.

12 is a timing diagram of various signals supplied to the shift register of FIG. 10 and scan pulses output from the shift register;

FIG. 13 is a detailed configuration diagram of a node controller provided in the second stage of FIG. 10.

Fig. 14 is a view showing a shift register for a liquid crystal display device according to a third embodiment of the present invention.

FIG. 15 is a timing diagram of various signals supplied to the shift register of FIG. 14 and scan pulses output from the shift register; FIG.

＊ Description of symbols for main parts of the drawings ＊

300a to 300e: first to nth stages

CLK1 to CLK4: first to fourth clock pulses

Vout1 to Voutn + 1: First to nth + 1 scan pulses

300f: dummy stage

The present invention relates to a shift register of a liquid crystal display device that sequentially outputs at least two scan pulses by using at least two clock pulses in which one stage is overlapped, and sequentially supplies them to each gate line of the liquid crystal panel. .

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged in an intersecting manner, and a pixel region is located in an area defined by vertically intersecting the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed on the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source electrode and a drain electrode of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to the gate electrode via the gate line, so that the data signal of the data line is charged to the pixel voltage.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The timing controller controls driving timing of the gate driver and the data driver and supplies a pixel data signal to the data driver. The power supply unit boosts or depressurizes the input power source to generate driving voltages such as a common voltage VCOM, a gate high voltage signal VGH, and a gate low voltage signal VGL required by the liquid crystal display device. The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Here, the gate driver includes a shift register for sequentially outputting the scan pulses as described above. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of a conventional shift register.

The conventional shift register is composed of n stages 100a to 100e and one dummy stage 100f connected to each other, as shown in FIG. 1. Here, each of the stages 100a to 100e outputs one scan pulse Vout1 to Voutn, and at this time, the scan pulses Vout1 to Voutn are sequentially output from the first stage 100a to the nth stage 100e. do. As such, the scan pulses Vout1 to Voutn output from the stages 100a to 100e are sequentially supplied to the gate lines of the liquid crystal panel to sequentially scan the gate lines.

The entire stages 100a to 100f of the shift register configured as described above share one of a high potential voltage source VDD, a low potential voltage source VSS, and two clock pulses CLK1 and CLK2 having phases opposite to each other. Licensed as Here, the high potential voltage source VDD represents a constant voltage, and the low potential voltage source VSS represents a ground voltage.

The operation of the conventional shift register constructed as described above is as follows.

First, when a start pulse VST from a timing controller (not shown) is applied to the first stage 100a, the first stage 100a is enabled in response to the start pulse VST. Subsequently, the enabled first stage 100a receives the first clock pulse CLK1 from the timing controller and outputs the first scan pulse Vout1, which is then used to output the first gate line and the second stage 100b. Feed together. Then, the second stage 100b is enabled in response to the first scan pulse Vout1. Subsequently, the enabled second stage 100b receives the second clock pulse CLK2 from the timing controller and outputs a second scan pulse Vout2, and the second gate line and the third stage 100c. ) And the first stage 100a together. Then, the third stage 100c is enabled in response to the second scan pulse Vout2, and the first stage 100a supplies the low potential voltage source VSS to the first gate line. Subsequently, the enabled third stage 100c receives the first clock pulse CLK1 from the timing controller and outputs a third scan pulse Vout3, and the third gate line and the fourth stage 100d. And the second stage 100b. Then, the fourth stage 100d is enabled in response to the third scan pulse Vout3, and the second stage 100b supplies the low potential voltage source VSS to the second gate line. In this manner, the fifth to nth scan pulses Voutn are sequentially output to the remaining fifth to nth stages 100e and sequentially applied to the fifth to nth gate lines. As a result, the first to nth gate lines are sequentially scanned by the sequentially output first to nth scan pulses Vout1 to Voutn.

On the other hand, the dummy stage 100f is enabled in response to the nth scan pulse Voutn from the nth stage 100e, and then the first or second clock signal CLK1 or CLK2 from the timing controller. Receives the n + 1 th scan pulse Voutn + 1. The nth stage 100e may provide the low potential voltage source VSS to an nth gate line by supplying the nth + 1 scan pulse Voutn + 1 to the nth stage 100e. Make sure

However, the conventional shift register having such a configuration has the following problems.

As described above, each stage outputs only one scan pulse. Therefore, in order to scan all the gate lines of the liquid crystal panel, the conventional shift register must include a large number of stages and one dummy stage corresponding to the number of gate lines. For this reason, the overall size of the shift register is inevitably increased, and such a large size makes it difficult for a conventional shift register to be integrated on a liquid crystal panel of a liquid crystal display device.

That is, recently, in order to reduce the size of the liquid crystal display device, a liquid crystal display device in which the shift register is formed on the glass substrate of the liquid crystal panel has been developed (in which case, the shift register is the same as the thin film transistor array of the liquid crystal panel). Since the conventional shift registers require a large number of stages as described above, there are many difficulties in integrating the shift registers in a limited narrow space of the glass substrate. In addition, a glass substrate made of a hydrogenated amorphous silicon material is used in the liquid crystal panel because of the advantage of not causing a characteristic change during light irradiation. Since the amorphous silicon has a low current mobility, the shift resistor is placed on the glass substrate. When integrated, the size of the switching device included in the stage must be increased to overcome the low current mobility, which in turn increases the size of the shifter resistor.

The present invention has been made to solve the above problems, in the shift register having a plurality of stages are connected to each other, each stage using at least two overlapping clock pulses at least two scan pulses It is an object of the present invention to provide a shift register of a liquid crystal display device which outputs sequentially and supplies the same to the gate lines of the liquid crystal panel, thereby reducing the number of stages while minimizing signal distortion.

The shift register of the liquid crystal display device according to the present invention for achieving the above object, in the shift register of the liquid crystal display device having a plurality of stages connected to each other, at least two clock pulses each stage is overlapped It is characterized in that at least two scan pulses are output in sequence, and these are sequentially supplied to each gate line of the liquid crystal panel.

In addition, the shift register of the liquid crystal display according to the present invention for achieving the above object includes a plurality of stages in order to output the scan pulse, each stage in turn in accordance with the signal state of the first node At least two outputting the low potential voltage sources in accordance with the signal states of the at least two second output switching element third nodes outputting the low potential voltage sources in accordance with the signal states of the at least two first output switching element second nodes. And three third output switching elements and the second node and the third node to be kept in a low logic state when the first node is in a high logic state, and the second node and when the first node is in a low logic state. A node controller for maintaining one of the third nodes in the high logic state and the other node in the low logic state. And characterized in that the adapted to also.

Hereinafter, the shift register of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a shift register of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the exemplary embodiment of the present invention includes n stages 300a to 300e and one dummy stage 300f connected to each other independently. 300a to 300e sequentially output at least two scan pulses (Vout1 to Vout2, Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Voutn-1 to Voutn), and output them to each of the liquid crystal panels (not shown). Supply to the gate line (not shown) in sequence. FIG. 2 illustrates an example in which each stage 300a to 300e sequentially outputs two scan pulses Vout1 to Vout2, Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Voutn-1 to Voutn. As described above, the stages 300a to 300e output two scan pulses Vout1 to Vout2, Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Voutn-1 to Voutn. ) Scans the entire gate line in two. Therefore, when driving the same resolution liquid crystal panel, the shift register of the present invention can scan the entire gate lines of the liquid crystal panel using fewer stages 300a to 300f than in the prior art. Therefore, the shift register according to the present invention may have a smaller size than in the prior art.

Here, each of the stages 300a to 300e sequentially outputs two scan pulses Vout1 to Vout2, Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Voutn-1 to Voutn. 300e) is enabled by receiving the last scan pulse output from the two scan pulses output from the previous stage. The enabled stage is supplied with four clock pulses CLK1 to CLK4 sequentially output from a timing controller (not shown), where the enabled stage receives the first clock pulse CLK1 supplied in time first. The first scan pulse Vout1 is output, and the second clock pulse CLK2 supplied is output as the second scan pulse Vout2. The enabled stage supplies the first scan pulse to a first gate line of two gate lines connected to the first stage to drive the first gate line first, and then to the second gate line. The scan pulse is supplied to drive the second gate line.

In addition, each of the stages 300a to 300e is disabled by receiving the last scan pulse output from the two scan pulses output from the next stage. This disabled stage outputs a low potential voltage source VSS, and simultaneously supplies the low potential voltage source VSS to all the gate lines connected thereto to deactivate the gate lines.

On the other hand, since there is no stage in front of the first stage 300a, the first stage 300a is enabled by receiving a start pulse VST from a timing controller (not shown). Since the stage does not exist next to the dummy stage 300f, the dummy stage 300f is disabled by the first clock pulse CLK1 from the timing controller.

The scan pulse Voutn + 1 output from the dummy stage 300f is not supplied to the gate line. That is, the scan pulse Voutn + 1 output from the dummy stage 300f is supplied to the nth stage 300e and serves to disable the nth stage 300e.

For this driving, each stage has the following configuration.

3 is a configuration diagram schematically illustrating the first stage illustrated in FIG. 2.

Here, since the configurations of the stages 300a to 300e are the same, only the first stage 300a will be representatively described.

As illustrated in FIG. 3, the first stage 300a includes one node controller 500 and two outputs connected to the node controller 500 through first and second nodes Q to QB. Sections 503a to 503b.

The node controller 500 controls the logic states of the first and second nodes Q to QB. That is, the node controller makes the first node Q in a high logic state in response to a start pulse (or a scan pulse of a previous stage) from the timing controller (or a previous stage), and the second node. Make (QB) low logic. In addition, the node controller 300 sets the first node Q to a low logic state in response to the scan pulse Vout4 from the next stage (ie, the second stage), and the second node ( Make QB) high logic.

In this case, each of the nodes Q through QB may be in a high logic state through the high potential voltage source VDD from the outside or the scan pulse Vout2 from the front end stage 300a. Each of the nodes Q through QB is in a low logic state through the low potential voltage source VSS.

When the first node Q is in a high logic state, the first clock pulse CLK1 to which the first output unit 503a is first supplied is output as the first scan pulse Vout1 and supplied to the first gate line. In addition, the second output unit 503b outputs the second clock pulse CLK2, which is then supplied, as a second scan pulse Vout2, and supplies the second clock pulse Vout2 to the second gate line.

In addition, when the second node QB is in a high logic state, the first and second output units 503a to 503b output a low potential voltage source VSS and are simultaneously supplied to the first and second gate lines. do.

The first output unit 503a includes a first pull-up switching device Tr7 and a first pull-down switching device Tr8, and the second output unit 503b includes a second pull-up switching device Tr9 and a second And a pull-down switching device Tr10.

The first pull-up switching device Tr7 is turned on when the first node Q has a high logic value to output the first clock pulse CLK1 as the first scan pulse Vout1, and the second pull-up switching. The device Tr9 is turned on when the first node Q is in a high logic state to output the second clock pulse CLK2 as the second scan pulse Vout2. The first and second pull-down switching devices Tr8 to Tr10 are turned on when the second node QB is in a high logic state to output a low potential voltage source VSS.

Meanwhile, a plurality of clock pulses CLK1 to CLK4 having a phase difference from each other are supplied to the shift register of the present invention configured as described above.

4 is a diagram illustrating a timing diagram of clock pulses supplied to the shift register of FIG. 2, and FIG. 5 is a diagram illustrating another timing diagram of clock pulses supplied to the shift register of FIG. 2. That is, clock pulses CLK1 to CLK4 as shown in FIG. 4 or clock pulses CLK1 to CLK4 as shown in FIG. 5 may be supplied to the shift register of the present invention.

As shown in FIG. 4, each of the clock pulses CLK1 to CLK4 has the same amplitude and pulse width. Each of these clock pulses CLK1 to CLK4 has a high logic value in another period not overlapping each other. The pulse width of each clock pulse CLK1 to CLK4 corresponds to about 1H period (one horizontal period).

On the other hand, as shown in Figure 5, each of the clock pulses (CLK1 to CLK4) can be output at the same time with a high logic value for a predetermined period of time. That is, the overlapping clock pulses CLK1 to CLK4 will be described in more detail as follows.

Each of the clock pulses CLK1 to CLK4 illustrated in FIG. 5 has the same pulse width and amplitude, and the clock pulses CLK1 to CLK4 output in adjacent time zones are simultaneously simultaneously high-logic values in a predetermined section. Has That is, the second clock pulse CLK2 is output later than the first clock pulse CLK1, where the second clock pulse CLK2 is before the first clock pulse CLK2 is completely maintained at a low logic value. That is, the first clock pulse CLK1 starts to rise to the high logic value within the period of still maintaining the high logic value, and maintains the high logic value for the 1.5H period. Accordingly, the first clock pulse CLK1 and the second clock pulse CLK2 have a high logic value simultaneously for a predetermined period.

Similarly, the third clock pulse CLK3 is output later than the second clock pulse CLK2 so that the second clock pulse CLK2 starts to rise to a high logic value within a period in which the second clock pulse CLK2 maintains a high logic value. Maintain a high logic value for the duration. The fourth clock pulse CLK4 is output later than the third clock pulse CLK3 to start rising to a high logic value for a period of 1.5H while maintaining the high logic value of the third clock pulse CLK3. Keep the logic high. In addition, since each of the clock pulses CLK1 to CLK4 is periodically outputted, the first clock pulse CLK1 is output later than the fourth clock pulse CLK4 at the next period after one cycle. The clock pulse CLK1 starts to rise to the high logic value within the period in which the fourth clock pulse CLK4 maintains the high logic value and maintains the high logic value for 1.5H period.

It is preferable to set the period in which the high logic values between clock pulses adjacent to each other simultaneously have a value larger than 0H and smaller than the period corresponding to the entire pulse width. The period in which the clock pulses adjacent to each other shown in the figure simultaneously have a high logic value, that is, the overlapping period is about 0.5H. On the other hand, the start pulse VST is output before the first clock pulse CLK1, and the start pulse VST does not overlap the first clock pulse CLK1. Of course, although not shown in the figure, the start pulse VST and the first clock pulse CLK1 may be superimposed and output in the manner described above.

Here, although the pulse widths of the clock pulses CLK1 to CLK4 shown in FIG. 5 are extended by 0.5 H periods longer than the clock pulse widths shown in FIG. 4, the clock pulses CLK1 to CLK4 shown in FIG. 5 are extended. ) Is simultaneously output in this 0.5H period, so that the time from the first clock pulse CLK1 to the fourth clock pulse CLK4 in FIG. 3 and the first clock pulse CLK1 to the fourth clock pulse CLK4 in FIG. The output time until) is the same.

As described above, when the respective clock pulses CLK1 to CLK4 as shown in FIG. 4 are supplied to the shift register of the present invention, the operation of each stage will be described.

Since the operation of all the stages is the same, the operation of the first stage will be described as follows.

First, the first node Q is in a high logic state by the start pulse VST output in the enable period T0, and the second node QB is in a low logic state. Then, both the first and second pull-up switching devices Tr7 to Tr9 having gate terminals connected to the first node Q are turned on. Thereafter, the first clock pulse CLK1 is output as the first scan pulse Vout1 through the turned-on first pull-up switching device Tr7 in the first period T1.

At this time, when the first clock pulse CLK1 is supplied to the source terminal of the first pull-up switching device Tr7 in the first period T1, the source terminal of the first pull-up switching device Tr7 and the first pull-up The voltage of the gate terminal is increased by the coupling phenomenon between the gate terminals of the switching element Tr7 (boot strapping). That is, while the first clock pulse CLK1 rises to a high logic value, the voltage of the gate terminal also rises in synchronization with it.

Here, since the gate terminal is connected to the first node Q, the voltage of the first node Q is raised. Accordingly, the first pull-up switching device Tr7 can be turned on almost completely, whereby the first clock pulse CLK1 is output with almost no distortion thereof. In other words, the first scan pulse CLK1 is supplied to the first gate line without attenuating its signal size.

However, while the first clock pulse CLK1 falls to a low logic value during the second period T2, the voltage of the first node Q drops rapidly in synchronization with the first clock pulse CLK1. In this state, the second clock pulse CLK2 is supplied to the source terminal of the second pull-up switching element Tr9.

In addition, when the second clock pulse CLK2 is supplied to the source terminal of the second pull-up switching device Tr9 in the second period T2, the source terminal and the second terminal of the second pull-up switching device Tr9 are provided. The voltage of the gate terminal is increased by the coupling phenomenon between the gate terminals of the pull-up switching device (bootstrap). That is, as the second clock pulse CLK2 rises to a high logic value, the voltage of the gate terminal also rises in synchronization with it.

However, even though the voltage of the first node Q rises as described above, the voltage of the first node Q is rapidly increased due to the first clock pulse CLK1 that is already kept at a low logic value. Since the voltage is reduced, the voltage of the first node Q may not increase significantly even by the second clock pulse CLK2. That is, the voltage of the first node Q has a voltage magnitude insufficient to completely turn on the second pull-up switching device Tr9. Specifically, as shown in FIG. 4, the voltage of the first node Q in the second period T2 is smaller than the voltage of the first node Q in the first period T1. It can be seen that. Accordingly, the second scan pulse Vout2 output from the second pull-up switching device Tr9 is distorted and output.

Next, the operation of each stage when the clock pulse as shown in FIG. 5 is supplied to the shift register of the present invention as follows is as follows.

First, the first node Q is in a high logic state and the second node QB is in a low logic state by the start pulse VST output in the enable period T0.

Then, both the first and second pull-up switching devices Tr7 and Tr9 having gate terminals connected to the first node Q are turned on. Thereafter, the first clock pulse CLK1 is output as the first scan pulse Vout1 through the turned-on first pull-up switching device Tr7 in the first period T1. At this time, when the first clock pulse CLK1 is supplied to the source terminal of the first pull-up switching device Tr7 in the first period T1, the source terminal of the first pull-up switching device Tr7 and the first pull-up The voltage of the gate terminal is increased by the coupling phenomenon between the gate terminals of the switching element Tr7 (primary bootstrapping). That is, while the first clock pulse CLK1 rises to a high logic value, the voltage of the gate terminal also rises in synchronization with it.

Here, since the gate terminal is connected to the first node Q, the voltage of the first node Q is raised. Accordingly, the first pull-up switching device Tr7 can be turned on almost completely, whereby the first clock pulse CLK1 is output with almost no distortion thereof. In other words, the first scan pulse Vout1 is supplied to the first gate line without attenuating its signal size.

Thereafter, the second clock pulse CLK2 is output while the second period T2 is started. That is, in the second period T2, the second clock pulse CLK2 has a high logic value. On the other hand, since the first clock pulse CLK1 has a high logic value from the first period T1 to the second period T2, the first and second clock pulses CLK1 during the second period T2. CLK2) has a high logic value at the same time. Accordingly, during the second period T2, the voltage of the first node Q rapidly rises in synchronization with the high logic values of the first and second clock pulses CLK1 and CLK2 (secondary bootstrapping). .

From this second period T2, the second pull-up switching device Tr9 remains completely turned on. Therefore, the second scan pulse Vout2 output from the second pull-up switching device Tr9 in this second period T2 is output without distortion.

On the other hand, in the third period T3, the second clock pulse CLK2 still shows a high logic value, while the first clock pulse CLK2 has a low logic value. Accordingly, the voltage of the first node Q drops in synchronization with the low logic value of the first clock pulse CLK1 in the third period T3. However, since the second clock pulse CLK2 still maintains a high logic value in the third period T3, the voltage of the first node Q does not abruptly fall but remains for the first period T1. It has a value almost equal to the voltage of the first node Q. Accordingly, the second pull-up switching device Tr9 may remain fully turned on for the third period T3, and thus, the second scan pulse T3 output through the second pull-up switching device Tr9. Vout2) is not distorted.

Meanwhile, the stages 300a to 300f according to the present invention may output three or more scan pulses. In this case, clock pulses CLK1 to CLK4 corresponding to the number of scan pulses Vout1 to Voutn + 1 are supplied to each of the stages 300a to 300f. That is, in order to design each stage 300a to 300f to output k scan pulses (k is a natural number of 2 or more), k clock pulses may be supplied to the stages 300a to 300f.

6 is a circuit diagram illustrating a node controller and first to second output units of FIG. 3.

As shown in FIG. 6, the first stage 300a includes a node controller 500 for controlling the logic state of the first node Q and the logic state of the second node QB, and the first node. A first output unit 503a and a second that are turned on according to the state of Q and the second node QB to selectively output each clock pulse CLK1 to CLK2 or the low potential voltage source VSS; It consists of the output part 503b.

Here, the configuration of the node control unit 500 will be described in detail.

First, as shown in FIG. 5, each node controller 500 of the first stage 300a includes a gate terminal and a high potential voltage source VDD to which a start pulse VST from a timing controller is input. A gate terminal to which a first switching element Tr1 having a drain terminal applied, a source terminal connected to the first node Q, and a scan pulse Vout4 output from the second stage 300b are input. A gate terminal to which a second switching element Tr2 and a fourth clock pulse CLK4 are input, the source terminal to which the low potential voltage source VSS is applied, and a drain terminal connected to the first node Q, and A drain terminal to which the high potential voltage source VDD is applied, a third switching element Tr3 having a source terminal connected to the second node QB, and a gate terminal connected to the drain terminal of the second switching element Tr2, Drain terminal connected to the second node QB And a drain terminal connected to a source terminal of the fourth switching element Tr4 and the first switching element Tr1 having a source terminal to which the low potential voltage source VSS is applied, and the low potential voltage source VSS is applied. A gate terminal to which a fifth switching element Tr5 having a source terminal and a gate terminal connected to the second node QB and the start pulse VST are input, a drain terminal connected to the second node QB, And a sixth switching element Tr6 having a source terminal to which the low potential voltage source VSS is applied. However, gate pulses of the first switching element Tr1 and the sixth switching element Tr6 included in the second to nth stages 300b to 300e are provided at the end of the stage of the previous stage. Vout2, Vout4 to Voutn) are input.

Here, the first node Q and the second node QB alternately have a high or low logic value. That is, the second node QB maintains a low logic value when the first node Q is in a high logic state, and the first node Q when the second node QB is in a high logic state. Will keep the logic low.

Next, the configuration of the first to second output units 503a to 503b will be described in detail as follows.

The reason that the first stage 300a includes two output units 503a to 503b is that, as described above, each of the stages 300a to 300e outputs two scan pulses Vout1 to Vout2. It is assumed.

 The first output unit 503a has a seventh switching element having a gate terminal connected to the first node Q, a drain terminal to which the first clock pulse CLK1 is applied, and a source terminal connected to the first gate line. Tr7, a gate terminal connected to the second node QB, a source terminal of the seventh switching element Tr7 and a drain terminal connected to the first gate line, and the low potential voltage source VSS are applied. An eighth switching element Tr8 having a source terminal is provided.

The second output unit 503b has a ninth switching element having a gate terminal connected to the first node Q, a drain terminal to which the second clock pulse CLK2 is applied, and a source terminal connected to a second gate line. A tenth having a Tr9, a gate terminal connected to the second node QB, a drain terminal connected to a source terminal of the ninth switching element Tr9, and a source terminal to which the low potential voltage source VSS is applied; The switching element Tr10 is provided. That is, the two output units 503a to 503b sequentially output the scan pulses Vout1 to Vout2 under the control of the node controller 500. In other words, each stage 300a to 300e includes one node controller 500 and two output units 503a to 503b controlled by the one node controller 500. Therefore, each stage 300a to 300e sequentially outputs two scan pulses Vout1 to Vout2, Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Voutn-1 to Voutn.

 The first output unit 503a switches the first clock pulse CLK1 input from the timing controller when the first node Q is in a high logic state, and supplies the first clock pulse CLK1 to the gate line as the first scan pulse Vout1. do. In this case, each input terminal of each of the output units 503a to 503b is commonly connected to the node controller 500, and each output terminal is connected to the gate lines, respectively. The clock pulses CLK1 to CLK2 supplied to the output units 503a to 503b have a phase difference of one pulse width from each other. Therefore, when the first node Q is in a high logic state, the second output unit 503b switches the second clock pulse CLK2 input from the timing control to serve as a second scan pulse Vout2. To feed. The output units 503a to 503b switch the low potential voltage source VSS from the power supply unit (not shown) to supply the gate line when the second node QB is in a high logic state. .

Although not shown, the dummy stage 300f having the same configuration as the first stage 300a makes the first node Q of the nth stage 300e low, and the second node QB. ) Provides one scan pulse (Voutn + 1) needed to bring the logic into a high logic state, and does not provide a scan pulse (Voutn + 1) to the gate line. Therefore, the dummy stage 300f may include a node controller 500 and one output unit 503a. In the output part 503a of the dummy stage 300f, a second output part (most lastly, a clock pulse applied to the output part 503b outputting the scan pulse Voutn) provided in the n-th stage 300e is provided. A clock pulse with a phase delay of one clock pulse is applied.

As described above, each stage 300a to 300e has one node controller 500 and two output units 503a to 503b which are commonly controlled by the one node controller 500. The total number of outputs included in the shift registers having the stages 300a to 300e having the above structure is equal to the total number of gate lines of the liquid crystal panel. Therefore, the total number of output units included in the shift register of the present invention is the same as the number of conventional output units (200b in FIG. 2), but in the related art, one node control unit (200a in FIG. 2) is used for one output unit (FIG. 2). In the present invention, since one node controller 500 controls two output units 503a to 503b in common, the shift register of the present invention has a smaller number of node controllers 400 than in the related art. ) Will be provided. Therefore, the size of the shift register of the present invention becomes smaller than in the prior art. In the present invention, one node controller 500 controls two output units 503a to 503b as an example. However, the one node controller 500 may be configured to control three or more output units. .

The operation of the shift register of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail with reference to FIGS. 5 and 6.

First, the start pulse VST output from the timing controller is input to the first stage 300a. Specifically, as shown in FIG. 5, the start pulse VST is input to the gate terminals of the first switching element Tr1 and the sixth switching element Tr6 provided in the first stage 300a. Then, the first switching element Tr1 and the sixth switching element Tr6 are turned on, and at this time, the low potential voltage source (eg, through the drain terminal and the source terminal of the turned-on first switching element Tr1). VDD) is applied to the first node (Q). In addition, the low potential voltage source VST is applied to the second node QB via the drain terminal and the source terminal of the turned-on sixth switching element Tr6. Accordingly, the fourth, seventh, and ninth switching elements Tr4, Tr7, and Tr9 having gate terminals connected to the first node Q in common are turned on. Thus, as shown in FIG. 5, the first node Q of the first stage 300a is in a high logic state with the high potential voltage source VDD, and the second node QB is in a low logic state. As a result, the first stage 300a is enabled.

Subsequently, when the first clock pulse CLK1 overlapped for a period larger than OH and smaller than one pulse width is input to the drain terminal of the seventh switching element Tr7, the high potential voltage source VDD of the first node Q is applied. ) Is amplified by bootstrapping and the first clock pulse CLK1 acts as a scan pulse on the first gate line via the drain terminal and the source terminal of the seventh switching element Tr7 so as to be more stable. . The second clock pulse CLK2 of the ninth switching element Tr9 has a phase difference delayed by one pulse width from the first clock pulse CLK1 but overlapped for a period greater than OH and smaller than one pulse width. When input to the drain terminal, the high potential voltage source VDD of the first node Q is further amplified by bootstrapping as shown in FIG. 4, and the second clock pulse CLK2 is turned on to be more stable. The second gate line acts as a scan pulse through the drain terminal and the source terminal of the ninth switching element Tr9. At this time, the second clock pulse CLK2 is supplied to the second gate line and to the second stage 300b which is the next stage.

Although not shown in the drawings, the second scan pulse includes the first switching element Tr1 and the sixth switching element Tr6 provided in the second stage 300b having the same configuration as the first stage 300a. Is input to the gate terminal.

Therefore, the first switching element Tr1 and the sixth switching element Tr6 of the second stage 300b are turned on, and at this time, the drain terminal and the source of the turned-on first switching element Tr1 are turned on. The high potential voltage source VDD is applied to the first node Q via the terminal. In addition, the low potential voltage source VSS is applied to the second node QB via the drain terminal and the source terminal of the turned-on sixth switching element Tr6. As a result, the fourth, seventh and ninth switching elements Tr4, Tr7 to Tr9 having the gate terminal connected to the first node Q in common are turned on. Therefore, as shown in FIG. 4, the first node Q of the second stage 300b is in a high logic state with a high potential voltage source VDD, and the second node QB is in a low logic state. As a result, the second stage 300b is enabled.

Subsequently, when the third clock pulse CLK3 overlapped for a predetermined period is input to the drain terminal of the seventh switching element Tr7, the high potential voltage source VDD of the first node Q is formed by bootstrapping. The seventh switching element Tr7 amplified and the gate terminal connected to the first node Q is connected to the third clock pulse CLK3 via the drain terminal and the source terminal of the seventh switching element Tr7. The scan gate acts on the third gate line. In addition, the fourth clock pulse CLK4 having a phase difference delayed by one pulse width from the third clock pulse CLK3 and overlapping for a period smaller than one pulse width is connected to the drain terminal of the ninth switching element Tr9. When input, the high potential voltage source VDD of the first node Q amplified by the superimposed three clock pulses CLK3 is further amplified by bootstrapping as shown in FIG. 5 and the fourth clock. The pulse CLK4 acts as a scan pulse to the second gate line via the drain terminal and the source terminal of the ninth switching element Tr9 turned on to be more stable. In this case, the fourth clock pulse CLK4 is supplied to the fourth gate line and to the first stage 300a and the third stage 300c.

Since the fourth stage 300c also has the same configuration as the first stage 300a and the second stage 300b, the operation as described above by receiving the fourth scan pulse from the second stage 300b. Will be performed.

On the other hand, the fourth scan pulse Vout4 output from the second stage 300b is input to the gate terminal of the second switching element Tr2 of the first stage 300a and the fourth clock pulse CLK4 is input to the fourth scan pulse Vout4. 3 is input to the gate terminal of the switching element Tr3. Therefore, the first node Q connected to the drain terminal of the second switching element Tr2 is in a low logic state by the low potential voltage source VSS and the high voltage connected to the drain terminal of the third switching element Tr3. The second node QB is in a high logic state by the voltage source VDD. Therefore, a low potential voltage source VSS is supplied to the first gate line and the second gate line.

In the same manner as described above, the remaining second to nth stages 300a to 300e respectively output two sequential scan pulses Vout3 to Vout4, Vout5 to Vout6, Vout7 to Vout8, and Vout-n to Voutn. Supply the lines sequentially.

FIG. 7 is a timing diagram of still another clock pulses supplied to the shift register of FIG. 3.

As shown in FIG. 7, although the first to fourth clock pulses CLK1 to CLK4 have bootstrapping to prevent distortion of a signal and have a phase difference from each other to generate a normal output voltage. Overlaid for a certain period of time. That is, the overlapping period of the first to fourth clock pulses CLK1 to CLK4 is possible for a period larger than OH and smaller than one pulse width based on the four-phase clock. In addition, the first to fourth clock pulses CLK1 to CLK4 are phase-delayed by one pulse width and output. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is output by one pulse than the second clock pulse CLK2. The phase delay is output by the width, and the fourth clock pulse CLK4 is output by being phase-delayed by one pulse width than the third clock pulse CLK3. On the other hand, the start pulse VST is output for 2H once per frame and does not overlap the first to fourth clock pulses CLK1 to CLK4.

8 is a waveform diagram illustrating a simulation result using the start pulse and the clock pulses shown in FIG. 5.

As shown in FIG. 8, as a result of simulation using the start pulse VST and the first to fourth clock pulses CLK1 to CLK4 shown in FIG. 5, the high potential charged in the first node Q is shown. The voltage source VDD is amplified by bootstrapping. That is, as the start pulse VST is applied, the first node Q has a high logic value at the high potential voltage source VDD, and the superimposed first clock pulse CLK1 and the second second pulse voltage have a high logic value. Amplified by clock pulse CLK2. Thereafter, the second node QB1 is in a high logic state by the high potential voltage source VDD and the first node Q is in a low logic state by the low potential voltage source VSS.

9 is a waveform diagram illustrating a simulation result using the start pulse and the clock pulses shown in FIG. 7.

As shown in FIG. 9, as a result of simulation using the start pulse VST and the first to fourth clock pulses CLK1 to CLK4 shown in FIG. 7, the high potential charged in the first node Q is shown. The voltage source VDD is amplified by bootstrapping. That is, as the start pulse VST is applied, the first node Q has a high logic value at the high potential voltage source VDD, and the superimposed first clock pulse CLK1 and the second second pulse voltage have a high logic value. Amplified by clock pulse CLK2. Thereafter, the second node QB1 is in a high logic state by the high potential voltage source VDD and the first node Q is in a low logic state by the low potential voltage source VSS. However, in the fourth period T4, unlike the simulation waveform illustrated in FIG. 9, the voltage of the first node Q does not immediately fall into a low logic state but maintains a high logic state.

When the non-overlapping clock pulses are applied, that is, compared to the first node voltage O_QV to which the clock pulses shown in FIG. 4 are applied, the first node voltage O_QV is the first non-overlapping first clock pulse ( It can be seen that the timing falls further when the timing O_CLK1 is applied and the second clock pulse O_CLK2 is applied. However, it can be seen that the first node voltage QV according to the embodiment of the present invention is amplified by bootstrapping when the overlapping first clock pulse CLK1 is applied and the second clock pulse CLK2 is applied.

In the embodiment according to the present invention, the high potential voltage source VDD charged to each of the stages 300a to 600e and the first node of the dummy stage 300f by using four clock pulses CLK1 to CLK4 superimposed on each other. As amplified by the bootstrapping, each of the switching elements Tr1 to Tr24 can be turned on and off completely.

Hereinafter, a shift register for a liquid crystal display according to a second embodiment of the present invention will be described in detail.

10 illustrates a shift register for a liquid crystal display according to a second embodiment of the present invention.

The shift register for a liquid crystal display according to the second embodiment of the present invention includes a plurality of stages 130a to 130e and dummy stages 130f connected to each other, as shown in FIG. 10.

Each stage 130a to 130f receives three clock pulses out of four clock pulses CLK1 to CLK4 having phase differences from each other, and sequentially outputs three scan pulses.

Each stage 130a through 130f is enabled in response to a scan pulse from the front end stages 130a through 130f. In the enabled state, three clock pulses are sequentially supplied, and these three clock pulses are output as scan pulses, respectively, and are sequentially supplied to three gate lines.

At this time, each stage 130a to 130f enables the next stage by supplying the last scan pulse among the three scan pulses output from the stage to the next stage. In addition, each stage 130a to 130f disables the shear stage by supplying the first stage of the three scan pulses output from the front stage to the front stage. The disabled stage outputs a low potential voltage source VSS to three gate lines.

For example, the second stage 130b is supplied with the third scan pulse Vout3 that is output last among the first to third scan pulses Vout1 to Vout3 output from the first stage 130a. That is, the third stage 130c is enabled in response to the third scan pulse Vout3 from the first stage 130a.

Thereafter, the enabled second stage 130b outputs the fourth clock pulse CLK4 supplied thereto as the fourth scan pulse Vout4, and outputs the first clock pulse CLK1 to the fifth scan pulse Vout5. ), And the second clock pulse CLK2 is output as the sixth scan pulse Vout6.

The fourth to sixth scan pulses Vout4 to Vout6 output from the second stage 130b are sequentially supplied to the fourth to sixth gate lines.

The sixth scan pulse Vout6 output from the second stage 130b is supplied to the third stage 130c to enable the third stage 130c.

Then, as described above, the third stage 130c sequentially outputs the seventh to ninth scan pulses Vout7 to Vout9. In this case, the seventh scan pulse Vout7 output for the first of the seventh to ninth scan pulses Vout7 to Vout9 output from the third stage 130c is supplied to the second stage 130b. Then, the second stage 130b outputs the low potential voltage source VSS in response to the seventh scan pulse Vout7 and simultaneously supplies the same to the fourth to sixth gate lines.

Here, the configuration of each stage 130a to 130f will be described in more detail as follows.

FIG. 11 is a diagram illustrating a node controller provided in the second stage of FIG. 10.

Each stage 130a to 130f includes the first to third nodes Q, QB1, and QB2, the first to third pull-up switching devices Trup1, Trup2, and Trup3, and the first to sixth pull-down switching devices Trdw1 and Trdw2. , Trdw3, Trdw4, Trdw5, Trdw6), and the node controller 110.

The first to third pull-up switching devices Trup1 to Trup3 sequentially output scan pulses according to the signal state of the first node Q. That is, each of the first to third pull-up switching devices Trup1 to Trup3 provided in the first stage 130a receives the first to third clock pulses CLK1, CLK2, and CLK3, and then receives the first to third clock pulses CLK1, CLK2, and CLK3. Output as scan pulses Vout1 to Vout3.

The first to third pull-down switching devices Trdw1 to Trdw3 output the low potential voltage source VSS according to the signal state of the second node QB1.

The fourth to sixth pull-down switching devices Trdw4 to Trdw6 output the low potential voltage source VSS according to the signal state of the third node QB2.

The node controller 110 controls the second and third nodes QB1 and QB2 to be kept in a low logic state (discharge state) when the first node Q is in a high logic state (charge state), When the first node Q is in a low logic state, one of the second node QB1 and the third node QB2 is maintained in a high logic state and the other node is kept in a low logic state. .

The stage being enabled means that the first node Q of the stage is maintained in the charged state and the second and third nodes QB1 and QB2 are kept in the discharged state.

In addition, the stage being disabled means that the first node Q of the stage is maintained in a discharge state, and either one of the second and third nodes QB1 and QB2 is kept in a charged state.

12 is a timing diagram of various signals supplied to the shift register of FIG. 10 and scan pulses output from the shift register, and FIG. 13 is a detailed configuration diagram of a node controller provided in the second stage of FIG. 10.

The node controller 110 of each stage 130a to 130f includes first to eighteenth switching elements Tr1 to Tr18.

The first switching element Tr1 of each stage 130a to 130f charges the first node Q to the high potential voltage source VDD in response to the scan pulse last output from the front end stage. That is, the first switching device Tr1 included in the second stage 130b may operate the first node Q in response to the third scan pulse Vout3 from the first stage 130a. VDD). To this end, the gate terminal of the first switching element Tr1 is connected to the first stage 130a, the source terminal is connected to a power line for transmitting the high potential voltage source VDD, and the drain terminal is connected to the first terminal 130a. It is connected to one node Q.

The second switching element Tr2 of each of the stages 130a to 130f discharges the second node QB1 to the low potential voltage source VSS in response to the scan pulse last output from the previous stage. That is, the second switching device Tr2 included in the second stage 130b may move the second node QB1 to the low potential voltage source VSS in response to the third scan pulse Vout3 from the first stage 130a. To discharge). To this end, the gate terminal of the second switching element Tr2 is connected to the first stage 130a, the source terminal is connected to the second node QB1, and the drain terminal is connected to the low potential voltage source VSS. It is connected to the power line to transmit.

The third switching element Tr3 of each of the stages 130a to 130f discharges the third node QB2 to the low potential voltage source VSS in response to the scan pulse last output from the previous stage. That is, the third switching device Tr3 included in the second stage 130b may move the third node QB2 to the low potential voltage source VSS in response to the third scan pulse Vout3 from the first stage 130a. To discharge). To this end, the gate terminal of the third switching device Tr3 is connected to the first stage 130a, the source terminal is connected to the third node QB2, and the drain terminal is connected to the low potential voltage source VSS. It is connected to the power line to transmit.

The fourth switching device Tr4 of each of the stages 130a to 130f turns the second node QB1 into the low potential voltage source VSS in response to the high potential voltage source VDD charged in the first node Q. Discharge. To this end, the gate terminal of the fourth switching device Tr4 is connected to the first node Q, the source terminal is connected to the second node QB1, and the drain terminal is connected to the low potential voltage source VSS. It is connected to the power line to transmit.

The fifth switching element Tr5 of each of the stages 130a to 130f may turn the third node QB2 into the low potential voltage source VSS in response to the high potential voltage source VDD charged in the first node Q. To discharge. To this end, the gate terminal of the fifth switching device Tr5 is connected to the first node Q, the source terminal is connected to the third node QB2, and the drain terminal is connected to the low potential voltage source VSS. It is connected to the power line to transmit.

The sixth switching element Tr6 of each of the stages 130a to 130f is turned on or turned off in response to the first AC voltage source Vac1 having a different voltage source for each frame. Output the voltage source Vac1. To this end, the gate terminal of the sixth switching element Tr6 is connected to a power line for transmitting the first AC voltage source Vac1, and the source terminal is connected to a power line for transmitting the first AC voltage source Vac1. do.

The seventh switching element Tr7 of each of the stages 130a to 130f transmits the second node QB1 to the first alternating voltage source in response to the first alternating voltage source Vac1 from the sixth switching element Tr6. Charge to (Vac1). To this end, the gate terminal of the seventh switching element (Tr7) is connected to the drain terminal of the sixth switching element (Tr6), the source terminal is connected to a power line for transmitting the first AC voltage source (Vac1), The drain terminal is connected to the second node QB1.

The eighth switching element Tr8 of each of the stages 130a to 130f responds to the first alternating voltage source Vac1 charged in the second node QB1 and turns the first node Q to a low potential voltage source. VSS). To this end, the gate terminal of the eighth switching device Tr8 is connected to the second node QB1, the source terminal is connected to the first node Q, and the drain terminal of the low potential voltage source VSS. It is connected to the power line to transmit.

The ninth switching device Tr9 of each of the stages 130a to 130f is connected to the gate terminal of the seventh switching device Tr7 in response to the high potential voltage source VDD charged in the first node Q. The seventh switching device Tr7 is turned off by supplying the potential voltage source VSS. To this end, the gate terminal of the ninth switching element Tr9 is connected to the first node Q, the source terminal is connected to the gate terminal of the seventh switching element Tr7, and the drain terminal of the low potential It is connected to a power supply line that transmits a voltage source VSS.

The tenth switching element Tr10 of each of the stages 130a to 130f has a low potential voltage source VSS at the gate terminal of the seventh switching element Tr7 in response to the scan pulse last output from the previous stage. The seventh switching device Tr7 is turned off by supplying. That is, the tenth switching device Tr10 of the second stage 130b is connected to the gate terminal of the seventh switching device Tr7 in response to the third scan pulse Vout3 from the first stage 130a. The seventh switching device Tr7 is turned off by supplying a low potential voltage source VSS. To this end, the gate terminal of the tenth switching element Tr10 is connected to the first stage 130a, the source terminal is connected to the gate terminal of the seventh switching element Tr7, and the drain terminal of the low potential voltage source. It is connected to the power line which transmits (VSS).

The eleventh switching element Tr11 of each of the stages 130a to 130f is turned on or turned off in response to the second AC voltage source Vac2 having a different voltage source every frame, and when turned on, the second AC power source Tr11 is turned on. Output the voltage source Vac2. To this end, a gate terminal of the eleventh switching element Tr11 is connected to a gate terminal for transmitting the second AC voltage source Vac2, and a source terminal is connected to a power line for transmitting the second AC voltage source Vac2. do.

Here, the second AC voltage source Vac2 and the first AC voltage source Vac1 have opposite logic states in the same frame.

The twelfth switching element Tr12 of each of the stages 130a to 130f transmits the third node QB2 to the second alternating voltage source in response to the second alternating voltage source Vac2 from the eleventh switching element Tr11. Charge to (Vac2). To this end, the gate terminal of the twelfth switching element Tr12 is connected to the drain terminal of the eleventh switching element Tr11, and the source terminal is connected to a power line for transmitting the second AC voltage source Vac2. The drain terminal is connected to the third node QB2.

The thirteenth switching element Tr13 of each of the stages 130a to 130f supplies the first node Q to the low potential voltage source VSS in response to the second AC voltage source Vac2 charged in the third node QB2. To discharge). To this end, the gate terminal of the thirteenth switching element Tr13 is connected to the third node QB2, the source terminal is connected to the first node Q, and the drain terminal of the low potential voltage source VSS. It is connected to the power line to transmit.

The fourteenth switching element Tr14 of each of the stages 130a to 130f is connected to the gate terminal of the twelfth switching element Tr12 in response to the high potential voltage source VDD charged in the first node Q. The twelfth switching element Tr12 is turned off by supplying the potential voltage source VSS. To this end, the gate terminal of the fourteenth switching element Tr14 is connected to the first node Q, the source terminal is connected to the gate terminal of the twelfth switching element Tr12, and the drain terminal of the low potential It is connected to a power supply line that transmits a voltage source VSS.

The fifteenth switching element Tr15 of each of the stages 130a to 130f has a low potential voltage source VSS at the gate terminal of the twelfth switching element Tr12 in response to the scan pulse last output from the previous stage. The twelfth switching element Tr12 is turned off by supplying. That is, the fifteenth switching element Tr15 of the second stage 130b is connected to the gate terminal of the twelfth switching element Tr12 in response to the third scan pulse Vout3 from the first stage 130a. The twelfth switching element Tr12 is turned off by supplying the potential voltage source VSS. To this end, the gate terminal of the fifteenth switching element Tr15 is connected to the first stage 130a, the source terminal is connected to the gate terminal of the twelfth switching element Tr12, and the drain terminal of the low potential voltage source. It is connected to the power line which transmits (VSS).

The sixteenth switching element Tr16 of each of the stages 130a to 130f is turned on or turned off in response to the first AC voltage source Vac1, and when turned on, the third node QB2 has a low potential. Discharge to voltage source VSS. To this end, a gate terminal of the sixteenth switching element Tr16 is connected to a power line for transmitting the third voltage source, a source terminal is connected to the third node QB2, and a drain terminal of the low potential voltage source ( VSS) is connected to the power supply line.

The seventeenth switching device Tr17 of each of the stages 130a to 130f is turned on or turned off in response to the second AC voltage source Vac2, and when turned on, the second node QB1 has a low potential. Discharge to voltage source VSS. To this end, a gate terminal of the seventeenth switching element Tr17 is connected to a power line for transmitting the fourth voltage source, a source terminal is connected to the second node QB1, and a drain terminal is connected to the low potential voltage source ( VSS) is connected to the power supply line.

The eighteenth switching device Tr18 discharges the first node Q to the low potential voltage source VSS in response to the scan pulse first output from the next stage. That is, the eighteenth switching device Tr18 discharges the first node Q to the low potential voltage source VSS in response to the seventh scan pulse Vout7 from the third stage 130c. To this end, the gate terminal of the eighteenth switching element Tr18 is connected to the third stage 130c, the source terminal is connected to the first node Q, and the drain terminal of the low potential voltage source VSS. It is connected to the power line to transmit.

On the other hand, since the stage does not exist in front of the first stage 130a, the first, second, third, ninth, and fourteenth switching elements Tr1, Tr2, and Tr3 included in the first stage 130a are provided. , Tr9 and Tr14 are controlled by the start pulse Vst from the timing controller.

Since the stage does not exist at the rear end of the dummy stage 130f, the eighteenth switching element Tr18 included in the dummy stage 130f is controlled by the start pulse Vst.

The operation of the shift register having such a circuit configuration is as follows.

First, the operation during the initial period T0 of the first frame will be described.

Prior to this, since the first AC voltage source Vac1 is in a high logic state during the first frame, the sixth and sixteenth switching elements Tr6 and Tr16, which are supplied through the gate terminal, are turned on during the first frame. Keep it. In addition, since the second AC voltage source Vac2 is in a low logic state during the first frame, the eleventh and seventeenth switching elements Tr11 and Tr17 supplied with the gate terminal are turned off during the first frame. do.

During the initial period T0, only the start pulse Vst remains high, as shown in FIG.

The start pulse Vst may include a gate terminal of the first switching element Tr1, a gate terminal of the second switching element Tr2, a gate terminal of the third switching element Tr3, and a tenth switching element Tr10. Is applied to the gate terminal and the gate terminal of the fifteenth switching element Tr15 to turn the first, second, third, tenth and fifteenth switching elements Tr1, Tr2, Tr3, Tr10 and Tr15. -Turn on.

Then, the high potential voltage source VDD is supplied to the first node Q through the turned-on first switching device Tr1. In this case, as the first node Q is charged with the high potential voltage source VDD, fourth, fifth, ninth, and fourteenth switching elements having gate terminals connected to the first node Q, Tr4, Tr5, Tr9, and Tr14, and the first to third pull-up switching devices Trup1 to Trup3 are all turned on.

At this time, the low potential voltage source VSS is supplied to the second node QB1 through the turned-on second and fourth switching devices Tr2 and Tr4. Thus, the second node QB1 is discharged, the eighth switching device Tr8 having a gate terminal connected to the discharged second node QB1, and the first to third pull-down switching devices Trdw1 to Both Trdw3) are turned off.

The low potential voltage source VSS is supplied to the third node QB2 through the turned-on third, fifth, and sixteenth switching elements Tr3, Tr5, and Tr16. Accordingly, the third node QB2 is discharged, the thirteenth switching device Tr13 having a gate terminal connected to the discharged third node QB2, and the fourth to sixth pull-down switching devices Trdw4 to Trdw6. ) Is turned off.

Meanwhile, the first AC voltage source Vac1 and the low potential voltage source VSS are simultaneously supplied to the gate terminal of the seventh switching element Tr7. That is, the first AC voltage source Vac1 is supplied to the gate terminal of the seventh switching device Tr7 through the turned-on sixth switching device Tr6. The low potential voltage source VSS is supplied to the gate terminal of the seventh switching device Tr7 through the turned-on ninth and tenth switching devices Tr9 and Tr10. In this case, since the number of transistors for supplying the low potential voltage source VSS is greater than the number of transistors for supplying the first AC voltage source Vac1 to the gate terminal of the seventh switching element Tr7, the seventh switching element ( The gate terminal of Tr7) is maintained as a low potential voltage source VSS. Therefore, the seventh switching device Tr7 maintains the turn-off state in the initial period T0. In addition, since the low potential voltage source VSS supplied through the turned-on fourteenth and fifteenth switching elements Tr14 and Tr15 is applied to the gate terminal of the twelfth switching element Tr12, the initial period T0. The twelfth switching element Tr12 maintains a turn-off state.

On the other hand, the start pulse Vst output in the initial period T0 is also supplied to the dummy stage 130f. That is, the start pulse Vst is supplied to the gate terminal of the eighteenth switching element Tr18 provided in the dummy stage 130f. The eighteenth switching element Tr18 is turned on by the start pulse Vst. Then, the low potential voltage source VSS is supplied to the first node Q of the dummy stage 130f through the turned-on eighteenth switching element Tr18. As a result, the first node Q of the dummy stage 130f is maintained in a discharged state.

In summary, the first stage 130a is enabled and the dummy stage 130f is disabled in the initial period T0. That is, the first node Q of the first stage 130a is charged, and the second and third nodes QB1 and QB2 are discharged. The first node Q of the dummy stage 130f is discharged.

The operation during the first period T1 will now be described.

During the first period T1, as shown in FIG. 12, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low. Therefore, the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 of the first stage 130a in response to the low state start pulse Vst. Is turned off, so that the first node Q of the first stage 130a remains in a floating state.

Meanwhile, as the first node Q of the first stage 130a is continuously maintained as the high potential voltage source VDD applied during the initial period T0, the first to the first to 130th portions of the first stage 130a are maintained. 3 The pull-up switching devices Trup1 to Trup3 remain turned on. At this time, as the first clock pulse CLK1 is applied to the source terminal of the turned-on first pull-up switching device Tr19, the high potential charged in the first node Q of the first stage 130a. The voltage source VDD is amplified by bootstrapping. Thus, the first pull-up switching device Trup1 is almost completely turned on. Accordingly, the first clock pulse CLK1 applied to the source terminal of the first pull-up switching device Trup1 of the first stage 130a is stably output through the drain terminal of the first pull-up switching device Trup1. do. In this case, the output first clock pulse CLK1 is applied to a first gate line to serve as a first scan pulse Vout1 for driving the first gate line.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 12, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the second pull-up switching device Trup2 provided in the first stage 130a. Accordingly, the second clock pulse CLK2 applied to the source terminal of the second pull-up switching device Trup2 of the first stage 130a is stably output through the drain terminal of the second pull-up switching device Trup2. do. In this case, the output second clock pulse CLK2 is applied to a second gate line to serve as a second scan pulse Vout2 for driving the second gate line.

Next, the operation during the third period T3 will be described.

During the third period T3, as shown in FIG. 12, only the third clock pulse CLK3 remains high and the remaining clock pulses remain low.

The third clock pulse CLK3 is supplied to the third pull-up switching device Trup3 provided in the first stage 130a. Accordingly, the third clock pulse CLK3 applied to the source terminal of the third pull-up switching device Trup3 of the first stage 130a is stably output through the drain terminal of the third pull-up switching device Trup3. do. In this case, the output third clock pulse CLK3 is applied to a third gate line to serve as a third scan pulse Vout3 for driving the third gate line.

In this case, the third scan pulse Vout3 is supplied to the third gate line and input to the second stage 130b. Specifically, the third scan pulse Vout3 includes first, second, third, tenth, and fifteen switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 provided in the second stage 130b. Supplied to. Here, the third scan pulse Vout3 supplied to the second stage 130b plays the same role as the start pulse Vst supplied to the first stage 130a. That is, the second stage 130b charges its first node Q with the high potential voltage source VDD in response to the third scan pulse Vout3, and the second and third nodes QB1. , QB2) is discharged.

In summary, in the first to third periods T1, T2, and T3, the first stage 130a outputs first to third scan pulses Vout1 to Vout3, and the second stage 130b. Is enabled in response to the third scan pulse Vout3.

Next, the operation during the fourth period T4 will be described.

During the fourth period T4, as shown in FIG. 12, only the fourth clock pulse CLK4 is kept high and the remaining clock pulses are kept low.

Therefore, the third scan pulse Vout3 (that is, the third clock pulse CLK3) from the first stage 130a that has been applied in the third period T3 goes low in the fourth period T4. As the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 of the second stage 130b, which are applied through the gate terminal, are turned on. It is turned off, and thus the first node Q of the second stage 130b is kept in a floating state. In this case, as the fourth clock pulse CLK4 is applied to the source terminal of the first pull-up switching device Trup1 of the second stage 130b, the first node Q of the second stage 130b is applied. The charged high potential voltage source VDD is amplified by bootstrapping.

Therefore, the fourth clock pulse CLK4 applied to the source terminal of the first pull-up switching device Trup1 of the second stage 130b is stably output through the drain terminal of the first pull-up switching device Trup1. . In this case, the fourth clock pulse CLK4 output from the second stage 130b is applied to a fourth gate line to serve as a fourth scan pulse Vout4 driving the fourth gate line.

Next, the operation during the fifth period T5 will be described.

During the fifth period T5, as shown in FIG. 12, only the first clock pulse CLK1 remains high and the remaining clock pulses remain low.

The first clock pulse CLK1 is supplied to the second pull-up switching device Trup2 provided in the second stage 130b. Accordingly, the first clock pulse CLK1 applied to the source terminal of the second pull-up switching device Trup2 of the second stage 130b is stably output through the drain terminal of the second pull-up switching device Trup2. do. In this case, the output first clock pulse CLK1 is applied to a fifth gate line to serve as a fifth scan pulse Vout5 for driving the fifth gate line.

Next, the operation during the sixth period T6 will be described.

During the sixth period T6, as shown in FIG. 12, only the second clock pulse CLK2 remains high and the remaining clock pulses remain low.

The second clock pulse CLK2 is supplied to the third pull-up switching device Trup3 provided in the second stage 130b. Accordingly, the second clock pulse CLK2 applied to the source terminal of the third pull-up switching device Trup3 of the second stage 130b is stably output through the drain terminal of the third pull-up switching device Trup3. do. In this case, the output second clock pulse CLK2 is applied to a sixth gate line to serve as a sixth scan pulse Vout6 driving the sixth gate line.

On the other hand, the fourth scan pulse Vout4 output from the second stage 130b in the fourth period T4 is also input to the first stage 130a. In detail, the fourth scan pulse Vout4 is input to the gate terminal of the eighteenth switching element Tr18 provided in the first stage 130a. Herein, as the eighteenth switching device Tr18 of the first stage 130a is turned on by the fourth scan pulse Vout4, the low potential voltage source VSS is turned on. It is supplied to the first node Q of the first stage 130a through Tr18. Therefore, the first node Q of the first stage 130a is discharged by the low potential voltage source VSS. Then, the fourth, fifth, ninth, and fourteenth switching elements Tr4, Tr5, Tr9, and Tr14 having gate terminals connected to the first node Q of the first stage 130a in common. All of the first to third pull-up switching devices Trup1 to Trup3 are turned off.

Meanwhile, since the ninth and tenth switching elements Tr9 and Tr10 of the first stage 130a are turned off during the fourth period T4, the first stage (T4) during the fourth period T4. The second node QB1 of 130a is charged with the high potential voltage source VDD supplied through the seventh switching element Tr7. Therefore, all of the eighth switching element Tr8 and the first to third pull-down switching elements Trdw1 to Trdw3 having the gate terminal connected to the second node QB1 of the first stage 130a are turned on. . In this case, the low potential voltage source VSS is simultaneously supplied to the first to third gate lines through the turned-on first to third pull-down switching devices Trdw1 to Trdw3.

Meanwhile, the low potential voltage source VSS is supplied to the first node Q through the turned-on eighth switching device Tr8. As a result, during the fourth period T4, the first node Q of the first stage 130a is discharged by the eighth and eighteenth switching elements Tr8 and Tr18.

In addition, in the sixth period T6, the sixth scan pulse Vout6 output from the second stage 130b is input to the third stage 130c. Specifically, the sixth scan pulse Vout6 includes first, second, third, tenth, and fifteen switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 provided in the third stage 130c. Is input to the gate terminal of. Therefore, in the sixth period T6, the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 of the third stage 130c are all turned on. -On. Therefore, in the sixth period T6, the third stage 130c is enabled. That is, in the sixth period T6, the first node Q of the third stage 130c is charged, and the second and third nodes QB1 and QB2 are discharged.

In this manner, the scan pulse is output once from the first stage 130a to the dummy stage 130f.

In the second frame, the first AC voltage source is maintained in a low logic state, and the second AC voltage source is maintained in a high logic state. The second node QB1 is kept in the discharged state, and the third node QB2 is kept in the charged state. Accordingly, the fourth to sixth pull-down switching devices Trdw4 to Trdw6 operate in the second frame, and the first to third pull-down switching devices Trdw1 to Trdw3 do not operate.

On the other hand, each stage (130a to 130f) may be enabled in response to the second scan pulse output in the front stage, and may be disabled in response to the second scan pulse output in the next stage.

In this case, the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 provided in each of the stages 130a to 130f are second output from the front stage. Turned on according to the output pulse. The eighth switching device Tr8 included in each of the stages 130a to 130f is turned on according to the second scan pulse output from the next stage.

For example, the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 included in the second stage 130b may be provided from the first stage 130a. It is turned on according to the second scan pulse Vout2. The eighth switching device Tr8 of the second stage 130b is turned on according to the eighth scan pulse Vout8 from the third stage 130c.

Hereinafter, a shift register for a liquid crystal display according to a third embodiment of the present invention will be described in detail with reference to the accompanying drawings.

14 is a diagram illustrating a shift register for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 15 is a timing diagram of various signals supplied to the shift register of FIG. 14 and scan pulses output from the shift register. Drawing.

The shift register for a liquid crystal display according to the third exemplary embodiment of the present invention includes a plurality of stages 140a to 140e and a dummy stage 140f connected to each other, as shown in FIG. 14.

Each stage 140a to 140f receives three clock pulses out of five clock pulses CLK1 to CLK5 having phase differences from each other, and sequentially outputs three scan pulses.

The first to fifth clock pulses CLK1 to CLK5 are sequentially outputted with phase differences from each other, and clock pulses output in adjacent periods simultaneously exhibit a high logic state for a predetermined period. Accordingly, scan pulses output from adjacent stages also exhibit a high logic state at the same time for the predetermined period.

Each stage 140a through 140f is enabled in response to a scan pulse from the front end stage. In this enabled state, three clock pulses are sequentially supplied, and these three clock pulses are output as scan pulses, and are sequentially supplied to three gate lines. At this time, each of the stages 140a to 140f supplies the second stage of the three scan pulses output from the stage to the next stage to enable the next stage. In addition, each stage 140a to 140f supplies the second stage of the three scan pulses outputted therefrom to the front stage, thereby disabling the shear stage. The disabled stage outputs a low potential voltage source to supply three gate lines.

For example, the second stage 140b is supplied with the second scan pulse Vout2 output second from the first to third scan pulses Vout1 to Vout3 output from the first stage 140a. That is, the third stage 140c is enabled in response to the second scan pulse Vout2 from the first stage 140a.

Thereafter, the enabled second stage 140b outputs the fourth clock pulse CLK4 supplied thereto as the fourth scan pulse Vout4, and outputs the first clock pulse CLK1 to the fifth scan pulse Vout5. ), And the second clock pulse CLK2 is output as the sixth scan pulse Vout6.

The fourth to sixth scan pulses Vout4 to Vout6 output from the second stage 140b are sequentially supplied to the fourth to sixth gate lines.

The fifth scan pulse Vout5 output from the second stage 140b is supplied to the third stage 140c to enable the third stage 140c.

Then, in the same manner as described above, the third stage 140c sequentially outputs the seventh to ninth scan pulses Vout7 to Vout9. At this time, the second eighth scan pulse Vout8 output from the seventh to ninth scan pulses Vout7 to Vout9 output from the third stage 140c is supplied to the second stage 140b. . Then, the second stage 140b outputs the low potential voltage source VSS in response to the eighth scan pulse Vout8 and simultaneously supplies the same to the fourth to fifth gate lines.

The node controller of each stage 140a to 140f includes the first to eighteenth switching elements Tr1 to Tr18 shown in FIG. 13.

On the other hand, each stage 140a to 140f may be enabled in response to the scan pulse last output from the front stage, and may be disabled in response to the second scan pulse output from the next stage.

In this case, the gate terminals of the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 provided in each of the stages 140a to 140f have the most from the front stage. It is turned on according to the last scanned pulse. The gate terminal of the eighth switching element Tr8 provided in each of the stages 140a to 140f is turned on according to the second scan pulse output from the next stage.

For example, the first, second, third, tenth, and fifteenth switching elements Tr1, Tr2, Tr3, Tr10, and Tr15 included in the second stage 140b may be provided from the first stage 140a. It is turned on according to the third scan pulse Vout3. The eighth switching device Tr8 of the second stage 140b is turned on according to the eighth scan pulse Vout8 from the third stage 140c.

As a result, although the shift register according to an embodiment of the present invention uses four clock pulses CLK1 to CLK4, the present invention uses fewer node controllers by using only at least two clock pulses CLK1 to CLK2. Since the gate line can be driven at 500, the number of stages can be reduced, thereby reducing the area occupied by the shift register in the liquid crystal panel.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the shift register of the liquid crystal display according to the present invention has the following effects.

The shift register of the liquid crystal display according to the present invention includes a plurality of stages that are dependently connected to each other, and each stage is configured to output at least two scan pulses using at least two clock pulses supplied from a timing controller. have. To this end, each stage includes one node control unit and at least two output units sequentially outputting scan pulses under the control of the node control unit in common. Accordingly, by amplifying the node voltage with only at least two overlapping clock pulses, it is possible to completely turn on / off the switching element and reduce the number of the node controllers provided in the conventional shift register. As a result, the shift register of the present invention has a smaller size than the conventional one.

Claims (25)

In the shift register of the liquid crystal display device having a plurality of stages connected to each other, And each stage sequentially outputs at least two scan pulses using at least two overlapping clock pulses, and sequentially supplies them to each gate line of the liquid crystal panel. The method of claim 1, And the at least two scan pulses are sequentially superimposed for a period greater than 0H and less than one pulse width and sequentially output. The method of claim 1, Each of the stages sequentially outputs at least two superimposed scan pulses in response to the scan pulses outputted last from the previous stage, sequentially providing them to the gate lines of the liquid crystal panel, and simultaneously outputting the scanned scan pulses. The shift register of the liquid crystal display device, characterized in that to provide the scan pulse that is output at the end of the pulse to the previous stage and the next stage. The method of claim 3, wherein And a dummy stage for outputting one scan pulse in response to the scan pulse outputted last from the last stage of the stages and providing the scan pulse to the stage of the last stage. Shift register. The method of claim 3, wherein The first stage of the stages sequentially outputs at least two scan pulses in response to a start pulse from the timing controller, and sequentially supplies them to each gate line of the liquid crystal panel, and at the same time, the most of the scan pulses. A shift register of a liquid crystal display device, characterized by providing a scan pulse output at the end to a next stage. The method of claim 3, wherein Each stage includes a node controller for controlling the logic states of the first node and the second node; And And at least two output units configured to output one of the scan pulse, the low potential voltage source, and the high potential voltage source according to the logic states of the first node and the second node. The method of claim 3, wherein Each stage includes a node controller for controlling logic states of a first node, a second node, and a third node; And And at least two output units configured to output one of the scan pulse, the low potential voltage source, and the high potential voltage source according to logic states of the first node, the second node, and the third node. Shift register. The method of claim 6, The node control unit may include: a first switching element configured to make the first node a high logic state as a high potential voltage source in response to a scan pulse last output from a previous stage; A second switching element for bringing the first node into a low logic state as a low potential voltage source in response to a scan pulse last output from the next stage; A third switching element for bringing the second node into a high logic state as a high potential voltage source in response to a scan pulse last output from the next stage or a clock pulse input; A fourth switching element for bringing said second node into a low logic state using a low potential voltage source in response to a high potential voltage source having said first node in a high logic state; A fifth switching element for bringing said first node into a low logic state using a low potential voltage source in response to a high potential voltage source having said second node in a high logic state; And And a sixth switching element for bringing the second node into a low logic state by using a low potential voltage source in response to a scan pulse last output from the previous stage. Shift register. The method of claim 6, The at least two outputs comprise first and second outputs; The first and second output units may include: a seventh switching element configured to output a scan pulse in response to a high logic state of the first node and a clock pulse input; An eighth switching device configured to output a low potential voltage source in response to a low logic state of the second node; A ninth switching device configured to output a scan pulse in response to a high logic state of the first node and an input clock pulse; And And a tenth switching element outputting a low potential voltage source in response to a low logic state of the second node. The method according to claim 6 or 7, And a phase difference between the clock pulses input to each output unit by one pulse width. 11. The method of claim 10, And the clock pulses input to each output unit overlap each other for a period greater than OH and smaller than one pulse width. The method according to claim 6 or 7, The start pulse input to the node controller is 1H (Horizontal; horizontal period) to 2H, the shift register of the liquid crystal display device, characterized in that may not overlap with each clock pulse. The method according to claim 6 or 7, The width of the clock pulse input to each output unit is 1H (horizontal; horizontal period) to 2H, the shift register of the liquid crystal display device, characterized in that overlapping for a period greater than 0H and less than one pulse width. In the driving method of the shift register having a plurality of stages for sequentially outputting the scan pulse for driving the gate line of the liquid crystal panel for one frame, Inputting a scan pulse last output from the n-th stage to the n-th stage to enable the n-th stage; Outputting a first scan pulse by the nth stage as a first clock pulse is input to the nth stage; As the second clock pulse is input to the nth stage, the nth stage outputs a second scan pulse and supplies the n-1th stage and the n + 1th stage to disable the n-1th stage. And enabling the n + 1th stage of the shift register driving method of the liquid crystal display device. 15. The method of claim 14, And each stage outputs at least two superimposed scan pulses using at least two superimposed clock pulses. 15. The method of claim 14, And the scan pulses are superimposed on each other for a period greater than 0H and less than one pulse width. 15. The method of claim 14, The width of each clock pulse is 1H (horizontal; horizontal period) to 2H, the shift register driving method of the liquid crystal display device, characterized in that overlapping for a period greater than 0H and less than one pulse width. A plurality of stages which in turn output scan pulses; Each stage, At least two first output switching elements for outputting scan pulses in sequence according to the signal state of the first node; At least two second output switching devices for outputting a low potential voltage source according to the signal state of the second node; At least two third output switching devices configured to output the low potential voltage source according to a signal state of a third node; And When the first node is in a high logic state, the second and third nodes are controlled to be kept in a low logic state, and when the first node is in a low logic state, either one of the second node and the third node is high. And a node controller for maintaining the logic state and maintaining the other node in a low logic state. The method of claim 18, The first output switching device includes first, second, and third pull-up switching devices that are commonly connected to the first node and receive at least three clock pulses having a phase difference from each other, and sequentially output scan pulses. Includes; The second output switching device includes first, second, and third pull-down switching devices commonly connected to the second node to output the low potential voltage source; And, And the third output switching device comprises fourth, fifth, and sixth pull-down switching devices commonly connected to the third node to output the low potential voltage source. 20. The method of claim 19, And each stage is enabled in response to the scan pulse outputted last from the previous stage, and disabled in response to the scan pulse outputted first from the next stage. 21. The method of claim 20, The node control unit of each stage is A first switching element for bringing the first node into a high logic state in response to the scan pulse last output from the previous stage; A second switching element for bringing the second node into a low logic state in response to the scan pulse last output from the previous stage; A third switching device for bringing the third node into a low logic state in response to the scan pulse last output from the previous stage; A fourth switching element for making the second node in a low logic state in response to a high potential voltage source in which the first node is in a high logic state; A fifth switching device for bringing the third node into a low logic state in response to a high potential voltage source having the first node in a high logic state; A sixth switching element configured to output the first AC voltage source in response to the first AC voltage source whose logic state is inverted every frame; A seventh switching device for bringing the second node into a high logic state in response to a first AC voltage source from the sixth switching device; An eighth switching device which makes the first node low in logic in response to a high potential voltage source which has made the second node in high logic; A ninth switching device for turning off the seventh switching device in response to a high potential voltage source having the first node in a high logic state; A tenth switching element turning off the seventh switching element in response to the scan pulse last output from the previous stage; An eleventh switching element configured to output the second AC voltage source in response to a second AC voltage source having a logic state inverted with respect to the first AC voltage source; A twelfth switching element which makes the third node high logic in response to a second alternating current voltage source from the eleventh switching element; A thirteenth switching element which makes the first node low in logic in response to the high potential voltage source which has made the third node in high logic; A fourteenth switching device that turns off the twelfth switching device in response to a high potential voltage source which makes the first node high logic; A fifteenth switching element that turns off the twelfth switching element in response to the scan pulse last output from the previous stage; A sixteenth switching element for bringing the third node into a low logic state in response to the first AC voltage source; A seventeenth switching device which brings the second node into a low logic state in response to the second AC voltage source; And And an eighteenth switching element for bringing the first node into a low logic state in response to a scan pulse output first from a next stage. 20. The method of claim 19, And each stage is enabled in response to the scan pulse output second from the previous stage, and disabled in response to the scan pulse output first from the next stage. 23. The method of claim 22, The node control unit of each stage is A first switching device for bringing the first node into a high logic state in response to the second scan pulse output from the previous stage; A second switching device for bringing the second node into a low logic state in response to the second scan pulse output from the previous stage; A third switching device for bringing the third node into a low logic state in response to the second scan pulse output from the previous stage; A fourth switching element for making the second node in a low logic state in response to a high potential voltage source in which the first node is in a high logic state; A fifth switching device for bringing the third node into a low logic state in response to a high potential voltage source having the first node in a high logic state; A sixth switching element configured to output the first AC voltage source in response to the first AC voltage source whose logic state is inverted every frame; A seventh switching device for bringing the second node into a high logic state in response to a first AC voltage source from the sixth switching device; An eighth switching device which makes the first node low in logic in response to a high potential voltage source which has made the second node in high logic; A ninth switching device for turning off the seventh switching device in response to a high potential voltage source having the first node in a high logic state; A tenth switching element turning off the seventh switching element in response to the second scan pulse output from the previous stage; An eleventh switching element configured to output the second AC voltage source in response to a second AC voltage source having a logic state inverted with respect to the first AC voltage source; A twelfth switching element which makes the third node high logic in response to a second alternating current voltage source from the eleventh switching element; A thirteenth switching element which makes the first node low in logic in response to the high potential voltage source which has made the third node in high logic; A fourteenth switching device that turns off the twelfth switching device in response to a high potential voltage source which makes the first node high logic; A fifteenth switching element that turns off the twelfth switching element in response to the second scan pulse output from the previous stage; A sixteenth switching element for bringing the third node into a low logic state in response to the first AC voltage source; A seventeenth switching device which brings the second node into a low logic state in response to the second AC voltage source; And And an eighteenth switching element for bringing the first node into a low logic state in response to a scan pulse output first from a next stage. 20. The method of claim 19, Three clock pulses of at least five clock pulses having different phase differences and overlapping intervals of a high logic state for a predetermined period are supplied to the first, second, and third pull-up switching elements provided in each stage; And each stage is enabled in response to a second scan pulse output from a previous stage, and is disabled in response to a second scan pulse output from a next stage. 20. The method of claim 19, Three clock pulses of at least five clock pulses having different phase differences and overlapping intervals of a high logic state for a predetermined period are supplied to the first, second, and third pull-up switching elements provided in each stage; And each stage is enabled in response to the scan pulse outputted last from the previous stage, and disabled in response to the scan pulse outputted first from the next stage.

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