KR102321802B1 - Gate shift register and display device using the same - Google Patents

Abstract

The present invention provides a gate shift register capable of improving reliability by preventing multiple outputs from a gate line sharing one stage, and a display device using the same, wherein the gate shift register is a plurality of stages sequentially outputting scan pulses. Each of the plurality of stages includes a node controller for controlling voltages of the first, second and third nodes in response to an output control clock signal, and a plurality of clock signals in response to voltages of the second and third nodes. Accordingly, a gate output unit for selectively outputting a gate output signal may be included.

Description

GATE SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME

The present invention relates to a gate shift resistor, and more particularly, to a gate shift resistor capable of reducing an area when designing a gate shift resistor and a display device using the same.

Recently, a display device that is widely used includes a liquid crystal display device, an organic light emitting display device, and the like.

In general, a display device includes a display panel displaying an image, a gate driver supplying scan pulses to gate lines of the display panel, a data driver supplying data voltages to data lines of the display panel, and a gate driver and a timing controller for controlling the data driver.

The gate driver includes a gate shift register for driving a plurality of gate lines, and the gate shift register includes a plurality of stages for sequentially outputting scan pulses.

1 is a diagram illustrating a gate driver of a general display device.

In a typical display device, a gate driver receives a clock signal CLK from the timing controller to generate a gate output signal Vgout in each of the plurality of stages. The number of the clock signals CLK applied to the gate driver may be different depending on the driving method, and in the present invention, eight clock signals CLK are applied.

However, each of the plurality of stages is connected in a one-to-one correspondence with the plurality of gate lines to which the gate output signal Vgout is output. Accordingly, since each of the plurality of gate lines requires the plurality of stages, a problem arises in that a recent design of reducing the bezel area cannot be satisfied.

The present invention has been devised to solve the above problems, and it is a technical task to provide a gate shift register capable of applying a gate output signal by sharing one stage by a plurality of gate lines, and a display device using the same.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

A gate shift register and a display device using the same according to the present invention for achieving the above technical problem include a plurality of stages selectively connected to lines to which a plurality of clock signals are supplied, and each of the plurality of stages includes a plurality of A gate output signal may be selectively applied to the shared gate lines by being shared with the gate line.

According to the means for solving the above problems, the present invention has the following effects.

The gate shift register of the present invention generates a gate output signal using the clock signal and the output control clock signal applied from the timing controller, so that the first node and the second node of the gate driver can maintain stable values without noise. In particular, since a single stage is shared and used by a plurality of gate lines, the efficiency of the gate shift register can be increased, and the bezel corresponding to the non-display area of the panel can be reduced by reducing the area.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the art from such description and description.

1 is a block diagram showing a conventional gate shift register.
2 is a block diagram of a display device having a gate driver according to the present invention.
FIG. 3 is a configuration diagram illustrating a gate shift register constituting the gate driver shown in FIG. 2 .
Fig. 4 is a configuration circuit diagram of a first example for an arbitrary stage shown in Fig. 3;
5 is a driving waveform diagram of the gate shift register of the present invention.
Fig. 6 is a configuration circuit diagram of a second example for an arbitrary stage shown in Fig. 3;

The meaning of the terms described in this specification should be understood as follows. The singular expression is to be understood as including the plural expression unless the context clearly defines otherwise, and the terms "first", "second", etc. are used to distinguish one element from another, The scope of rights should not be limited by these terms. It should be understood that terms such as “comprise” or “have” do not preclude the possibility of addition or existence of one or more other features or numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It means a combination of all items that can be presented from more than one. The term “on” is meant to include not only cases in which a certain component is formed directly on top of another component, but also a case in which a third component is interposed between these components.

Hereinafter, a preferred example of a gate shift register and a display device using the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a display device having a gate driver according to the present invention.

Referring to FIG. 2 , the display device according to the present invention includes a display panel 1 , a gate driver 2 , a data driver 3 , and a timing controller 4 .

The display panel 1 includes a plurality of gate lines GL and a plurality of data lines DL that intersect each other, and a plurality of pixels P are provided in the intersection regions of the GL and DL. Each pixel P displays an image according to an image signal (data voltage) supplied from the data line DL in response to the scan pulse G supplied from the gate line GL.

The gate driver 2 is a gate in panel (GIP) type gate driver and is disposed in a non-display area of the display panel 2 . The gate driver 2 includes a gate shift register that supplies the gate output signal Vgout to the plurality of gate lines GL according to the plurality of gate control signals GCS provided from the timing controller 4 . The plurality of gate control signals GCS include a plurality of clock signals CLK1 - 8 having different phases and a gate start signal VST instructing the start of driving of the gate driver 2 . The gate shift register will be described in detail later with reference to FIGS. 3 to 6 .

The data driver 3 converts digital image data RGB input from the timing controller 4 into a data voltage using a reference gamma voltage, and supplies the converted data voltage to a plurality of data lines DL. The data driver 3 is controlled according to a plurality of data control signals DCS provided from the timing controller 4 .

The timing controller 4 aligns image data RGB input from the outside according to the size and resolution of the display panel 1 and supplies it to the data driver 3 . The timing controller 4 uses a plurality of synchronization signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The gate and data control signals GCS and DCS are generated and supplied to the gate driver 2 and the data driver 3 , respectively.

FIG. 3 is a configuration diagram illustrating a gate shift register constituting the gate driver 2 shown in FIG. 2 .

Referring to FIG. 3 , the gate shift register includes a plurality of stages GIP connected to each other, and the plurality of stages GIP includes a plurality of gate lines GL connected to one stage GIP. and a gate output unit 22 that sequentially generates a gate output signal Vgout according to the clock signals CLK1 - 8 applied from the timing controller 4 .

Specifically, the gate driver 2 receives a plurality of clock signals CLK1 - 8 from the timing controller 4 and simultaneously applies at least one output control clock signal QCLK.

The plurality of clock signals CLK1-8 may include eight-phase clock signals that are shifted by a predetermined period and output, that is, first to eighth clock signals CLK1-8.

The output control clock signal QCLK is applied at the level of the gate high voltage VGH. The output control clock signal QCLK may include a first output control clock signal QCLK1 and a second output control clock signal QCLK2 separated into two signals having opposite (or inverted) phases.

In particular, the gate shift register of the present invention applies the gate high voltage VGH to the first node Q provided in each stage GIP by using the output control clock signal QCLK, so that the first node Q is voltage can be maintained stably.

FIG. 4 is a configuration circuit diagram of the first example for the arbitrary stage GIP shown in FIG. 3, and FIG. 5 is a driving waveform diagram of the gate shift register of the present invention.

4 and 5 , the stage GIP includes a node control unit 21 and a gate output unit 22 .

The node controller 21 controls the voltages of the first and second nodes Q and QB in response to the first and second output control clock signals QCLK1-2. To this end, the node controller 21 includes first to fifth transistors T1, T2, T3, T3R, T3N, T4, T5, and T5Q.

The first transistor T1 receives the gate start signal VST as the gate electrode and applies the gate driving voltage VDD to the third node Q′. In addition, the fifth transistor T5 sets the second node QB to the level of the gate-off signal VSS in response to the gate start signal VST.

The second transistor T2 receives the second output control clock signal QCLK2 and transmits it to the second node QB. Here, the second transistor T2 is diode-connected between the supply line of the second output control clock signal QCLK2 and the second node QB.

The fourth transistor T4 has a gate electrode connected to a third node Q′, a first electrode to which the first output control clock signal QCLK1 is applied, and a first electrode connected to the first node Q. It consists of two electrodes. The fourth transistor T4 transfers the first output control clock signal QCLK1 to the first node Q according to the voltage of the third node Q′.

The 3R transistor T3R is turned on according to the reset signal RST to bring the third node Q' to the level of the gate-off signal VSS in every frame, and the 3N transistor T3N is horizontally reset It is turned on according to the signal Vnext1 to bring the third node Q' to the level of the gate-off signal VSS every horizontal period H.

The third transistor T3 is turned on when a voltage is applied to the second node QB to bring the third node Q' to the level of the gate-off signal VSS, and the 5Q transistor T5Q is When a voltage is applied to the third node Q', it is turned on to bring the second node QB to the level of the gate-off signal VSS. The level of the gate-off signal VSS may be a gate low voltage VGL.

The gate output unit 22 outputs the gate output signal Vgout to the gate line GL according to the voltage level of the first node Q and the voltage level of the sixth transistor T6 and the second node QB. Accordingly, a seventh transistor T7 for supplying a gate-off signal VSS to the gate line GL is included. Specifically, the sixth transistor T6 has a gate electrode connected to the first node Q, a first electrode connected to a supply line of the first clock signal CLK1, and a gate line GL connected to and a second electrode. The seventh transistor T7 has a gate electrode connected to the second node QB, a first electrode connected to the gate line GL, and a second electrode connected to the gate-off signal VSS supply line. includes

In another embodiment of the present invention, instead of separately applying the output control clock signal QCLK applied from the timing controller, a 2A transistor operating as an inverter circuit inside the stage GIP of the gate shift register of the gate driver 2 is provided. include more This will be described later with reference to FIG. 5 .

FIG. 6 is a configuration circuit diagram of a second example for an arbitrary stage GIP shown in FIG. 3 .

5 and 6 , the stage GIP includes a node control unit 21 and a gate output unit 22 .

The node controller 21 controls the voltages of the first and second nodes Q and QB in response to the output control clock signal QCLK1. To this end, the node controller 21 includes first to fifth transistors T1, T2, T2A, T3, T3R, T3N, T4, T5, and T5Q.

The first transistor T1 receives the gate start signal VST as the gate electrode and applies the gate driving voltage VDD to the third node Q′. In addition, the fifth transistor T5 sets the second node QB to the level of the gate-off signal VSS in response to the gate start signal VST.

The 2A transistor T2A operates as an inverter in response to the output control clock signal QCLK1 to bring the second node QB to the level of the gate-off signal VSS. The second transistor T2 receives the gate driving voltage VDD and transmits it to the second node QB. Here, the second transistor T2 is connected in a diode form between the supply line of the gate driving voltage VDD and the second node QB. In addition, the second transistor T2 and the second transistor T2A may constitute an inverter circuit.

The fourth transistor T4 has a gate electrode connected to a third node Q′, a first electrode to which the first output control clock signal QCLK1 is applied, and a first electrode connected to the first node Q. It consists of two electrodes. The fourth transistor T4 transfers the first output control clock signal QCLK1 to the first node Q according to the voltage of the third node Q′.

The 3R transistor T3R is turned on according to the reset signal RST to bring the third node Q' to the level of the gate-off signal VSS in every frame, and the 3N transistor T3N is horizontally reset It is turned on according to the signal Vnext1 to bring the third node Q' to the level of the gate-off signal VSS every horizontal period H.

The third transistor T3 is turned on when a voltage is applied to the second node QB to bring the third node Q' to the level of the gate-off signal VSS, and the 5Q transistor T5Q is When a voltage is applied to the third node Q', it is turned on to bring the second node QB to the level of the gate-off signal VSS. The level of the gate-off signal VSS may be a gate low voltage VGL.

The gate output section 22 is the same as in the first embodiment.

The gate output unit 22 outputs a gate output signal Vgout to the gate line GL according to the clock signal CLK1 - 8 applied from the timing controller 4 , and one of the gate shift registers A plurality of gate lines GL are connected to the gate output unit 22 included in the stage GIP. For example, in the embodiment of the present invention, the gate output unit 22 included in one stage GIP is connected to four gate lines GL to form a first node Q generated in one stage GIP. ) and the voltage of the second node QB are shared and output to the plurality of gate lines GL according to the clock signals CLK1 - 8 . In this case, the clock signals CLK1-4 may be one bundle, and the remaining clock signals CLK5-6 may be another bundle. In addition, in the stage GIP shared by the plurality of gate lines GL operating according to the clock signal CLK5-6, the fourth gate output signal Vgout4 operates in place of the gate start signal VST. can

According to the embodiment of the present invention, since a plurality of gate lines GL share and use one stage GIP in the gate driver 2 , the width of the output control clock signal QCLK1-2 applied from the timing controller may be equal to or wider than the four clock signals CLK.

In addition, in the present invention, since the voltage of the first node Q must be applied to both the gate start signal VST and the first output control clock signal QCLK1, it is connected to a plurality of gate lines GL and used as a multi-output. There is no problem such as noise, etc.

Accordingly, the voltage of the second node QB may operate as a periodic signal according to the second output control clock signal QCLK2 or the inverted first output control clock signal QCLK1 . Therefore, it is possible to obtain an effect of reducing deterioration of the seventh transistor that applies the voltage of the second node QB to the gate line GL.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical matters of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

21: node control unit
22: gate output unit

Claims (10)

a plurality of stages selectively connected to lines to which a plurality of clock signals are supplied;
Each of the plurality of stages,
a node controller for controlling voltages of the first and second nodes in response to the output control clock signal; and
a gate output unit that is shared with a plurality of gate lines and selectively outputs a gate output signal to a plurality of shared gate lines according to the plurality of clock signals in response to voltages of the first and second nodes;
The node control unit,
a first transistor turned on according to a gate start signal to apply a gate driving voltage to the third node; and
and a fourth transistor that is turned on according to the voltage of the third node and transfers the output control clock signal to the first node. The method of claim 1,
The node control unit,
a fifth transistor turned on according to the gate start signal to transmit a gate-off signal to the second node;
a fifth Q transistor that is turned on according to the voltage of the third node and transmits the gate-off signal to the second node;
a third transistor turned on according to the voltage of the second node to transmit the gate-off signal to the third node; and
The gate shift register of claim 1, further comprising: a third R transistor that is turned on according to a reset signal to transfer the gate-off signal to the third node. The method of claim 1,
The gate output unit,
at least two or more sixth transistors that are turned on at the voltage of the first node and selectively output the gate output signal according to different clock signals among the plurality of clock signals;
A gate shift register having at least two or more seventh transistors that are turned on by the voltage of the second node to output a gate-off signal. 4. The method of claim 3,
the gate output signal is at a gate high voltage level;
The gate-off signal is a gate-low voltage level of a gate shift register. 5. The method of claim 4,
The voltage of the second node is a periodic signal having a phase opposite to that of the output control clock signal. The method of claim 1,
The node control unit further comprises a second transistor for applying the output control clock signal to the second node,
The output control clock signal is
a first output control clock signal applied to the fourth transistor; and
and a second output control clock signal applied to the second transistor while having a phase opposite to the first output control clock signal. The method of claim 1,
The node control unit,
a second transistor for applying the gate driving voltage to the second node; and
and a second transistor configured to apply a gate-off signal to the second node according to the output control clock signal. a display panel having a plurality of gate lines;
and a gate driver embedded in a non-display area of the display panel to drive the plurality of gate lines;
The display device, wherein the gate driver includes the gate shift register according to any one of claims 1 to 7. 9. The method of claim 8,
The output control clock signal is applied at a gate high voltage level while the gate output signals according to the plurality of clock signals are supplied to the plurality of shared gate lines. delete

Images