KR101244559B1 - Gate driver - Google Patents

Abstract

The present invention relates to a display device, and more particularly to a gate driver for a display device. The gate driver according to the present invention is characterized in that the output node of the shift register for generating a scan signal can be commonly used for a plurality of gate lines in order to reduce the internal area of the gate driver. According to this configuration, the present invention can reduce the built-in area of the gate driver, thereby making it possible to reduce the volume. In addition, the present invention is helpful in pursuing miniaturization and portableness of the product, and furthermore, it is expected that various products may be applied due to the reduction of the interior area.

Gate driver, output node, built-in area

Description

Gate driver {Gate driver}

1 is a block diagram showing a gate driver of the liquid crystal display device of the present invention;

2 is a detailed circuit diagram of a first multi-channel stage of the gate driver according to the first embodiment of the present invention;

3 is a voltage waveform diagram for driving the multi-channel stage shown in FIG.

4 is a detailed circuit diagram illustrating a second multichannel stage of the gate driver according to the second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21: shift register 22: output section

T1 ~ T9: Transistor ST1 ~ STn: Multichannel Stage

The present invention relates to a display device, and more particularly to a gate driver for a display device.

In general, a device for displaying an image by driving pixels arranged in an active matrix form, such as a liquid crystal display device or an organic EL (OLED), has been actively studied.

In particular, the liquid crystal display device is a display device in which a desired image is displayed by individually supplying data signals according to image information to pixels arranged in the form of an active matrix, thereby adjusting the light transmittance of the liquid crystal layer.

Therefore, the liquid crystal display includes a liquid crystal panel in which pixels are arranged in a matrix and a driving circuit for driving the liquid crystal panel. In the liquid crystal panel, gate lines and data lines are arranged to cross each other, and pixel regions are divided by the gate lines and the data lines. Each of the pixel regions includes a thin film transistor, which is a switching element, and a pixel electrode connected to the thin film transistor. In this case, the gate terminal of the thin film transistor is connected to the gate line, the source terminal is connected to the data line, and the drain terminal is connected to the pixel electrode.

The driving circuit includes a gate driver for supplying a scan signal (eg, a gate signal) to each of the gate lines, and a data driver for supplying a video signal to the data lines.

The gate driver supplies a scan signal to each of the gate lines to sequentially select pixels on the liquid crystal panel by one line. The data driver supplies a video signal to the data lines whenever gate lines are sequentially selected. Accordingly, the liquid crystal display adjusts the light transmittance of the liquid crystal layer by an electric field applied between the pixel electrode and the common electrode according to the video signal applied for each pixel, thereby displaying an image.

On the other hand, most of the recently developed electronic devices are pursuing miniaturization and portable. Therefore, it is essential to reduce the gate driver built-in area, which is a driving circuit of the liquid crystal display device.

In the conventional gate driver, a plurality of stages are provided to supply a scan signal to each gate line. Looking at the structure of each stage, an input terminal to which a set, reset signal is input, one node associated with an output, two output bar nodes provided with dual, and a VDD connected thereto It consists of odd / even power supply. Each node consists of a thin film transistor (TFT), which plays a basic role, and a number of additional transistors (TFT) for longevity. Therefore, about 20 thin film transistors (TFTs) are required for each stage of the conventional gate driver.

The conventional gate driver configured as described above has nodes configured independently for each stage, and each node has a plurality of thin film transistors independently. Therefore, the conventional gate driver has a problem that it is difficult to achieve a low internal area due to a large number of stages and a large number of thin film transistors configured for each stage.

Accordingly, an object of the present invention is to provide a gate driver capable of reducing the current consumption and reducing the built-in area while improving the current consumption and improving compatibility with the basic panel.

According to an aspect of the present invention, a gate driver includes a plurality of multi-channel stages that sequentially output at least two shift signals, and each multi-channel stage is the lowest of an upper multi-channel stage. A latch unit controlling first and second nodes in response to a scan signal from a channel and a scan signal from a top channel of a lower multi-channel stage; Pull-up driving switches configured to output a shifted scan signal through at least two channels in response to at least two clock signals of the signal on the first node and at least three clock signals; And pull-down transistors for supplying a first supply voltage on the at least two channels in response to the signal on the second node.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a gate driver of a liquid crystal display of the present invention.

As shown in FIG. 1, the gate driver of the present invention includes a plurality of multichannel stages ST1 to STn. The multi-channel stages ST1 to STn are connected to the start pulse SP input line and connected to each of three clock signal input lines among the four-phase clock signal C1 to C4 input lines. As shown in FIG. 3, the four-phase clock signals C1 to C4 are sequentially supplied in a phase delayed form by one clock period. Using three clock signals among these clock signals C1 to C4, each of the multi-channel stages ST1 to STn shifts the start pulse SP by one clock period and uses the shifted start pulse as a scan signal. Output At this time, the number of scan signals output from one multi-channel stage is plural (three). The scan signal output from each of the multi-channel stages ST1 to STn is supplied to the corresponding gate lines GL1 to GLn, and one of the plurality of scan signals is supplied as a start pulse to the next stage. do.

Accordingly, the plurality of multichannel stages are configured such that three stages share one output node Q and two output bar nodes QB / O and QB / E in order to reduce the internal area of the gate driver. As shown in FIG. 2, the plurality of multi-channel stages are cascaded to generate a plurality of scan signals to be supplied to the gate lines GL by shifting start pulses.

Specifically, the start pulse SP is input to the first multichannel stage ST1, and the previous stages of the multichannel stages ST1 to STn-1 are input to the second to nth multichannel stages ST2 to STn. One scan signal of the plurality of scan signals is input. As shown in FIG. 3, the plurality of multichannel stages ST1 to STn receive three clock signals among the first to fourth clock signals C1 to C4 which are sequentially delayed in phase. The multi-channel stages ST1 to STn sequentially shift the start pulse SP to generate a plurality of scan signals having the start pulse SP sequentially by using the input three clock signals.

2 is a diagram illustrating a detailed circuit configuration of a first multi-channel stage of the gate driver according to the first embodiment of the present invention.

As described above, the gate driver of the liquid crystal display includes a plurality of multichannel stages ST1 to STn for generating scan signals Vg1 to Vgn.

In the following description, the first multi-channel stage ST1 among the multi-channel stages ST1 to STn will be described. The remaining multichannel stages ST2 to STn operate in the same manner as the first multichannel stage ST1. However, the third scan signal of the first multichannel stage ST1 is supplied as a start pulse of the next second multichannel stage ST2, and the third scan signal output from the second multichannel stage ST2 is supplied. It is supplied as a start pulse of the next third multichannel stage ST3. Each of the remaining multichannel stages ST4 to STn also receives one scan signal from the previous multichannel stage as a start pulse and generates a scan signal having a predetermined high logic pulse shifted in phase by one clock. .

Referring to FIG. 2, the first multichannel stage ST1 controls the non-inverting node Q in response to the next scan signal of the start pulse SP and the next multichannel stage ST2, and starts the start pulse ( A shift register 21 for controlling a first inverted node QBO and a second inverted node QBE in response to an SP and a voltage of the non-inverted node Q; The first clock signal C1, the second clock signal C2, and the third clock signal C3 are input, and the voltage of the non-inverting node Q, the first inverting node QBO, and the second inverting node ( And an output unit 22 for sequentially generating an output in response to the voltages of the QBE.

The output unit 22 is configured to generate three scan signals, which are connected between the non-inverting node Q of the shift register 21 and the first clock signal C1 supply line to generate the first scan signal. The transistor T1 is included. The first scan signal generated by the transformer T1 is supplied to the gate line GL1.

The output unit 22 includes a transistor T2 connected to the non-inverting node Q of the shift register 21 and the second clock signal C2 supply line to generate a second scan signal. The second scan signal generated by the transistor T2 is supplied to the gate line GL2.

The output unit 22 includes a transistor T3 connected to the non-inverting node Q of the shift register 21 and the third clock signal C3 supply line to generate a third scan signal. The third scan signal generated by the transistor T3 is supplied to the gate line GL3. The third scan signal generated by the multi-channel stage ST1 is provided as a start pulse of the next multi-channel stage ST2.

Pull-down transistors T4 and T5 are connected between the inversion node QB / O and the inversion node QB / E of the shift register 21. When the output of the multi-channel stage configured in the next stage of the pull-down transistors T4 and T5 is high, one of the transistors is turned on by the power supplies VDD1 and VDD2 so that the first scan signal Mutes the residual signal to ground.

Also, pull-down transistors T6 and T7 are connected between the inversion node QB / O and the inversion node QB / E of the shift register 21. When the output of the multi-channel stage configured in the next stage of the pull-down transistors T6 and T7 is high, one of the transistors is turned on by the power supplies VDD1 and VDD2 so as to generate the second scan signal. Mutes the residual signal to ground.

In addition, pull-down transistors T8 and T9 are connected between the inversion node QB / O and the inversion node QB / E of the shift register 21. When the output of the multi-channel stage configured in the next stage of the pull-down transistors T8 and T9 is high, any one of the transistors is turned on by the power supplies VDD1 and VDD2 so that the third scan signal Mutes the residual signal to ground.

3 is a diagram illustrating a voltage waveform for driving the multi-channel stage shown in FIG. 2. The first supply voltage VDD1 and the second supply voltage VDD2 are inverted at a predetermined period (for example, every n frames). Accordingly, the first supply voltage VDD1 is maintained at high logic in an odd frame and is kept low logic in an even frame, and the second supply voltage VDD2 is maintained at low logic in an odd frame and maintained at high logic in an even frame. .

The other start pulses SP and the first and second clock signals C1 and C2 are approximately 20V in high logic and -5V in low logic. For example, when the inversion period is one frame, in the odd frame, the first supply voltage VDD1 has a high logic voltage of 20V and the second supply voltage VDD2 has a low logic voltage of −10V. . The first supply voltage VDD1 may have a low logic voltage of −10 V and the second supply voltage VDD2 may have a high logic voltage of 20 V in an even-numbered frame.

The operation of the stage will be described using these waveforms.

While the first period t1, that is, the high logic start pulse SP is applied, the high logic signal is charged to the non-inverting node Q by the start pulse SP. At this time, supply of the first and second supply voltages VDD1 and VDD2 to be supplied to the first inverted node QB / O and the second inverted node QB / E is cut off. Therefore, during the first period t1, the non-inverting node Q is charged with a voltage that is a high logic signal, and the first inverting node QBO and the second inverting node QBE correspond to a low logic signal. Voltage appears. As a result, the first multi-channel stage ST1 is set by the start pulse SP.

Since the start pulse SP becomes low logic while the second period t2, that is, the high logic first clock signal C1, is applied, the first clock signal C1 becomes the source of the first transistor T1. It is input to the terminal. Accordingly, since the non-inverting node Q has a floating state, the previous high logic voltage is maintained. Similarly, the first inverted node QBO and the second inverted node QBE also remain in their previous states. In this case, a bootstrapping phenomenon occurs due to the influence of the internal capacitor Cgs formed between the gate terminal and the source terminal of the first transistor T1, so that the high logic signal on the non-inverting node Q is 40V. It will be boosted to a degree. The first transistor T1 responding to the high logic signal on the boosted non-inverting terminal Q is output to the first gate line GL1 as a first scan signal without attenuation of the first clock signal C1 of 20V. To be. During the third period t3, that is, while the high logic second clock signal C2 is applied, the second transistor T2 is the second gate line as the second scan signal without attenuating the second clock signal C2. Output to (GL2). In addition, while the fourth period t4, that is, the high logic third clock signal C3 is applied, the third transistor T3 is a third gate signal as a third scan signal without attenuating the third clock signal C3. Output to line GL3.

Next, a fifth period t5, that is, a low logic first clock signal C1, a second clock signal C2, and a third clock signal C3 are applied and high logic from the next multichannel stage ST2. While the fourth scan signal (not shown) is outputted, the first multi-channel stage ST1 is reset. The high logic fourth scan signal charges the gate line connected to the output terminal of the second multichannel stage ST2 and is also input to the shift register 21 of the first multichannel stage ST1. Accordingly, the high logic signal (i.e., the high potential voltage) on the non-inverting node Q is discharged by the high logic scan signal from the next multi-channel stage ST2 so that the low logic signal is transmitted to the non-inverting node Q. Make it appear. When the non-inverting node Q is converted to low logic, the first supply voltage VDD1 is supplied to the inverting node QB / O, and the second supply voltage VDD2 is the second inverting node QB / E. Is supplied. In other words, a high logic signal is generated at any one of the first and second inverted nodes QB / O and QB / E, while a low logic signal is generated at the non-inverted node Q. Accordingly, the high logic first scan signal on the gate line GL1 is discharged via any one of the fourth and fifth transistors T4 and T5 and reset to have a low logic. This state continues until the start pulse SP is applied again in the next frame. In addition, the high logic second scan signal on the gate line GL2 is discharged through any one of the sixth and seventh transistors T6 and T7 to have a low logic, and the high logic on the gate line GL3. The third scan signal is discharged via any one of the eighth and ninth transistors T8 and T9 and reset to have a low logic. This state continues until the start pulse SP is applied again in the next frame.

In this case, the first to fourth sections t1 to t4 may be defined as active sections, and the sections may be defined as inactive sections until the next frame including the fifth section t5.

The first supply voltage VDD1 and the second supply voltage VDD2 may be inverted at predetermined intervals. For example, when the inversion period is one frame, the first supply voltage VDD1 maintains high logic and the second supply voltage VDD2 maintains low state during the odd frame, and the first supply voltage during the even frame. VDD1) maintains low logic and the second supply voltage VDD2 maintains high logic.

In this case, the high logic first supply voltage VDD1 is supplied to the first inversion node QB / O and the low logic second supply voltage is supplied to the second inversion node QB / E in the inactive period of the odd frame. VDD2) is supplied, a low logic first supply voltage VDD1 is supplied to the first inversion node QB / O, and a high logic second is supplied to the second inversion node QB / E in an inactive period of an even frame. Supply voltage VDD2 is supplied.

As described above, when operated every frame, the first inverted node QB / O and the second inverted node QB / E are alternately supplied with a high logic voltage and a low logic voltage. Therefore, since the high logic voltage and the low logic voltage are alternately supplied to the first inversion node QB / O and the second inversion node QB / E, pull-down transistors T4 and T5 (T6 and T7). By preventing the accumulation of stress voltage at the gate terminals of (T8, T9), degradation can be fundamentally blocked. Accordingly, the pull-down transistors T4 and T5 (T6 and T7) (T8 and T9) respectively connected to the first inversion node QB / O and the second inversion node QB / E operate stably. As a result, image quality is improved and long life is possible.

4 is a diagram illustrating a detailed circuit configuration of the first multi-channel stage of the gate driver according to another embodiment of the present invention.

The first multi-channel stage ST1 controls the non-inverting node Q in response to the next scan signal of the start pulse SP and the next multi-channel stage ST2, and starts the start pulse SP and the non-inverting. A shift register 21 for controlling the first inversion node QBO and the second inversion node QBE in response to the voltage of the node Q; The first clock signal C1, the second clock signal C2, and the third clock signal C3 are input, and the voltage of the non-inverting node Q, the first inverting node QBO, and the second inverting node ( And an output unit 22 which sequentially generates an output in response to the voltages of QBE).

The output unit 22 is configured to generate three scan signals, which are connected between the non-inverting node Q of the shift register 21 and the first clock signal C1 supply line to generate the first scan signal. The transistor T1 is included. The first scan signal generated by the transistor T1 is supplied to the gate line GL1.

While the high logic start pulse SP is applied to the shift register 21, the non-inverting node Q is charged with the high logic signal by the start pulse SP. At this time, the supply of the first supply voltage VDD1 to be supplied to the first inverted node QB / O is cut off. Therefore, during the first period t1, the non-inverted node Q is a high logic signal. After the charging, the voltage corresponding to the low logic signal appears on the inversion node QBO, and finally, the first multi-channel stage ST1 is set by the start pulse SP.

Then, while the high logic first clock signal C1 is applied, the start pulse SP becomes low logic, so that the first clock signal C1 is input to the source terminal of the first transistor T1. Accordingly, since the non-inverting node Q has a floating state, the previous high logic voltage is maintained. Similarly, the inverted node QBO also remains in its previous state. In this case, a bootstrapping phenomenon occurs due to the influence of the internal capacitor Cgs formed between the gate terminal and the source terminal of the first transistor T1, so that the high logic signal on the non-inverting node Q is 40V. It will be boosted to a degree. The first transistor T1 responding to the high logic signal on the boosted non-inverting terminal Q is output to the first gate line GL1 as a first scan signal without attenuation of the first clock signal C1 of 20V. To be.

In the above operation, the transistor T2 connected to the non-inverting node Q of the shift register 21 and the second clock signal C2 supply line and generating the second scan signal attenuates the second clock signal. It is supplied to the gate line GL2 as a second scan signal without any change.

In addition, the transistor T3 connected to the non-inverting node Q of the shift register 21 and the third clock signal C3 supply line and generating a third scan signal may perform a third scan without attenuating the third clock signal. The signal is supplied to the gate line GL3 as a signal. The third scan signal generated by the multi-channel stage ST1 is provided as a start pulse of the next multi-channel stage ST2.

On the other hand, the transistor T4 is connected to the inverting node QB / O of the shift register 21. The transistor T4 is turned on by the supply power supply VDD1 when the output of the multi-channel stage configured in the next stage is high to mute the residual signal of the first scan signal to ground.

That is, when the fourth scan signal of the next stage multi-channel stage ST2 becomes high, the non-inverting node Q of the shift register 21 is turned low and the inverting node QB / O is supplied at the same time. The power supply VDD1 is charged to be in a high state.

That is, the low logic first clock signal C1, the second clock signal C2, and the third clock signal C3 are applied, and a high logic fourth scan signal from the next multi-channel stage ST2 (not shown). Is output, the first multi-channel stage ST1 is reset. The high logic fourth scan signal charges the gate line connected to the output terminal of the second multichannel stage ST2 and is also input to the shift register 21 of the first multichannel stage ST1. Accordingly, the high logic signal (i.e., the high potential voltage) on the non-inverting node Q is discharged by the high logic scan signal from the next multi-channel stage ST2 so that the low logic signal is transmitted to the non-inverting node Q. Make it appear. When the non-inverting node Q is switched to low logic, the first supply voltage VDD1 is supplied to the inverting node QB / O. In other words, while the inverted node QB / O shows a high logic signal, the non-inverted node Q generates a low logic signal. Accordingly, the high logic first scan signal on the gate line GL1 is discharged via the fourth transistor T4 and reset to have low logic. This state continues until the start pulse SP is applied again in the next frame.

In addition, the high logic second scan signal on the gate line GL2 is discharged via the transistor T5 connected to the inverting node QB / O of the shift register 21 to have low logic. The high logic third scan signal on the gate line GL3 is discharged through the transistor T6 connected to the inversion node QB / O of the shift register 21, and reset to have a low logic. . This state continues until the start pulse SP is applied again in the next frame.

That is, in another embodiment of the present invention shown in FIG. 4, only one supply power source VDD1 and one transistor group T4, R5, and R6 operated by the supply power source VDD1 are connected to each other, thereby providing a gate. It is operated to mute the scan power remaining in the line.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to the case where the internal area is reduced in the gate driver for the liquid crystal display. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

The gate driver according to the present invention described above is characterized in that the output node of the shift register for generating a scan signal can be commonly used for a plurality of gate lines in order to reduce the internal area of the gate driver. According to this feature, the present invention can reduce the built-in area of the gate driver, thereby making it possible to reduce the volume. Therefore, the present invention is helpful in pursuing miniaturization and portability of the product, and furthermore, it can be expected that various products can be applied due to the reduction of the interior area.

Claims (5)

A plurality of multi-channel stages for sequentially outputting at least two or more shift signals, each multi-channel stage, In response to the first scan signal from the lowest channel of the two or more channels of the multichannel stage in the front stage and the second scan signal from the highest channel of the two or more channels of the multichannel stage in the rear stage, the first, second and third nodes are selected. A latch unit for controlling; Pull-up driving switches for outputting at least two scan signals shifted through at least two channels in response to at least two clock signals of the signal on the first node and at least three clock signals; And And a pull-down transistor connected between the second node, the third node, and the pull-up driving switch, and configured to discharge the two or more scan signals in response to the second scan signal. delete The method according to claim 1, And apply a first supply voltage and a second supply voltage to each of the second and third nodes in response to the second scan signal. The method of claim 3, Each of the first and second supply voltages is alternately supplied to each of the second and third nodes. The method of claim 1, The pull-down transistor is a pair of gate drivers.

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