JP2010049721A - Shift register and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register which saves power consumption, reduce circuit area and prevent the deterioration of image quality, and to provide a display. <P>SOLUTION: The shift register includes a plurality of stages of reset/set type flip-flops (RS-FF) 34. A start signal STV or a shift register output pulse of a previous stage is input as a set signal S to the RS-FF circuit, and a shift register output pulse of a next stage is input as a reset signal R. In this case, as a reset signal R of the RS-FF circuit of the last stage, a set signal S of the flip-flop of the first stage (start signal STV) is input. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a shift register including a reset-set type flip-flop (RS-FF), and a display device using the shift register.

Conventionally, a reset / set flip-flop (RS-FF) has been widely used as a flip-flop constituting a shift register.
The reset / set flip-flop is set when the set signal input to the set terminal becomes active, and the output signal output from the output terminal becomes H level. Even when the set signal becomes inactive, the output state is maintained and the reset signal input to the reset terminal is activated to be reset, and the output signal becomes L level. After that, even if the reset signal becomes inactive, the state is kept until the next set signal becomes active.

As a shift register (RS-FF type shift register) having such a reset-set type flip-flop, the reset signal input to the reset terminal of the i-th flip-flop is supplied to the (i + k × M) -th stage (k ≧ 1). , M ≧ 2) using a shift register output pulse is known (for example, see Patent Document 1).
As described above, when the subsequent shift register output pulse is used as the reset signal, the set state is maintained without resetting the final flip-flop, and the shift register output pulse is continuously output.

In order to avoid this, the shift register described in Patent Document 1 is provided with a dummy stage, and the shift register output pulse of the dummy stage is input to the reset terminal of the flip-flop of the final stage. The output pulse of the own stage is inputted to the reset terminal of the flip-flop of the dummy stage.
Japanese Patent No. 3588020

However, in the shift register described in Patent Document 1, since it is essential to provide a dummy stage, the drive frequency increases with the increase of the drive line, the power consumption increases, and the circuit area increases. There is a drawback.
In addition, when the output pulse of the own stage is input to the reset terminal of the flip-flop of the final stage without providing the dummy stage, it is not possible to sufficiently secure the ON period of the output pulse in the final stage. For this reason, the higher the definition, the shorter the active period, and there is a risk of image quality degradation due to a reduction in data writing time.

  Accordingly, an object of the present invention is to provide a shift register and a display device that can realize low power consumption, circuit area reduction, and prevention of image quality deterioration.

  In order to solve the above-described problem, a shift register according to the present invention includes N (N is an integer of 2 or more) stages of reset set flip-flops, and is provided for each flip-flop. A flip-flop set terminal from the second stage to the N-th stage, comprising a switch that is controlled to open and close based on the output and outputs an output pulse having a pulse width corresponding to the duty ratio of the clock signal The output pulse of the previous stage is input to the flip-flop reset terminal from the first stage to the (N−1) th stage, and the output pulse of the subsequent stage is input to the first stage. A start signal is commonly input to the set terminal of the flip-flop of the eye and the reset terminal of the flip-flop of the Nth stage.

  As described above, when the output pulse of the subsequent stage is used as the reset signal, the start signal is input as the reset signal to the final stage flip-flop, so that the final stage flip-flop can be reset without providing a dummy stage. Therefore, it is possible to prevent an increase in circuit area and power consumption due to the provision of the dummy stage. Further, by using the start signal as the reset signal, it is possible to sufficiently secure the ON period of the output pulse in the final stage.

In the shift register according to the present invention, in the above description, the clock signal is a positive logic signal, and the start signal is input to the flip-flop after the output pulse of the Nth stage is output. In the meantime, the clock signal is fixed at a low level.
As a result, it is possible to prevent unnecessary pulse output from the flip-flop using the start signal as the reset signal, and to perform pulse output similar to the other stages.

Furthermore, in the shift register according to the present invention, in the above, the clock signal is a negative logic signal, and from when the output pulse of the Nth stage is output until the start signal is input to the flip-flop. In the meantime, the clock signal is fixed at a high level.
As a result, it is possible to prevent unnecessary pulse output from the flip-flop using the start signal as the reset signal, and to perform pulse output similar to the other stages.

In the shift register according to the present invention, the output of the flip-flop from the first stage to the (N−k) stage (k is an integer of 1 or more) is connected to the output after the k stage of the own stage. A pulse is input and the start signal is input to reset terminals of flip-flops from the (N- (k-1)) stage to the N stage.
Thereby, for example, when the output pulse of the next stage is used as the reset signal, the flip-flop one stage before the final stage can be normally reset.

Further, in the shift register according to the present invention, in the above description, the clock signals are K types (K is an integer of 2 or more) of different phases, and the K types of clock signals are respectively (K− 1) It is configured to be inputted every other piece, and the k is set to be equal to or less than the K.
Thereby, the ON period of a switch can be adjusted appropriately. That is, when the clock signal is K types of signals, setting k to 1 or more and K or less can prevent output pulses from being output a plurality of times during the ON period of the switch.

  The display device according to the present invention further includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. In the display device, a scanning line driving circuit that supplies a selection voltage to the scanning line in a predetermined order, and an image signal corresponding to the gradation of the pixel for a pixel corresponding to the selected scanning line And a data line driving circuit supplied via the data line, and at least one of the scanning line driving circuit and the data line driving circuit includes any one of the shift registers described above.

  As a result, a display device including a drive circuit that achieves low power consumption and circuit area reduction can be obtained. In addition, by providing the driver circuit with a shift register that sufficiently secures the ON period of the output pulse in the final stage, a sufficient data writing time can be secured and image quality deterioration can be prevented.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration of a display device 10 according to the present embodiment.
The display device 10 is a liquid crystal display device including a liquid crystal panel using, for example, an active matrix thin film transistor (TFT), and the display device 10 includes a display region 100 as shown in FIG. Around the display area 100, a control circuit 20, a scanning line driving circuit 30, and a data line driving circuit 40 are arranged.

  Although not specifically shown, the liquid crystal panel has a configuration in which the element substrate and the counter substrate are bonded together with a certain gap so that the electrode formation surfaces face each other, and the liquid crystal is sealed in the gap. ing. On the element substrate of the liquid crystal panel, switching elements of pixels to be described later are formed by a common process, and the scanning line driving circuit 30 and the data line driving circuit 40 are formed on the element substrate by SOG (System On Glass) technology. Is formed. Various control signals are supplied to the scanning line driving circuit 30 and the data line driving circuit 40 from the control circuit 20 mounted on the element substrate by the COG technique or the like.

  In the display area 100 of the liquid crystal panel, a plurality (N) of scanning lines 112 are provided so as to extend in the row (X) direction, and a plurality (M) of data lines 114 are arranged in a column (Y). The scanning lines 112 are provided so as to extend in the direction and to be electrically insulated from each other. The pixels 110 are arranged corresponding to the intersections between the scanning lines 112 and the data lines 114, respectively.

Next, a detailed configuration of the pixel 110 will be described.
FIG. 2 is a diagram illustrating the configuration of the pixel 110. Here, a configuration for a total of two pixels corresponding to the intersection of n rows, (n + 1) rows adjacent thereto, and m columns is shown.
Note that n is a symbol that generally indicates a row in which the pixels 110 are arranged, and m is a symbol that generally indicates a column in which the pixels 110 are arranged.

  As shown in FIG. 2, each pixel 110 has an n-channel thin film transistor (hereinafter referred to as TFT) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, and a storage capacitor 130. . Since each pixel 110 has the same configuration, the pixel 110 of n rows and m columns is connected to the n-th scanning line 112 in the pixel 110 of the n rows and m columns. On the other hand, the source electrode is connected to the data line 114 in the m-th column, and the drain electrode is connected to the pixel electrode which is one end of the pixel capacitor 120.

The other end of the pixel capacitor 120 is connected to the common electrode 108. As shown in FIG. 1, the common electrode 108 is common to all the pixels 110, and a common signal Vcom is supplied from the control circuit 20.
The pixel capacitor 120 has a configuration in which a liquid crystal that is a kind of dielectric is sandwiched between the pixel electrode and the common electrode 108, and holds a differential voltage between the pixel electrode and the common electrode 108. In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage.

  Returning to FIG. 1 again, the control circuit 20 outputs the vertical start signal STV and the vertical clock signals CKV1 and CKV2 to the scanning line driving circuit 30 and the horizontal start signal to the data line driving circuit 40 as the control signals. STH and horizontal clock signals CKH1 and CKH2 are output. The vertical start signal STV is a signal for driving the scanning line driving circuit 30, and the horizontal start signal STH is a signal for driving the data line driving circuit 40.

Here, the vertical clock signals CKV1 and CKV2 are positive logic signals, and have a phase such that their H level periods do not overlap each other. The vertical clock signals CKV1 and CKV2 are set such that the H level period is shorter than the L level period. The same applies to the horizontal clock signals CKH1 and CKH2.
The scanning line driving circuit 30 includes a vertical shift register and a plurality of switching circuits provided for each scanning line 112. Each switching circuit is configured to apply a driving voltage to the corresponding scanning line 112 by being driven in accordance with a driving signal from the vertical shift register.

  The data line driving circuit 40 includes a horizontal shift register and a plurality of sample and hold circuits provided for each data line 114. The data line driving circuit 40 has a function as a sampling circuit that samples image data to be displayed on each pixel from the video signal Da input from the control circuit 20.

The basic operation of the display device 10 configured as described above is as follows.
The vertical shift register of the scanning line driving circuit 30 outputs a driving signal to the switching circuit corresponding to the uppermost scanning line 112 in the display area 100 in accordance with the vertical start signal STV input from the control circuit 20.
The vertical shift register also changes from the uppermost scanning line 112 to the lowermost scanning line 112 in the display area 100 in synchronization with the rising / falling of the vertical clock signals CKV1 and CKV2 input from the control circuit 20 as well. The switching circuit that outputs the drive signal is sequentially shifted. The switching circuit to which the driving signal is input applies a driving voltage to the corresponding scanning line 112.

On the other hand, the horizontal shift register of the data line driving circuit 40 receives a driving signal from the sample and hold circuit corresponding to the leftmost data line 114 in the display area 100 in response to the horizontal start signal STH input from the control circuit 20. Is output.
Similarly, the horizontal shift register synchronizes with the rising / falling of the horizontal clock signals CKH1 and CKH2 input from the control circuit 20 in the same manner as the leftmost data line 114 to the rightmost data line 114 in the display area 100. The sample and hold circuit for outputting the drive signal is sequentially shifted toward the above. The sample hold circuit to which the drive signal is input from the horizontal shift register samples the image data to be displayed on the pixel from the video signal and holds the image data for an appropriate period. The image data held in the sample hold circuit is supplied to the corresponding data line 114 at an appropriate timing.

Next, the configuration of the vertical shift register of the scanning line driving circuit 30 will be described.
FIG. 3 is a circuit diagram schematically showing the configuration of the vertical shift register.
As shown in FIG. 3, the vertical shift register includes N stages corresponding to the number of scanning lines 112, and two types of vertical clock signals CKV1 and CKV2 having different phases are alternately input to the respective stages. Here, the vertical clock signal CKV1 is input to the odd-numbered stages, and the vertical clock signal CKV2 is input to the even-numbered stages.

Each stage shift register includes a switch 31, an n-type transistor 32, and a flip-flop unit 33. The flip-flop unit 33 includes a reset / set type flip-flop (RS-FF) 34 and inverters 35 and 36.
The RS-FF 34 outputs the output signals Q and / Q (Q bar) that become active when the output pulse (vertical start signal STV in the first stage) of the previous shift register is input as the set signal S. Here, the output signal Q is a positive logic signal and the output signal / Q is a negative logic signal.

These output signals Q and / Q are input to a switch 31 provided corresponding to each RS-FF 34. The output signal / Q is also input to the n-type transistor 32.
Furthermore, the RS-FF 34 is configured such that the output pulse of the shift register at the next stage (the vertical start signal STV at the final stage) is input as the reset signal R. By inputting this reset signal R, Inactive output signals Q and / Q are output.

FIG. 4 is a diagram illustrating an example of a circuit configuration of the RS-FF 34.
As shown in FIG. 4, the RS-FF 34 includes set / reset n-type transistors Tr1 to Tr4, scan direction switching n-type transistors Tr5 to Tr8, an output node stabilization n-type transistor Tr9, and an inverter. 37 and 38 are provided.

  The gates of the transistors Tr1 and Tr2 are connected to the set terminal, and the set signal S is applied. The gates of the transistors Tr3 and Tr4 are connected to the reset terminal, and the reset signal R is applied. Further, the scan direction switching signal UD is applied to the gates of the transistors Tr5 and Tr6, the scan direction switching signal XUD is applied to the gates of the transistors Tr7 and Tr8, and the initialization signal RST (panel initialization) is applied to the gate of the transistor Tr9. Signal) is applied.

  The RS-FF 34 shown in FIG. 4 sets the UD = H level and XUD = L level so that the scan direction of the shift pulse is positive scan (left to right in FIG. 3), UD = L level, and XUD = H level. As a result, the scan direction of the shift pulse can be switched from reverse scan (right to left in FIG. 3). When the scan direction of the shift pulse is reverse scan, the set terminal in FIG. 4 becomes the reset terminal, and the reset terminal becomes the set terminal. That is, the gates of the transistors Tr3 and Tr4 are connected to the set terminal, the set signal S is applied, the gates of the transistors Tr1 and Tr2 are connected to the reset terminal, and the reset signal R is applied.

In addition, the RS-FF 34 has a configuration in which, for example, by setting RST = H level immediately after power-on, the transistor Tr9 can be turned on and the node of the latch unit can be fixed at the L level.
With such a configuration, the RS-FF 34 is set when the set signal S input to the set terminal becomes active, and outputs an output signal Q that becomes H level from the output terminal. Even when the set signal S becomes inactive, the output state is maintained, and the reset signal R input to the reset terminal is reset by being activated, and the output signal Q that is at the L level is output. . Thereafter, even if the reset signal R becomes inactive, the state is kept until the next set signal S becomes active.

Here, although the case where the RS-FF 34 has the circuit configuration shown in FIG. 4 has been described, any reset-set flip-flop that performs the above-described operation may be used, and the present invention is not limited to this.
The switch 31 is turned on while the output signals Q and / Q are in an active state (Q = H level, / Q = L level). During this on period, the vertical clock signal CKV1 or CKV2 is passed through the inverters 35 and 36. And output as an output pulse Gate. That is, during the ON period of the switch 31, an output pulse Gate having the same pulse width as that of the clock signal CKV1 or CKV2 is output in synchronization with the clock signal CKV1 or CKV2.

  On the other hand, during the period when the output signals Q and / Q are in an inactive state (Q = L level, / Q = H level) and the switch 31 is off, the n-type transistor 32 to which the output signal / Q is input. Is in a conductive state, and therefore, an output pulse Gate that is L level is output.

Next, the operation of the vertical shift register of the scanning line driving circuit 30 will be described.
FIG. 5 is a timing chart showing the operation of the vertical shift register.
In FIG. 5, UD = H level and XUD = L level are input to the RS-FF 34, and the scan direction of the shift pulse is a positive scan (left to right in FIG. 3). Note that when the scan direction of the shift pulse is reverse scan, the operation is reversed left and right, which will be described in parentheses.

As shown in FIG. 5, when the vertical start signal STV becomes H level at time t1, the RS-FF 34 in the first stage (N stage in the case of reverse scanning) is set, and the output signal Q1 is output from the RS-FF 34. = H level is output. As a result, the first-stage switch 31 (N-stage in the case of reverse scanning) is turned on.
Therefore, when the vertical clock signal CKV1 (CKV2 in the case of reverse scan) becomes H level at time t2, the output pulse Gate1 (GateN in the case of reverse scan) is synchronized with the vertical clock signal CKV1 (CKV2 in the case of reverse scan). ) = H level is output. At this time, the output pulse Gate1 (Gate N in the case of reverse scan) of the first stage (N stage in the case of reverse scan) is the second stage (N-1 stage in the case of reverse scan). Since the set signal S is input to the set terminal of the RS-FF 34, the RS-FF 34 in the second stage (N-1 stage in the case of reverse scanning) is set at the time t2, and is output from the RS-FF 34. The signal Q2 (QN-1 in the case of reverse scanning) = H level is output. As a result, the switch 31 at the second stage (N-1 stage in the case of reverse scanning) is turned on.

  Thereafter, when the vertical clock signal CKV2 (CKV1 in the case of reverse scan) becomes H level at time t3, the output pulse Gate2 (GateN in the case of reverse scan) is synchronized with the vertical clock signal CKV2 (CKV1 in the case of reverse scan). -1) = H level is output. At this time, the output pulse Gate2 (Gate N-1 in the case of reverse scan) of the second stage (N-1 stage in the case of reverse scan) is the RS of the first stage (N stage in the case of reverse scan). Since the reset signal R is input to the reset terminal of the FF 34, the RS-FF 34 in the first stage (the N stage in the case of reverse scanning) is reset at time t3, and the output output from the RS-FF 34 The signal Q1 (QN in the case of reverse scanning) becomes L level. As a result, the first-stage switch 31 (N-stage in the case of reverse scanning) is turned off.

Similarly, the RS-FF 34 in the second stage (N-1 stage in the case of reverse scanning) enters the reset state at time t4 when the vertical clock signal CKV1 (CKV2 in the case of reverse scanning) = H level. At t4, the output signal Q2 (QN-1 in the case of reverse scanning) changes to the L level.
This operation is repeated up to the shift register at the (N-1) th stage (second stage in the case of reverse scanning). That is, in the (N-1) -th stage (second stage in the case of reverse scanning), the output pulse GateN-2 ((N-2) stage (third stage in the case of reverse scanning) of the preceding stage is output. In the case of the reverse scan, the RS-FF 34 is set at the time t5 when the Gate (third stage) becomes the H level, and the output signal QN-1 (Q2 in the case of the reverse scan) = H level is output from the RS-FF 34. . When the vertical clock signal CKV1 (CKV2 in the case of reverse scanning) = H level at time t6, the output pulse GateN-1 (Gate2 in the case of reverse scanning) = H level is output. After that, at time t7, when the output pulse QN (Q1 in the case of reverse scan) from the N-th stage of the subsequent stage (first stage in the case of reverse scan) (last stage) shifts to the H level, (N− 1) The RS-FF 34 at the second stage (second stage in the case of reverse scanning) is in a reset state, and the output signal QN-1 (Q2 in the case of reverse scanning) becomes L level.

  At the final stage, RS− is output at time t6 when the output pulse GateN−1 (Gate2 in the case of reverse scan) of the previous (N−1) stage (second stage in the case of reverse scan) shift register becomes H level. The FF 34 is set, and the output signal QN (Q1 in the case of reverse scanning) = H level is output from the RS-FF 34. When the vertical clock signal CKV2 (CKV1 in the case of reverse scanning) = H level at time t7, the output pulse GateN (Gate1 in the case of reverse scanning) = H level is output. Thereafter, the output signal QN (Q1 in the case of reverse scanning) = H level is maintained until the reset signal R is input.

In the present embodiment, the vertical start signal STV is used as the reset signal R input to the reset terminal of the RS-FF 34 at the final stage. Accordingly, the RS-FF 34 in the final stage is reset at time t8 when the vertical start signal STV = H level, and the output signal QN (Q1 in the case of reverse scanning) changes to the L level.
In this manner, the output signal QN (Q1 in the case of reverse scanning) is at the H level during the period from time t6 to time t8, and the switch 31 at the final stage is kept on during that time. Since the output pulse GateN (Gate1 in the case of reverse scanning) corresponding to the vertical clock signal CKV2 (CKV1 in the case of reverse scanning) continues to be output while the last-stage switch 31 is in the ON state, In this embodiment, in order to eliminate unnecessary pulse output, a period (vertical period) from when the output pulse GateN (Gate1 in the case of reverse scanning) is output at time t7 until the next vertical start signal STV becomes H level. During the blanking period), the vertical clock signals CKV1 and CKV2 are fixed to the L level.

  Here, it is assumed that the vertical clock signals CKV1 and CKV2 are fixed to the L level by setting on the IC side. An AND circuit or the like is provided on the panel side, and the vertical clock signals CKV1 and CKV2 are ANDed with the enable signal that becomes “0” in the vertical blanking period, thereby obtaining the vertical clock signals CKV1 and CKV1 in the vertical blanking period. CKV2 can also be fixed at the L level. However, in this case, it is necessary to provide an AND circuit, and the circuit area increases accordingly. Therefore, it is desirable to set the levels of the vertical clock signals CKV1 and CKV2 on the IC side.

  By the way, in the RS-FF type shift register, it is common to use the output pulse of the next stage or the second stage shift register as the reset signal R. In such a configuration, the last stage or the last stage 1 is used. The reset signal of the previous RS-FF circuit cannot be input, and the set state is maintained. In order to avoid this, a dummy stage is provided, and the output pulse of the shift register at the dummy stage is input to the reset terminal of the flip-flop of the last stage or one stage before the last stage.

However, in this case, the drive line is increased by providing the dummy stage, and accordingly, the drive frequency is increased and the power consumption is increased. Furthermore, there is a drawback that the circuit area increases.
Further, when the shift register output pulse of the own stage is input to the reset terminal of the final stage flip-flop without providing the dummy stage, the on period of the final stage output pulse cannot be sufficiently secured. For this reason, the higher the definition, the shorter the active period and the deterioration of image quality due to the reduction in data writing time.

  On the other hand, in the present embodiment, the vertical start signal which is the set signal S of the RS-FF circuit in the first stage (N stage in the case of reverse scanning) is used as the reset signal R of the RS-FF circuit in the final stage. Since STV is used, the final stage can be normally reset without providing a dummy stage, and a sufficient ON period of the output pulse of the final stage can be secured. At this time, since the vertical clock signals CKV1 and CKV2 are fixed to the L level during the blanking period, a normal output pulse GateN (Gate1 in the case of reverse scanning) can be output from the final stage.

Next, the configuration of the horizontal shift register of the data line driving circuit 40 in FIG. 1 will be described.
The horizontal shift register has the same configuration as the vertical shift register shown in FIG. However, in the horizontal shift register, instead of the vertical clock signals CKV1 and CKV2, two types of horizontal clock signals CKH1 and CKH2 having different phases are alternately input to each stage. The horizontal start signal STH is input to the set terminal of the first-stage RS-FF circuit and the reset terminal of the final-stage RS-FF circuit in place of the vertical start signal STV.

In the horizontal blanking period, the horizontal clock signals CKH1 and CKH2 are fixed to the L level.
With this configuration, the horizontal shift register can sequentially output output pulses to the sample and hold circuit in synchronization with the horizontal clock signals CKH1 and CKH2 by receiving the horizontal start signal STH.

  At this time, the RS-FF circuit at the final stage of the horizontal shift register can be normally reset by the horizontal start signal STH. Further, by fixing the horizontal clock signals CKH1 and CKH2 to the L level during the horizontal blanking period, it is possible to prevent unnecessary pulse output from being performed from the final stage.

  As described above, in the first embodiment, since the set signal input to the first-stage RS-FF is used as the reset signal input to the final-stage RS-FF, a circuit and a control signal are newly provided. And the RS-FF at the final stage can be normally reset. Therefore, there is no need to provide a dummy stage as in the prior art, and an increase in power consumption and an increase in circuit area can be prevented. In addition, by using the start signal as the reset signal for the RS-FF in the final stage, it is possible to sufficiently secure the ON period of the output pulse in the final stage, and to ensure the data writing period to prevent image quality deterioration. it can.

Further, since the clock signal is fixed at the L level during the blanking period, unnecessary pulse output can be prevented from being performed from the final stage, and a shift register that performs proper operation can be obtained.
Also, every other clock signal is input to the RS-FF every other time, and the output pulse after one stage is input as a reset signal for the RS-FF of the own stage, so a switch provided for each RS-FF It is possible to prevent the output pulse from being output a plurality of times during the ON period. Therefore, even when this shift register is used in a scanning line driver circuit, it can be operated normally.

  Further, since the two types of clock signals are positive logic signals and set so that the periods of the H level do not overlap each other, it is possible to prevent output pulses output from adjacent stages from overlapping each other.

Next, a second embodiment of the present invention will be described.
In the second embodiment, the clock signal is configured by negative logic in the first embodiment described above.
That is, the vertical clock signals CKV1 and CKV2 are negative logic signals and have a phase such that their L level periods do not overlap. The vertical clock signals CKV1 and CKV2 are set such that the L level period is shorter than the H level period.

FIG. 6 is a circuit diagram schematically showing the configuration of the vertical shift register in the second embodiment.
As shown in FIG. 6, the flip-flop unit 33 has a configuration in which the inverter 36 in the flip-flop unit 33 of FIG. 3 is deleted. With such a configuration, the shift register at each stage inverts the clock signal CKV1 or CKV2 by the inverter 35 and outputs it as the output pulse Gate when the switch 31 is in the ON state.

  In this embodiment, a p-type transistor 32 ′ is provided instead of the n-type transistor 32, and an output signal Q is input to the gate of the p-type transistor 32 ′. As a result, when Q = L level, the p-type transistor 32 ′ becomes conductive, and an output pulse Gate that is L level is output via the inverter 35.

FIG. 7 is a timing chart showing the operation of the vertical shift register in the second embodiment.
As shown in FIG. 7, since the vertical clock signals CKV1 and CKV2 are configured with negative logic, the vertical clock signals CKV1 and CKV2 are fixed to the H level in the vertical blanking period.

As a result, the same effects as those of the first embodiment described above can be obtained.
In the second embodiment, the case where the vertical clock signals CKV1 and CKV2 are configured with negative logic has been described. However, the horizontal clock signals CKH1 and CKH2 can also be configured with negative logic. In this case, the horizontal clock signals CKH1 and CKH2 may be fixed at the H level during the horizontal blanking period.

In each of the embodiments described above, the case where the clock signal is fixed at the L level (H level in the case of negative logic) during the blanking period has been described. However, there is a display problem even if a pulse is output during the blanking period. If not, the clock signal need not be fixed.
In each of the above embodiments, the case where the output pulse of the next-stage shift register is input as the reset signal R of the RS-FF circuit has been described. However, in the case of a shift register that does not switch the scan direction of the shift pulse. Output pulses that are two or more stages later can be input as the reset signal R. For example, when the output pulse of the next-stage shift register is input, the reset signal R of the RS-FF circuit one stage before the last stage (N-1 stage) is the start signal or the last stage (N stages). Eye) output pulse may be input.

Further, although cases have been described with the above embodiments where two types of clock signals are input to the shift register, three or more types of clock signals can also be input.
Here, when the clock signals are K types (K is an integer of 2 or more) and the K types of clock signals are input to the RS-FF circuit every (K−1) units, RS If the shift register output pulse after k (1 ≦ k ≦ K) stages is input as the reset signal R of the FF circuit, the output pulse is output a plurality of times during the ON period of the switch provided for each RS-FF. The on-period can be adjusted to prevent output. In this case, as the reset signal R for the RS-FF circuit from the (N- (k-1)) stage to the (N-1) stage, a start signal or an output pulse one stage after the own stage is input. You just have to do it.

  Furthermore, in each of the above embodiments, the case where the present invention is applied to a display device using liquid crystal has been described. However, a display device using an electro-optical material other than liquid crystal, for example, organic EL or plasma discharge is used. It can also be applied to a display device.

It is a block diagram which shows the structure of the display apparatus in this embodiment. It is a figure which shows the structure of a pixel. It is a circuit diagram which shows roughly the structure of a shift register. It is a figure which shows an example of the circuit structure of RS-FF. 6 is a timing chart illustrating an operation of the shift register according to the first embodiment. It is a circuit diagram which shows roughly the structure of the shift register in 2nd Embodiment. 10 is a timing chart illustrating an operation of the shift register according to the second embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 20 ... Control circuit, 30 ... Scan line drive circuit, 31 ... Switch, 32, 32 '... N-type transistor, 33 ... Flip-flop part, 34 ... RS-type flip-flop (RS-FF), 35, 36, inverter, 40, data line driving circuit, 100, display region, 108, common electrode, 110, pixel, 112, scanning line, 114, data line, 116, TFT, 118, pixel electrode, 120, pixel capacitor, 130 ... accumulation capacity

Claims (6)

N (N is an integer greater than or equal to 2) stages of reset set type flip-flops, provided for each flip-flop, and controlled to open and close based on the output of each stage flip-flop, and according to the duty ratio of the clock signal And a switch for outputting an output pulse having a pulse width,
The output pulse one stage before the first stage is input to the set terminals of the flip-flops from the second stage to the N-th stage, and the reset terminals of the flip-flops from the first stage to the (N−1) stage are input, A shift register, wherein the output pulse after the first stage is inputted, and a start signal is inputted in common to the set terminal of the first flip-flop and the reset terminal of the N-stage flip-flop.   The clock signal is a positive logic signal, and the clock signal is fixed to a low level from when the output pulse of the Nth stage is output until the start signal is input to the flip-flop. The shift register according to claim 1.   The clock signal is a negative logic signal, and the clock signal is fixed to a high level from when the output pulse of the Nth stage is output until the start signal is input to the flip-flop. The shift register according to claim 1.   The output pulse after the k-th stage of its own stage is inputted to the reset terminals of flip-flops from the first stage to the (N−k) -th stage (k is an integer of 1 or more), and (N− (k−1) 4. The shift register according to claim 1, wherein the start signal is input to reset terminals of flip-flops from the stage to the N-th stage.   The clock signals are K types (K is an integer of 2 or more) of different phases, and the K types of clock signals are input to the flip-flops every (K−1) times. 5. The shift register according to claim 4, wherein k is set to be equal to or less than K. A display device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines,
A scanning line driving circuit for supplying a selection voltage to the scanning lines in a predetermined order;
A data line driving circuit that supplies an image signal corresponding to the gradation of the pixel to the pixel corresponding to the selected scanning line via the data line;
6. A display device, wherein at least one of the scanning line driving circuit and the data line driving circuit includes the shift register according to any one of claims 1 to 5.

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