CN111489676A - Array substrate, driving method and display device - Google Patents

Array substrate, driving method and display device Download PDF

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Publication number
CN111489676A
CN111489676A CN202010340149.XA CN202010340149A CN111489676A CN 111489676 A CN111489676 A CN 111489676A CN 202010340149 A CN202010340149 A CN 202010340149A CN 111489676 A CN111489676 A CN 111489676A
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China
Prior art keywords
shift register
stage
signal end
electrically connected
driving circuit
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CN202010340149.XA
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CN111489676B (en
Inventor
张振宇
郑皓亮
肖丽
刘冬妮
陈昊
陈亮
赵蛟
玄明花
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses an array substrate, a driving method and a display device, which comprise a driving circuit, wherein the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of the last stage of shift register is electrically connected with an input signal end of the first stage of shift register through the control circuit. When the driving circuit starts to work, only a frame trigger signal needs to be loaded to the driving circuit once through the frame trigger signal end, when the last stage of shift register of the driving circuit outputs a signal, the signal output by the last stage of shift register can be provided to the input signal end of the first stage of shift register, so that the driving circuit works circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal to the driving circuit at a high frequency.

Description

Array substrate, driving method and display device
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a driving method and a display device.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. In the Gate Driver on Array (GOA) technology, a Thin Film Transistor (TFT) Gate switch circuit is integrated on an Array substrate of a display panel to form a scan Driver for the display panel. Usually, a driving chip is required to provide a trigger signal when a gate switch circuit works, but the refresh rate of the trigger signal provided by the conventional driving chip has an upper limit, and the requirement of an array substrate requiring a high refresh rate cannot be met.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a driving method and a display device, which can realize high-refresh-rate scanning driving.
Therefore, an embodiment of the present invention provides an array substrate, including a driving circuit; the driving circuit comprises a control circuit and a plurality of cascaded shift registers;
the input signal end of the first stage shift register is electrically connected with the frame trigger signal end, and in each two adjacent stages of shift registers, the input signal end of the next stage shift register is electrically connected with the output signal end of the previous stage shift register, and the output signal end of the next stage shift register is electrically connected with the reset signal end of the previous stage shift register;
the output signal end of the last stage of shift register is electrically connected with the input signal end of the first stage of shift register through the control circuit; the control circuit is used for transmitting the signal of the output signal end of the last stage of shift register to the input signal end of the first stage of shift register.
Optionally, the control circuit includes a switching transistor, an output signal terminal of the last stage of shift register is electrically connected to a first pole and a control pole of the switching transistor, and an input signal terminal of the first stage of shift register is electrically connected to a second pole of the switching transistor.
Optionally, the control circuit comprises a cascade of a plurality of the first virtual shift registers;
in each two adjacent stages of the first virtual shift registers, the input signal end of the next stage of the first virtual shift register is electrically connected with the output signal end of the previous stage of the first virtual shift register, and the output signal end of the next stage of the first virtual shift register is electrically connected with the reset signal end of the previous stage of the first virtual shift register;
the output signal end of the last stage of shift register is electrically connected with the input signal end of the first stage of the first virtual shift register, and the reset signal end of the last stage of shift register is electrically connected with the output signal end of the first stage of the first virtual shift register; and the input signal end of the first-stage shift register is electrically connected with the output signal end of the first virtual shift register of any stage.
Optionally, the driving circuit further includes a plurality of cascaded second dummy shift registers connected between the input signal terminal of the first stage shift register and the frame trigger signal terminal;
the input signal end of the first-stage second virtual shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of second virtual shift registers, the input signal end of the next stage of second virtual shift register is electrically connected with the output signal end of the previous stage of second virtual shift register, and the output signal end of the next stage of second virtual shift register is electrically connected with the reset signal end of the previous stage of second virtual shift register;
the output signal end of the last stage of the second virtual shift register is electrically connected with the input signal end of the first stage of the shift register, and the reset signal end of the last stage of the second virtual shift register is electrically connected with the output signal end of the first stage of the shift register.
Optionally, the cyclic reset signal terminals of all the shift registers are electrically connected to the reset signal terminal; all the shift registers are configured to be reset according to a signal of the reset signal terminal.
Alternatively, the circuit configuration of all the shift registers is the same.
Optionally, the array substrate further includes a plurality of gate lines; the driving circuit is electrically connected with the grid lines; in the cascaded shift registers, each shift register is electrically connected with a grid line correspondingly.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises any one of the array substrates.
Based on the same inventive concept, the embodiment of the invention further provides a driving method of any one of the array substrates, which comprises a plurality of driving periods; each of the drive cycles comprises a plurality of successive scan phases;
in the first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first-stage shift register in a driving circuit;
in each scanning stage, the driving circuit inputs scanning signals to the plurality of grid lines which are electrically connected line by line in sequence.
Optionally, between every two adjacent driving cycles, a reset phase is further included;
and in the reset stage, loading a reset signal to the cyclic reset signal ends of all the shift registers in the driving circuit through the reset signal end so as to reset all the shift registers.
The invention has the following beneficial effects:
the array substrate, the driving method and the display device provided by the embodiment of the invention comprise a driving circuit, wherein the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of the last stage of shift register is electrically connected with an input signal end of the first stage of shift register through the control circuit. When the driving circuit starts to work, only a frame trigger signal needs to be loaded to the driving circuit once through the frame trigger signal end, when the last stage of shift register of the driving circuit outputs a signal, the signal output by the last stage of shift register can be provided to the input signal end of the first stage of shift register, so that the driving circuit works circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal to the driving circuit at a high frequency.
Drawings
Fig. 1 is a schematic diagram of a driving circuit in an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of an array substrate according to an embodiment of the invention;
fig. 3 is a schematic diagram of a driving circuit in another array substrate according to an embodiment of the invention;
fig. 4 is a schematic diagram of a driving circuit in another array substrate according to an embodiment of the invention;
fig. 5 is a schematic diagram of a driving circuit in another array substrate according to an embodiment of the invention;
fig. 6 is a schematic diagram of a driving circuit in another array substrate according to an embodiment of the invention;
fig. 7 is a signal timing diagram of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
An array substrate provided in an embodiment of the present invention is shown in fig. 1, and includes: a drive circuit; the driving circuit comprises a control circuit 10, a plurality of cascaded shift registers: SR (1), SR (2) … … SR (N-1), SR (N) (N shift registers, 1 < N);
an input signal end IN of a first-stage shift register SR (1) is electrically connected with a frame trigger signal end STV, and IN each two adjacent stages of shift registers, an input signal end IN of a next-stage shift register is electrically connected with an output signal end Out of a previous-stage shift register, and an output signal end Out of the next-stage shift register is electrically connected with a reset signal end Rst of the previous-stage shift register;
an output signal end Out of the last stage of shift register SR (N) is electrically connected with an input signal end IN of the first stage of shift register through a control circuit 10; the control circuit 10 is configured to transmit a signal at the output signal terminal Out of the last stage shift register SR (n) to the input signal terminal IN of the first stage shift register SR (1).
IN the array substrate provided by the embodiment of the present invention, the control circuit 10 is disposed IN the driving circuit, and the output signal terminal Out of the last stage shift register SR (n) is electrically connected to the input signal terminal IN of the first stage shift register SR (1) through the control circuit 10. When the driving circuit starts to work, only a frame trigger signal needs to be loaded to the driving circuit once through the frame trigger signal end STV, when the driving circuit outputs a signal from the last stage shift register SR (n), the signal output from the last stage shift register SR (n) can be provided to the input signal end IN of the first stage shift register SR (1), so that the driving circuit can work circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading a frame trigger signal to the driving circuit at a high frequency.
In a specific implementation, as shown in fig. 2, the array substrate may include: the liquid crystal display device comprises a substrate base plate and a plurality of pixel units positioned on the substrate base plate. In general, a pixel unit includes a plurality of sub-pixels P, each of which includes a pixel circuit and an organic light emitting diode electrically connected to the pixel circuit. The pixel circuits in one row of the sub-pixels P are electrically connected with one grid line G, the pixel circuits in one column of the sub-pixels P are electrically connected with one data line D, and the pixel circuits in the sub-pixels enable the organic light-emitting diodes to emit light under the control of the scanning signals of the electrically connected grid line G and the signals of the electrically connected data line D. The driving circuit 100 in the array substrate provided by the embodiment of the invention can be used as a gate driving circuit for providing a scanning signal to the gate line G. The driving circuit may be integrated on the substrate by using a Gate Driver on Array (GOA) technology to form a scan Driver for the Gate lines.
In specific implementation, in the embodiment of the present invention, as shown in fig. 1, the array substrate may include a plurality of gate lines: g (1), G (2) … … G (N-1), G (N); the driving circuit is electrically connected with the grid lines; in a plurality of cascaded shift registers, each shift register is correspondingly and electrically connected with one grid line.
In an implementation, the driving circuit is used for sequentially providing scanning signals to the electrically connected gate lines. Specifically, in a plurality of cascaded shift registers, an output signal end Out of each shift register is electrically connected to a gate line correspondingly: an output signal end Out of the first-stage shift register SR (1) is electrically connected with the grid line G (1), an output signal end Out of the second-stage shift register SR (2) is electrically connected with the grid line G (2), and an output signal end Out of the last-stage shift register SR (N) is electrically connected with the grid line G (N). The scanning signals are sequentially output to the corresponding grid lines from the first-stage shift register SR (1) to the last-stage shift register SR (N) through the output signal end Out, namely, the driving circuit finishes signal output of one frame, and can drive a display picture of one frame.
IN practical implementation, IN the embodiment of the present invention, as shown IN fig. 3, the control circuit 10 may include a switching transistor T, an output signal terminal Out of the last stage shift register SR (n) is electrically connected to a first pole and a control pole of the switching transistor T, and an input signal terminal IN of the first stage shift register SR (1) is electrically connected to a second pole of the switching transistor T.
IN specific implementation, when the switch transistor T is turned on, the signal output by the last shift register SR (n) is directly provided to the input signal terminal IN of the first shift register SR (1) through the switch transistor T, so that the first shift register SR (1) continues to output the signal. That is, when the signals are sequentially output from the first stage shift register SR (1) to the last stage shift register SR (n) in the driving circuit, that is, after the driving circuit finishes outputting the scanning signal of one frame, the scanning signal of the next frame can be immediately output, and no buffering time is required between the signal outputs of two frames, so that the seamless connection between the display frames of two adjacent frames can be realized.
In a specific implementation, the first pole of the switching transistor T is electrically connected to the control pole, forming a diode structure, so that the signal can only be transmitted from the first pole to the second pole of the switching transistor T. When the frame trigger signal is loaded through the frame trigger signal terminal STV, the frame trigger signal is not transmitted to the output signal terminal Out of the last stage shift register through the switching transistor T.
Specifically, in the array substrate provided in the embodiment of the present invention, the switch Transistor may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), which is not limited herein. Further, depending on the type of each switching transistor and the signal of the control electrode of the switching transistor, the control electrode of the switching transistor may be used as the gate, the first electrode of the switching transistor may be used as the source, and the second electrode may be used as the drain, or the first electrode of the switching transistor may be used as the drain and the second electrode may be used as the source, which is not specifically distinguished herein.
In practical implementation, in the embodiment of the present invention, as shown in fig. 4, the control circuit 10 may also include a plurality of cascaded first dummy shift registers: DS (1), DS (2) … …;
IN each two adjacent stages of first virtual shift registers, an input signal end IN of a next stage of first virtual shift register is electrically connected with an output signal end Out of a previous stage of first virtual shift register, and the output signal end Out of the next stage of first virtual shift register is electrically connected with a reset signal end Rst of the previous stage of first virtual shift register;
an output signal end Out of the last-stage shift register SR (N) is electrically connected with an input signal end IN of the first-stage first virtual shift register DS (1), and a reset signal end Rst of the last-stage shift register SR (N) is electrically connected with an output signal end Out of the first-stage first virtual shift register DS (1); an input signal terminal IN of the first-stage shift register SR (1) is electrically connected with an output signal terminal Out of any one of the first virtual shift registers.
IN a specific implementation, IN the driving circuit shown IN fig. 4, the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the output signal terminal Out of the first stage first dummy shift register DS (1), but is not limited thereto. In practical applications, the number of the first dummy shift registers may be determined according to practical requirements, and is not limited herein. The input signal terminal IN of the first stage shift register SR (1) may be electrically connected to the output signal terminal Out of which stage of the first virtual shift register, which may also be designed according to actual needs, and is not limited herein.
IN specific implementation, when the output signal of the output signal terminal Out of the last stage of the shift register sr (n) is provided to the input signal terminal IN of the first stage of the first dummy shift register DS (1), the first stage of the first dummy shift register is triggered to operate, so that the output signal terminal Out of the first stage of the first dummy shift register outputs a signal. And the signal output by the output signal terminal Out of the first-stage first dummy shift register is provided to the input signal terminal of the first-stage shift register to trigger the first-stage shift register to work, so that the scanning signal output of the next frame can be automatically started. Therefore, the buffering time can be set between the output of the scanning signals of two frames, and the display effect of the display pictures of two adjacent frames can be improved.
IN specific implementation, the control circuit 10 includes a plurality of cascaded first virtual shift registers, and when the input signal terminal IN of the first stage shift register SR (1) is electrically connected to the second stage first virtual shift register or a first virtual shift register behind the second stage first virtual shift register, the first virtual shift register also needs cascaded output signals after the output signal terminal Out of the last stage shift register SR (n) outputs signals, and when the first virtual shift register electrically connected to the first stage shift register outputs signals, the input signal terminal of the first stage shift register will input signals. Therefore, after the output signal terminal Out of the last stage shift register SR (n) outputs a signal, the input signal terminal IN of the first stage shift register SR (1) inputs a signal after waiting for the buffering time, and the buffering time can be adjusted by adjusting the number of the first dummy shift registers electrically connected between the output signal terminal Out of the last stage shift register SR (n) and the input signal terminal IN of the first stage shift register SR (1).
IN specific implementation, the output signal terminal Out of the first dummy shift register is not electrically connected to the gate line, and when the frame trigger signal is loaded through the frame trigger signal terminal STV, the frame trigger signal is transmitted to the output signal terminal Out of the first dummy shift register electrically connected to the input signal terminal IN of the first stage shift register SR (1), but the display is not affected.
IN specific implementation, IN the embodiment of the present invention, the driving circuit may further include a plurality of second dummy shift registers connected IN cascade between the input signal terminal IN of the first stage shift register and the frame trigger signal terminal STV;
an input signal end IN of the first-stage second virtual shift register is electrically connected with a frame trigger signal end STV;
IN each two adjacent stages of second virtual shift registers, an input signal end IN of a next stage of second virtual shift register is electrically connected with an output signal end Out of a previous stage of second virtual shift register, and the output signal end Out of the next stage of second virtual shift register is electrically connected with a reset signal end Rst of the previous stage of second virtual shift register;
an output signal end Out of the last-stage second virtual shift register is electrically connected with an input signal end IN of the first-stage shift register, and a reset signal end Rst of the last-stage second virtual shift register is electrically connected with an output signal end Out of the first-stage shift register.
IN a specific implementation, as shown IN fig. 5, the second dummy shift register D connected between the input signal terminal IN of the first stage shift register and the frame trigger signal terminal STV may include only one. Of course, in practical applications, the number of the second dummy shift registers may be determined according to practical requirements, and is not limited herein.
IN specific implementation, when the control circuit 10 transmits the signal at the output signal terminal Out of the last stage of shift register to the input signal terminal IN of the first stage of shift register, the second dummy shift register is set to avoid transmitting the signal to the frame trigger signal terminal STV.
In practical implementation, in the embodiment of the present invention, as shown in fig. 3 and fig. 6, all the shift registers, including the cascaded shift registers, the first dummy shift register, and the second dummy shift register, have the cyclic reset signal end CR; these cyclic reset signal terminals CR may be all electrically connected to the reset signal terminal TR; all shift registers are configured to be reset according to a signal of the reset signal terminal TR.
In specific implementation, when the driving circuit operates, the reset signal terminal TR loads the reset signal to all the cyclic reset signal terminals Rst, so that all the shift registers can be reset, that is, all the shift registers can stop operating.
In practical implementation, in the embodiment of the present invention, all the shift registers, including the cascaded shift registers, the first dummy shift register, and the second dummy shift register, may have the same circuit structure. Specifically, the circuit structures of all shift registers may be substantially the same as those in the prior art, and are not described herein again. Other essential components of the shift registers are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention.
Based on the same inventive concept, the embodiment of the present invention further provides a driving method of any one of the above array substrates provided by the embodiments of the present invention, including a plurality of driving cycles; each drive cycle comprising a plurality of successive scan phases;
in a first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first-stage shift register in a driving circuit;
in each scanning stage, the driving circuit inputs scanning signals to the electrically connected gate lines line by line in sequence.
In specific implementation, in the embodiment of the present invention, between every two adjacent driving cycles, a reset phase is further included;
in the reset stage, the cyclic reset signal ends of all the shift registers in the driving circuit are loaded with reset signals through the reset signal ends, so that all the shift registers are reset.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The following describes the operation process of the array substrate provided by the embodiment of the present invention with reference to the signal timing diagram shown in fig. 7 by taking the structure of the array substrate shown in fig. 3 as an example. Specifically, the driving period T1, the reset phase R, and the driving period T2 in fig. 7 are selected. The driving period T1 includes a first scanning phase T1 and a second scanning phase T2.
IN the first scanning phase t1, the input signal terminal IN of the first stage shift register SR (1) is loaded with the frame trigger signal through the frame trigger signal terminal STV. After receiving the frame trigger signal, the first stage shift register SR (1) shifts to output a scan signal, and supplies the scan signal to the gate line G (1) and the second stage shift register SR (2). After receiving the scan signal provided by the first stage shift register SR (1), the second stage shift register SR (2) shifts and outputs the scan signal, and provides the scan signal to the gate line G (2) and the third stage shift register SR (3). IN the adjacent two stages of shift registers, the previous stage shift register provides a scanning signal to the corresponding grid line and the input signal end IN of the next stage shift register, and the next stage shift register shifts and outputs the scanning signal after receiving the scanning signal. After receiving the scanning signal, the last stage of shift register SR (n) shifts and outputs the scanning signal to the gate line g (n) and the first electrode of the switching transistor T, and the switching transistor T provides the scanning signal to the input signal terminal IN of the first stage of shift register SR (1).
In the second scan stage t2, the first shift register SR (1) receives the scan signal outputted from the last shift register SR (n), and then shifts and outputs the scan signal. The subsequent operation process may be substantially the same as the first scanning stage t1, and will not be described herein.
In the reset phase R, all the shift registers can be reset by applying a reset signal to all the cyclic reset signal terminals Rst through the reset signal terminal TR, and all the shift registers stop outputting signals.
In the driving period T2, the driving period T2 includes a first scanning stage T1 and at least one second scanning stage T2, and the working process thereof may be substantially the same as the first scanning stage T1 and the second scanning stage T2 in the driving period T1, which is not described herein again.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the array substrate provided by the invention. The specific implementation of the method can be found in the implementation process of the array substrate, and the same parts are not described again. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The array substrate, the driving method and the display device provided by the embodiment of the invention comprise a driving circuit, wherein the driving circuit comprises a control circuit and a plurality of cascaded shift registers, and an output signal end of the last stage of shift register is electrically connected with an input signal end of the first stage of shift register through the control circuit. When the driving circuit starts to work, only a frame trigger signal needs to be loaded to the driving circuit once through the frame trigger signal end, when the last stage of shift register of the driving circuit outputs a signal, the signal output by the last stage of shift register can be provided to the input signal end of the first stage of shift register, so that the driving circuit works circularly, and the requirement that the driving circuit works at a high refresh rate can be met without loading the frame trigger signal to the driving circuit at a high frequency.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. The array substrate is characterized by comprising a driving circuit; the driving circuit comprises a control circuit and a plurality of cascaded shift registers;
the input signal end of the first stage shift register is electrically connected with the frame trigger signal end, and in each two adjacent stages of shift registers, the input signal end of the next stage shift register is electrically connected with the output signal end of the previous stage shift register, and the output signal end of the next stage shift register is electrically connected with the reset signal end of the previous stage shift register;
the output signal end of the last stage of shift register is electrically connected with the input signal end of the first stage of shift register through the control circuit; the control circuit is used for transmitting the signal of the output signal end of the last stage of shift register to the input signal end of the first stage of shift register.
2. The array substrate of claim 1, wherein the control circuit comprises a switching transistor, an output signal terminal of the last stage shift register is electrically connected to a first pole and a control pole of the switching transistor, and an input signal terminal of the first stage shift register is electrically connected to a second pole of the switching transistor.
3. The array substrate of claim 1, wherein the control circuit comprises a cascade of a plurality of the first dummy shift registers;
in each two adjacent stages of the first virtual shift registers, the input signal end of the next stage of the first virtual shift register is electrically connected with the output signal end of the previous stage of the first virtual shift register, and the output signal end of the next stage of the first virtual shift register is electrically connected with the reset signal end of the previous stage of the first virtual shift register;
the output signal end of the last stage of shift register is electrically connected with the input signal end of the first stage of the first virtual shift register, and the reset signal end of the last stage of shift register is electrically connected with the output signal end of the first stage of the first virtual shift register; and the input signal end of the first-stage shift register is electrically connected with the output signal end of the first virtual shift register of any stage.
4. The array substrate of claim 1, wherein the driving circuit further comprises a plurality of second dummy shift registers connected in cascade between an input signal terminal of the first stage shift register and the frame trigger signal terminal;
the input signal end of the first-stage second virtual shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of second virtual shift registers, the input signal end of the next stage of second virtual shift register is electrically connected with the output signal end of the previous stage of second virtual shift register, and the output signal end of the next stage of second virtual shift register is electrically connected with the reset signal end of the previous stage of second virtual shift register;
the output signal end of the last stage of the second virtual shift register is electrically connected with the input signal end of the first stage of the shift register, and the reset signal end of the last stage of the second virtual shift register is electrically connected with the output signal end of the first stage of the shift register.
5. The array substrate of any one of claims 1-4, wherein the cyclic reset signal terminals of all the shift registers are electrically connected to the reset signal terminal; all the shift registers are configured to be reset according to a signal of the reset signal terminal.
6. The array substrate of any one of claims 1-4, wherein the circuit structure of all the shift registers is the same.
7. The array substrate of any one of claims 1-4, wherein the array substrate further comprises a plurality of gate lines; the driving circuit is electrically connected with the grid lines; in the cascaded shift registers, each shift register is electrically connected with a grid line correspondingly.
8. A display device comprising the array substrate according to any one of claims 1 to 7.
9. A driving method of the array substrate according to any one of claims 1 to 7, comprising a plurality of driving periods; each of the drive cycles comprises a plurality of successive scan phases;
in the first scanning stage, loading a frame trigger signal to a frame trigger signal end electrically connected with a first-stage shift register in a driving circuit;
in each scanning stage, the driving circuit inputs scanning signals to the plurality of grid lines which are electrically connected line by line in sequence.
10. The driving method according to claim 9, further comprising, between each adjacent two of the driving periods, a reset phase;
and in the reset stage, loading a reset signal to the cyclic reset signal ends of all the shift registers in the driving circuit through the reset signal end so as to reset all the shift registers.
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