CN101477836A

CN101477836A - Shift register

Info

Publication number: CN101477836A
Application number: CNA200810181436XA
Authority: CN
Inventors: 金洪在
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2007-12-31
Filing date: 2008-11-13
Publication date: 2009-07-08
Anticipated expiration: 2028-11-13
Also published as: JP2009163862A; CN101477836B; KR20090073966A; KR101568249B1; JP5140570B2

Abstract

A shift register includes a plurality of scan stages to output scan pulses to a plurality of gate lines, a first dummy stage to output a first dummy scan pulse to a first of the plurality of scan stages, and a second dummy stage to output a second dummy scan pulse to a last of the plurality of scan stages.

Description

Shift register

Technical field

The present invention relates to a kind of shift register, more particularly, the present invention relates to a kind of shift register that can change the output order of level.

Background technology

The application requires the right of priority of korean patent application No.10-2007-0141546 that submitted on Dec 31st, 2007 and the korean patent application No.10-2008-0061604 that submitted on June 27th, 2008, this sentences the mode of quoting as proof and incorporates its full content into, just as having carried out complete elaboration at this.

Usually, liquid crystal display is configured to utilize the transmittance of electric field adjustment liquid crystal with display image.For this reason, liquid crystal display comprises the liquid crystal panel and the driving circuit that drives this liquid crystal panel that has with the pixel region of cells arranged in matrix.

In liquid crystal panel, many select liness and many data lines are arranged to intersected with each other, and pixel region lays respectively at intersecting in the zone that is limited by select lines and data line.The pixel electrode and the public electrode that electric field are applied to each pixel region are formed in this liquid crystal panel.Each pixel electrode is connected to a corresponding data line via source terminal and the drain terminal as the thin film transistor (TFT) (TFT) of switching device.Scanning impulse by being applied to its gate terminal via a corresponding select lines is this TFT conducting, thereby loads the data-signal from this corresponding data line in pixel electrode.

This driving circuit comprises: gate driver is used to drive select lines; Data driver is used for driving data lines; Timing controller is used to provide the control signal of controlling this gate driver and data driver; And power supply, be used for providing the various driving voltages that will use at this liquid crystal display.This gate driver provides scanning impulse to drive the liquid crystal cells in this liquid crystal panel by line ground order to the select lines order.Here, this gate driver comprises shift register, with order output scanning pulse as described above.

Conventional shift register comprises a plurality of levels with the pulse of permanent order output scanning.These the level output scanning pulses in one direction, promptly according to from top on earth the level the pulse of order output scanning.That is to say that this shift register is output scanning pulse in one direction only.Based on this reason, when using in the liquid crystal indicator of this conventional shift register in various models, can produce many problems.

Summary of the invention

Therefore, the present invention relates to a kind of shift register, it can overcome one or more problems of bringing because of the limitation of correlation technique and shortcoming basically.

The object of the present invention is to provide a kind of shift register of output order that can the gated sweep pulse.

Supplementary features of the present invention and advantage will obtain explanation in the following description, and by describing, partial content will be conspicuous, perhaps can understand by practice of the present invention.By the structure that particularly points out in written instructions, claim and the accompanying drawing, can realize and obtain above-mentioned target and other advantages of the present invention.

In order to realize these targets and other advantages, according to purpose of the present invention, as the description of concrete and broad sense, a kind of shift register comprises: a plurality of scanning stages, and it is to the pulse of many select lines output scannings; The first illusory level, its in described a plurality of scanning stages first is exported the first illusory scanning impulse; And second illusory grade, its last in described a plurality of scanning stages is exported the second illusory scanning impulse.

Should be appreciated that above-mentioned general description of the present invention and following detailed description are exemplary and explanat, and be intended to provide further explanation the present invention for required protection.

Description of drawings

Accompanying drawing is included in this instructions, so that to further understanding of the present invention.Accompanying drawing is attached in this instructions and constitutes the part of this instructions.Accompanying drawing shows embodiments of the present invention, and is used from explanation principle of the present invention with instructions one.In the accompanying drawing:

Fig. 1 is the block diagram that illustrates according to the structure of the shift register of first illustrative embodiments of the present invention;

Fig. 2 is the sequential chart of exemplary signal that offers the shift register of Fig. 1 under the forward drive pattern;

Fig. 3 is the sequential chart of exemplary signal that offers the shift register of Fig. 1 under reverse drive mode;

Fig. 4 is the circuit diagram of the last illusory level among Fig. 1;

Fig. 5 is the circuit diagram of the following illusory level among Fig. 1;

Fig. 6 is the circuit diagram of each grade among Fig. 1;

Fig. 7 is the block diagram that illustrates according to the structure of the shift register of second illustrative embodiments of the present invention;

Fig. 8 is the circuit diagram of each grade among Fig. 7; And

Fig. 9 A and Fig. 9 B are respectively the synoptic diagram that has fluorescent light liquid crystal display backlight and have the liquid crystal display of LED backlight.

Embodiment

To describe embodiments of the present invention in detail below, example has gone out its example in the accompanying drawings.Under possible situation, identical label is represented identical or like in whole accompanying drawing.

Fig. 1 is the block diagram that illustrates according to the structure of the shift register of first illustrative embodiments of the present invention.Fig. 2 is the sequential chart of various signals that offers the shift register of Fig. 1 under the forward drive pattern.Fig. 3 is the sequential chart of various signals that offers the shift register of Fig. 1 under reverse drive mode.

As shown in Figure 1, the shift register according to first illustrative embodiments of the present invention comprises n level ST1～STn and two illusory level (dummy stages) ST0 and STn+1.In a frame period, ST1～STn exports two scanning impulses separately.Each grade ST1～STn utilizes this scanning impulse to drive coupled select lines, and utilizes the operation of this scanning impulse control downstream stage and upstream stage.All grades ST0～STn+1 that comprises illusory level ST0 and illusory down level STn+1 is output scanning pulse Vout0～Vout2n+1 in order.

At this moment, the signal condition according to forward voltage V_F and reverse voltage V_R drives each grade ST0～STn+1 according to direction or inverse direction.At first, under the forward drive pattern, ST0～STn+1 is according to the order output scanning pulse from last illusory level ST0 to down illusory level STn+1.That is to say, illusory scanning impulse Vout0 in the last illusory level ST0 output, first order ST1 exports the first scanning impulse Vout1 and the second scanning impulse Vout2 in proper order then, second level ST2 exports the 3rd scanning impulse Vout3 and the 4th scanning impulse Vout4 in proper order then, third level ST3 exports the 5th scanning impulse Vout5 and the 6th scanning impulse Vout6 in proper order then, by that analogy, STn exports (2n-1) scanning impulse Vout2n-1 and (2n) scanning impulse Vout2n in proper order up to the n level, and illusory scanning impulse Vout2n+1 under the last output of illusory down level STn+1.

Under reverse drive mode, ST0～STn+1 is according to the order output scanning pulse from following illusory level STn+1 to last illusory level ST0.That is to say, illusory down level STn+1 output is illusory scanning impulse Vout2n+1 down, n level STn exports (2n) scanning impulse Vout2n and (2n-1) scanning impulse Vout2n-1 in proper order then, (n-1) level STn-1 exports (2n-2) scanning impulse Vout2n-2 and (2n-3) scanning impulse Vout2n-3 in proper order then, (n-2) level STn-2 exports (2n-4) scanning impulse and (2n-5) scanning impulse in proper order then, by that analogy, export the second scanning impulse Vout2 and the first scanning impulse Vout1 in proper order up to first order ST1, and illusory scanning impulse Vout0 is gone up in the last output of last illusory level ST0.

Except last illusory level ST0 and down illusory level STn+1, will offer the select lines of liquid crystal panel (not shown) in proper order with these select liness of sequential scanning from the scanning impulse Vout1～Vout2n of ST1～STn output.

This shift register can be built in this liquid crystal panel.That is to say that this liquid crystal panel has the viewing area of display image and centers on the non-display area of this viewing area, and this shift register is built in this non-display area.As shown in Figures 2 and 3, each grade ST1～STn in the shift register that is arranged on by this way structure provides among first to the 4th time clock CLK1～CLK4 of order output out of phase each other and circulation output two, charging voltage, first and second to exchange (AC) voltage Vac1 and Vac2, forward voltage V_F and reverse voltage V_R.On the other hand, among last illusory level ST0 and the illusory down level STn+1 each provide among first to the 4th time clock CLK1～CLK4 of order output out of phase each other and circulation output any one, initial pulse Vst, charging voltage, sparking voltage, forward voltage V_F and reverse voltage V_R.

This charging voltage and sparking voltage all are direct current (DC) voltage.This charging voltage is positive, and this sparking voltage is born.Perhaps, this sparking voltage can be a ground voltage.This first and second AC voltage Vac1 and Vac2 are used for controlling the charging of reset node of node of each grade ST1～STn and the signal of discharge.The one AC voltage Vac1 and the 2nd AC voltage Vac2 all are AC voltage.The one AC voltage Vac1 is anti-phase with respect to Vac2180 ° of the 2nd AC voltage.The high state magnitude of voltage of the first and second AC voltage Vac1 and Vac2 can be identical with the magnitude of voltage of charging voltage, and the low state magnitude of voltage of the first and second AC voltage Vac1 and Vac2 can be identical with the magnitude of voltage of sparking voltage.The state of the first and second AC voltage Vac1 and Vac2 carries out anti-phase with the interval in the cycle of p frame.Here, p is a natural number.

First to the 4th time clock CLK1～CLK4 is the signal that is used to produce the scanning impulse of each grade of ST1～STn.Each grade ST1～STn receives two among first to the 4th time clock CLK1～CLK4 and exports two scanning impulses.For example, each odd level in these grades utilizes the first and second time clock CLK1 and two scanning impulses of CLK2 output, and each even level in these grades utilizes the third and fourth time clock CLK3 and two scanning impulses of CLK4 output.Although the property purpose is utilized four types different time clock of phase place presented for purpose of illustration in the present invention, can utilize the time clock of any number type, as long as they are two or more.First to the 4th time clock CLK1～CLK4 is output out of phase each other.That is to say that with respect to the first time clock CLK1, second clock pulse CLK2 exports after carrying out certain phase delay, with respect to second clock pulse CLK2, the 3rd time clock CLK3 exports after carrying out certain phase delay.With respect to the 3rd time clock CLK3, the 4th time clock CLK4 exports after carrying out certain phase delay, and with respect to the 4th time clock CLK4, the first time clock CLK1 exports after carrying out certain phase delay.

First to the 4th time clock CLK1～CLK4 order and output circularly.In other words, export first to the 4th time clock CLK1～CLK4 in proper order from the first time clock CLK1 to the, four time clock CLK4, and then export first to the 4th time clock CLK1～CLK4 in proper order from the first time clock CLK1 to the, four time clock CLK4.As a result, the output first time clock CLK1 in the cycle between the 4th time clock CLK4 and second clock pulse CLK2.

At a frame, only export initial pulse Vst one time, and at a frame period, each among time clock CLK1～CLK4 is all exported several times.In other words, at a frame period, initial pulse Vst only shows an active state (high state), and at a frame period, time clock CLK1～CLK4 periodically shows the several times active state separately.In a frame period, this initial pulse Vst prior among time clock CLK1～CLK4 any one and export.

As shown in Figure 2, under the forward drive pattern, according to order output time clock CLK1～CLK4 from the first time clock CLK1 to the, four time clock CLK4.Comparatively speaking, as shown in Figure 3, under reverse drive mode, according to the output of the order from the 4th time clock CLK4 to first time clock CLK1 time clock CLK1～CLK4.

In the present invention, as shown in Figures 2 and 3, first to the 4th time clock CLK1～CLK4 has the pulse width that overlaps each other.That is to say, as shown in Figure 2, the i time clock (wherein, i is the natural number more than or equal to 2) the second half the overlapping of pulse width of the first half and (i-1) time clock of pulse width, and the first half the overlapping of the pulse width of the second half and (i+1) time clock of the pulse width of i time clock.In addition, as shown in Figure 3, the second half of the pulse width of the first half and (i+1) time clock of the pulse width of i time clock overlaps, and the first half the overlapping of the pulse width of the second half and (i-1) time clock of the pulse width of i time clock.For example, as shown in Figures 2 and 3, suppose that among first to the 4th time clock CLK1～CLK4 each all has and 2 corresponding pulse widths of leveled time 2H, the time period that then adjacent time clock overlaps each other is corresponding with 1 leveled time 1H.This pulse width overlapping time period is not limited to pulse width half, and can be adjusted to section any time.Utilize the time clock CLK1～CLK4 that overlaps by this way, also overlap each other from the pulse width of the scanning impulse of each grade ST1～STn output.

Under the forward drive pattern, as shown in Figure 2, the first illusory time clock DCLK1 exported in the time period between the output cycle of the output cycle of initial pulse Vst and the first time clock CLK1.The first illusory time clock DCLK1 is the signal as the scanning impulse of last illusory level ST0, and only exports once at a frame period.This first illusory time clock DCLK1 exports with the 4th time clock CLK4 by the clock conveyer line that transmits the 4th time clock CLK4.In addition, under the forward drive pattern, as shown in Figure 2, the second illusory time clock DCLK2 exported in the time period between the output cycle of the output cycle of the 4th time clock CLK4 and the initial pulse Vst of next frame in the cycle.In other words, the second illusory time clock DCLK2 exported before the blanking interval of a frame just.The second illusory time clock DCLK2 is as the following signal of the scanning impulse of illusory level STn+1, and only exports once at a frame period.This second illusory time clock DCLK2 exports with the first time clock CLK1 by the clock conveyer line that transmits the first time clock CLK1.

Under reverse drive mode, as shown in Figure 3, the output of first to the 4th time clock CLK1～CLK4 occurs in sequence change.As a result, the second illusory time clock DCLK2 exported in the time period between the output cycle of the output cycle of initial pulse Vst and the 4th time clock CLK4.The second illusory time clock DCLK2 is as the following signal of the scanning impulse of illusory level STn+1, and only exports once at a frame period.As mentioned above, this second illusory time clock DCLK2 exports with the first time clock CLK1 by the clock conveyer line that transmits the first time clock CLK1.In addition, under reverse drive mode, as shown in Figure 3, because the change of the output of first to the 4th time clock CLK1～CLK4 order, the first illusory time clock DCLK1 exported in the time period between the output cycle of the output cycle of the first time clock CLK1 and the initial pulse Vst of next frame in the cycle.In other words, the first illusory time clock DCLK1 exported before the blanking interval of a frame just.The first illusory time clock DCLK1 is the signal as the scanning impulse of last illusory level ST0, and only exports once at a frame period.As mentioned above, this first illusory time clock DCLK1 exports with the 4th time clock CLK4 by the clock conveyer line that transmits the 4th time clock CLK4.

Provide various signals to last illusory level shown in Figure 1 and illusory down level ST0 and STn+1 and a level ST1～STn, and utilize these signals these progressive line operates with above-mentioned characteristic.Each grade ST1～STn must at first be enabled with the output scanning pulse.Each level is enabled and represents that each level is set to the output enable state.That is, can export the time clock that offers these grades state as scanning impulse.

Under the forward drive pattern, each grade ST1～STn is enabled in response to one of front in two scanning impulses of the output of trip level from it.For example, the j level is enabled in response to one of front from two scanning impulses of (j-1) level output.Yet under the forward drive pattern, top or first order ST1 is enabled in response to the last illusory scanning impulse Vout0 from last illusory level ST0.Last illusory level ST0 is enabled in response to the initial pulse Vst from initial conveyer line.

Comparatively speaking, under reverse drive mode, each grade ST1～STn is enabled in response to one of front from two scanning impulses of its downstream stage output.For example, the j level is enabled in response to one of front from two scanning impulses of (j+1) level output.Yet under reverse drive mode, end level or n level STn are enabled in response to the following illusory scanning impulse Vout2n+1 from illusory level STn+1 output down.Illusory down level STn+1 is enabled in response to the initial pulse Vst from initial conveyer line.

On the other hand, each grade ST1～STn is disabled after the output scanning pulse.Each level of the disabled expression of each grade resets to the output disabled status.That is, can not export the time clock that offers these grades state as scanning impulse.

Under the forward drive pattern, each grade ST1～STn is enabled in response to one of back from two scanning impulses of its downstream stage output.For example, the j level is enabled in response to one of back from two scanning impulses of (j+1) level output.Yet under the forward drive pattern, end level or n level STn are enabled in response to the following illusory scanning impulse Vout2n+1 from following illusory level STn+1.Illusory down level STn+1 is enabled in response to the initial pulse Vst from initial conveyer line.

Comparatively speaking, under reverse drive mode, each grade ST1～STn is enabled in response to one of back in two scanning impulses of the output of trip level from it.For example, the j level is enabled in response to one of back from two scanning impulses of (j-1) level output.Yet under reverse drive mode, top or first order ST1 is enabled in response to the last illusory scanning impulse Vout0 from last illusory level ST0.Last illusory level ST0 is enabled in response to the initial pulse Vst from initial conveyer line.

Each structure among the level ST1～STn of shift register of the structure by this way that comprises illusory level and illusory down level ST0 and STn+1 hereinafter will be described in further detail.Fig. 4 is the circuit diagram of the last illusory level ST0 among Fig. 1.

As shown in Figure 4, last illusory level ST0 comprises Node Controller NC, output unit OP and direction of scanning controller SDC.Node Controller NC comprises first to the 3rd switching element T r1～Tr3.The first switching element T r1 is switched on/ends according to the signal condition of reset node QB, and is connected between the sparking voltage line of set node Q and transmission sparking voltage VSS.For this reason, the gate terminal of the first switching element T r1 is connected to reset node QB, and drain terminal is connected to set node Q, and source terminal is connected to the sparking voltage line.Second switch device Tr2 is switched on/ends according to the charging voltage VDD from the sparking voltage line, and is connected between charging voltage line and the reset node QB.For this reason, gate terminal and the drain terminal of second switch device Tr2 are connected to the charging voltage line, and source terminal is connected to reset node QB.The 3rd switch Tr3 is switched on/ends according to the signal condition of set node Q, and is connected between reset node and the sparking voltage line.For this reason, the gate terminal of the 3rd switching element T r3 is connected to set node Q, and drain terminal is connected to reset node QB, and source terminal is connected to the sparking voltage line.

Output unit OP comprises drag switch device Trpu and the device Trpd that pulls down switch.Last drag switch device Trpu is switched on/ends according to the signal condition of set node Q, and is connected between any and the lead-out terminal 333 in the clock conveyer line of transmission clock pulse CLK1～CLK4.For this reason, the gate terminal of last drag switch device Trpu is connected to set node Q, and drain terminal is connected to any in the clock conveyer line, and source terminal is connected to lead-out terminal 333.Here, the drain terminal of last drag switch device Trpu is connected to the clock conveyer line that transmits the 4th time clock CLK4.

Direction of scanning controller SDC comprises forward switching element T r_F and reverser device Tr_R.Forward switching element T r_F is switched on/ends in response to the initial pulse Vst from initial conveyer line, and is connected between the forward voltage line and set node Q that transmits forward voltage V_F.For this reason, the gate terminal of forward switching element T r_F is connected to initial conveyer line, and drain terminal is connected to the forward voltage line, and source terminal is connected to set node Q.

Reverser device Tr_R is switched on/ends in response to the first scanning impulse Vout1 from first order ST1, and is connected between the reverse voltage line of set node Q and transmission reverse voltage V_R.For this reason, the gate terminal of reverser device Tr_R is connected to any one in two lead-out terminals of first order ST1, and drain terminal is connected to set node Q, and source terminal is connected to the reverse voltage line.

Fig. 5 is the circuit diagram of the following illusory level STn+1 among Fig. 1.As shown in Figure 5, following illusory level STn+1 comprises Node Controller NC, output unit OP and direction of scanning controller SDC.Node Controller NC comprises first to the 3rd switching element T r1～Tr3.The first switching element T r1 is switched on/ends according to the signal condition of reset node QB, and is connected between the sparking voltage line of set node Q and transmission sparking voltage VSS.For this reason, the gate terminal of the first switching element T r1 is connected to reset node QB, and drain terminal is connected to set node Q, and source terminal is connected to the sparking voltage line.Second switch device Tr2 is switched on/ends according to the charging voltage VDD from the charging voltage line, and is connected between charging voltage line and the reset node QB.For this reason, gate terminal and the drain terminal of second switch device Tr2 are connected to the charging voltage line, and source terminal is connected to reset node QB.The 3rd switch Tr3 is switched on/ends according to the signal condition of set node Q, and is connected between reset node QB and the sparking voltage line.For this reason, the gate terminal of the 3rd switching element T r3 is connected to set node Q, and drain terminal is connected to reset node QB, and source terminal is connected to the sparking voltage line.

Output unit OP comprises drag switch device Trpu and the device Trpd that pulls down switch.Last drag switch device Trpu is switched on/ends according to the signal condition of set node Q, and is connected between any and the lead-out terminal 333 in the clock conveyer line of transmission clock pulse CLK1～CLK4.For this reason, the gate terminal of last drag switch device Trpu is connected to set node Q, and drain terminal is connected to any in the clock conveyer line, and source terminal is connected to lead-out terminal 333.Here, the drain terminal of last drag switch device Trpu is connected to the clock conveyer line that transmits the first time clock CLK1.

Direction of scanning controller SDC comprises forward switching element T r_F and reverser device Tr_R.Forward switching element T r_F is in response to being switched on/ending from two scanning impulses of n level STn any one, and is connected between the forward voltage line and set node Q that transmits forward voltage V_F.For this reason, the gate terminal of forward switching element T r_F is connected to any one in two lead-out terminals of n level, and drain terminal is connected to the forward voltage line, and source terminal is connected to set node Q.

Reverser device Tr_R is switched on/ends in response to the initial pulse Vst from initial conveyer line, and is connected between the reverse voltage line of set node Q and transmission reverse voltage V_R.For this reason, the gate terminal of reverser device Tr_R is connected to initial conveyer line, and drain terminal is connected to set node Q, and source terminal is connected to the reverse voltage line.

Fig. 6 is the circuit diagram of each grade ST1～STn among Fig. 1.As shown in Figure 6, ST1～STn Node Controller, direction of scanning controller SDC and output unit OP of including at different levels.Node Controller is controlled the signal condition of the first set node Q1, the second set node Q2, the first reset node QB1 and the second reset node QB2.The Node Controller of k level comprises the first to the 15 switching element T r1～Tr15.

The first switching element T r1 in the k level is switched on/ends according to the signal condition of the first reset node QB1, and is connected between the first set node Q1 and the sparking voltage line.For this reason, the gate terminal of the first switching element T r1 in the k level is connected to the first reset node QB1, and drain terminal is connected to the first set node Q1, and source terminal is connected to the sparking voltage line.

Second switch device Tr2 in the k level is switched on/ends according to the signal condition of the second reset node QB2, and is connected between the first set node Q1 and the sparking voltage line.For this reason, the gate terminal of the second switch device Tr2 in the k level is connected to the second reset node QB2, and drain terminal is connected to the first set node Q1, and source terminal is connected to the sparking voltage line.

The 3rd switching element T r3 in the k level is switched on/ends according to the signal condition of the first set node Q1, and is connected between the first reset node QB1 and the sparking voltage line.For this reason, the gate terminal of the 3rd switching element T r3 in the k level is connected to the first set node Q1, and drain terminal is connected to the first reset node QB1, and source terminal is connected to the sparking voltage line.

The 4th switching element T r4 in the k level is switched on/ends according to the AC voltage Vac1 from an AC pressure-wire, and is connected between an AC pressure-wire and the first common node CN1.For this reason, the gate terminal of the 4th switching element T r4 in the k level and drain terminal are connected to an AC pressure-wire, and source terminal is connected to the first common node CN1.

The 5th switching element T r5 in the k level is switched on/ends according to the signal condition of the first common node CN1, and is connected between an AC pressure-wire and the first reset node QB1.For this reason, the gate terminal of the 5th switching element T r5 in the k level is connected to the first common node CN1, and drain terminal is connected to an AC pressure-wire, and source terminal is connected to the first reset node QB1.

The 6th switching device in the k level is switched on/ends according to the signal condition of the first set node Q1, and is connected between the first common node CN1 and the sparking voltage line.For this reason, the gate terminal of the 6th switching element T r6 in the k level is connected to the first set node Q1, and drain terminal is connected to the first common node CN1, and source terminal is connected to the sparking voltage line.

Minion pass device Tr7 in the k level is switched on/ends according to the signal condition of the second set node Q2, and is connected between the first common node CN1 and the sparking voltage line.For this reason, the gate terminal that the minion in the k level is closed device Tr7 is connected to the second set node Q2, and drain terminal is connected to the first common node CN1, and source terminal is connected to the sparking voltage line.

Octavo in the k level is closed device Tr8 and is switched on/ends in response to the output signal from direction of scanning controller SDC, and is connected between the second reset node QB2 and the sparking voltage line.For this reason, the gate terminal of the octavo pass device Tr8 in the k level is connected to the lead-out terminal of direction of scanning controller SDC, and drain terminal is connected to the second reset node QB2, and source terminal is connected to the sparking voltage line.

The 9th switching element T r9 in the k level is switched on/ends according to the signal condition of the first reset node QB1, and is connected between the second set node Q2 and the sparking voltage line.For this reason, the gate terminal of the 9th switching element T r9 in the k level is connected to the first reset node QB1, and drain terminal is connected to the second set node Q2, and source terminal is connected to the sparking voltage line.

The tenth switching element T r10 in the k level is switched on/ends according to the signal condition of the second reset node QB2, and is connected between the second set node Q2 and the sparking voltage line.For this reason, the gate terminal of the tenth switching element T r10 in the k level is connected to the second reset node QB2, and drain terminal is connected to the second set node Q2, and source terminal is connected to the sparking voltage line.

The 11 switching element T r11 in the k level is switched on/ends according to the signal condition of the second set node Q2, and is connected between the second reset node QB2 and the sparking voltage line.For this reason, the gate terminal of the 11 switching element T r11 in the k level is connected to the second set node Q2, and drain terminal is connected to the second reset node QB2, and source terminal is connected to the sparking voltage line.

Twelvemo in the k level is closed device Tr12 and is switched on/ends according to the 2nd AC voltage Vac2 from the 2nd AC pressure-wire, and is connected between the 2nd AC pressure-wire and the second common node CN2.For this reason, gate terminal and drain terminal that the twelvemo in the k level is closed device Tr12 are connected to the 2nd AC pressure-wire, and source terminal is connected to the second common node CN2.

The 13 switching element T r13 in the k level is switched on/ends according to the signal condition of the second common node CN2, and is connected between the 2nd AC pressure-wire and the second reset node QB2.For this reason, the gate terminal of the 13 switching element T r13 in the k level is connected to the second common node CN2, and drain terminal is connected to the 2nd AC pressure-wire, and source terminal is connected to the second reset node QB2.

The 14 switching element T r14 in the k level is switched on/ends according to the signal condition of the second set node Q2, and is connected between the second common node CN2 and the sparking voltage line.For this reason, the gate terminal of the 14 switching element T r14 in the k level is connected to the second set node Q2, and drain terminal is connected to the second common node CN2, and source terminal is connected to the sparking voltage line.

The 15 switching element T r15 in the k level is switched on/ends according to the signal condition of the first set node Q1, and is connected between the second common node CN2 and the sparking voltage line.For this reason, the gate terminal of the 15 switching element T r15 in the k level is connected to the first set node Q1, and drain terminal is connected to the second common node CN2, and source terminal is connected to the sparking voltage line.

Direction of scanning controller SDC comprises first to the 3rd forward switching element T r_F1～Tr_F3, first to the 3rd reverser device Tr_R1～Tr_R3 and gauge tap device Tr_C.The first forward switching element T r_F1 in the k level is switched on/ends in response to one of front from two scanning impulses of (k-1) level output, and is connected between the forward voltage line and the first set node Q1.For this reason, the gate terminal of the first forward switching element T r_F1 in the k level is connected to the first lead-out terminal 111a of (k-1) level, and drain terminal is connected to the forward voltage line, and source terminal is connected to the first set node Q1.Significantly, the gate terminal of the first forward switching element T r_F1 among the first order ST1 is connected to the lead-out terminal of illusory level ST0.

The first reverser device Tr_R1 in the k level is switched on/ends in response to one of back from two scanning impulses of (k+1) level output, and is connected between the first set node Q1 and the reverse voltage line.For this reason, the gate terminal of the first reverser device Tr_R1 in the k level is connected to the second lead-out terminal 111b of (k+1) level, and drain terminal is connected to the first set node Q1, and source terminal is connected to the reverse voltage line.

The second forward switching element T r_F2 in the k level is switched on/ends in response to one of front from two scanning impulses of (k-1) level output, and is connected between the forward voltage line and the second set node Q2.For this reason, the gate terminal of the second forward switching element T r_F2 in the k level is connected to the first lead-out terminal 111a of (k-1) level, and drain terminal is connected to the forward voltage line, and source terminal is connected to the second set node Q2.Significantly, the gate terminal of the second forward switching element T r_F2 among the first order ST1 is connected to the lead-out terminal of illusory level ST0.

The second reverser device Tr_R2 in the k level is switched on/ends in response to one of back from two scanning impulses of (k+1) level output, and is connected between the second set node Q2 and the reverse voltage line.For this reason, the gate terminal of the second reverser device Tr_R2 in the k level is connected to the second lead-out terminal 111b of (k+1) level, and drain terminal is connected to the second set node Q2, and source terminal is connected to the reverse voltage line.

The 3rd forward switching element T r_F3 in the k level is switched on/ends in response to one of front from two scanning impulses of (k-1) level output, and is connected between the 3rd common node CN3 and the forward voltage line.For this reason, the gate terminal of the 3rd forward switching element T r_F3 is connected to the first lead-out terminal 111a of (k-1) level, and drain terminal is connected to the 3rd common node CN3, and source terminal is connected to the forward voltage line.

The 3rd reverser device Tr_R3 in the k level is switched on/ends in response to one of back from two scanning impulses of (k+1) level output, and is connected between reverse voltage line and the 3rd common node CN3.For this reason, the gate terminal of the 3rd reverser device Tr_R3 is connected to the second lead-out terminal 111b of (k+1) level, and drain terminal is connected to the reverse voltage line, and source terminal is connected to the 3rd common node CN3.

Gauge tap device Tr_C in the k level is according to the signal condition of the 3rd common node CN3 and Be Controlled, and is connected between the first reset node QB1 and the sparking voltage line.For this reason, the gate terminal of the gauge tap device Tr_C in the k level is connected to the 3rd common node CN3, and drain terminal is connected to the first reset node QB1, and source terminal is connected to the sparking voltage line.On the other hand, the gate terminal of the pass of the octavo in k level device Tr8 is connected to the 3rd common node CN3.

Output unit OP comprises that drag switch device Trpu1 and Trpu2 and first to the 4th pull down switch device Trpd1 to Trpd4 on first and second.Drag switch device Trpu1 is switched on/ends according to the signal condition of the first set node Q1 on first, and is connected between any and the first lead-out terminal 111a in the clock conveyer line of transmission clock pulse CLK1～CLK4.For this reason, the gate terminal of drag switch device Trpu1 is connected to the first set node Q1 on first, and drain terminal is connected to any in the clock conveyer line, and source terminal is connected to the first lead-out terminal 111a.

Drag switch device Trpu2 is switched on/ends according to the signal condition of the second set node Q2 on second, and is connected between any and the second lead-out terminal 111b in the clock conveyer line of transmission clock pulse CLK1～CLK4.For this reason, the gate terminal of drag switch device Trpu2 is connected to the second set node Q2 on second, and drain terminal is connected to any in the clock conveyer line, and source terminal is connected to the second lead-out terminal 111b.Here, on first on the drain terminal and second of drag switch device Trpu1 the drain terminal of drag switch device Trpu2 be connected to different clock conveyer lines.

The first device Trpd1 that pulls down switch is switched on/ends according to the signal condition of the first reset node QB1, and is connected between the first lead-out terminal 111a and the sparking voltage line.For this reason, first gate terminal that pulls down switch device Trpd1 is connected to the first reset node QB1, and drain terminal is connected to the first lead-out terminal 111a, and source terminal is connected to the sparking voltage line.

The second device Trpd2 that pulls down switch is switched on/ends according to the signal condition of the second reset node QB2, and is connected between the first lead-out terminal 111a and the sparking voltage line.For this reason, second gate terminal that pulls down switch device Trpd2 is connected to the second reset node QB2, and drain terminal is connected to the first lead-out terminal 111a, and source terminal is connected to the sparking voltage line.

The 3rd device Trpd3 that pulls down switch is switched on/ends according to the signal condition of the first reset node QB1, and is connected between the second lead-out terminal 111b and the sparking voltage line.For this reason, the 3rd gate terminal that pulls down switch device Trpd3 is connected to the first reset node QB1, and drain terminal is connected to the second lead-out terminal 111b, and source terminal is connected to the sparking voltage line.

The 4th device Trpd4 that pulls down switch is switched on/ends according to the signal condition of the second reset node QB2, and is connected between the second lead-out terminal 111b and the sparking voltage line.For this reason, the 4th gate terminal that pulls down switch device Trpd4 is connected to the second reset node QB2, and drain terminal is connected to the second lead-out terminal 111b, and source terminal is connected to the sparking voltage line.

The operation that hereinafter description is had the shift register of said structure.At first, with reference to Fig. 2, Fig. 4, Fig. 5 and Fig. 6 description operation based on the shift register of forward drive pattern.

Because the operation of shift register is based on the forward drive pattern, so as shown in Figure 2, time clock CLK1～CLK4 is according to exporting from the order of the first time clock CLK1 to the, four time clock CLK4, and forward voltage V_F is in high state, and reverse voltage V_R is in low state.At first, with the operation in the first initial time section Ts in first frame period of description.

In first frame period, an AC voltage Vac1 is positive, and the 2nd AC voltage Vac2 bears.As shown in Figure 2, in the first initial time section Ts, only the initial pulse Vst from timing controller output remains high state, and remains low state from the time clock CLK1～CLK4 of timing controller output.

To offer last illusory level ST0 and down illusory level STn+1 from the initial pulse Vst of timing controller output.That is to say, as shown in Figure 4, initial pulse Vst is offered the gate terminal of the forward switching element T r_F among the last illusory level ST0.As a result, the forward voltage V_F of forward switching element T r_F conducting and high state offers set node Q by the forward switching element T r_F of conducting.Therefore, aaset bit node Q charges and is connected to last drag switch device Trpu and the 3rd switching element T r3 conducting thus of the set node Q after the charging by its gate terminal.

Sparking voltage VSS offers reset node QB by the 3rd switching element T r13 of conducting.On the other hand, because second switch device Tr2 is by always keeping conducting as the charging voltage VDD of the dc voltage of high state, so charging voltage VDD offers reset node QB by second switch device Tr2.As a result, the sparking voltage VSS of the charging voltage VDD of the high state by second switch device Tr2 output and the low state by the 3rd switching element T r3 output is offered reset node QB together.At this moment, because the size of the 3rd switching element T r3 is set to larger than the size of second switch device Tr2, so the sparking voltage VSS of reset node QB by the low state that provides via the 3rd switching element T r3 discharges.Therefore, be connected to pull down switch the device Trpd and the first switching element T r1 conducting of the reset node QB after the discharge by its gate terminal.

On the other hand, owing to the output that in the first initial time section Ts, does not have from first order ST1, so the reverser device Tr_R remain off in last illusory level ST0.By this way, in the first initial time section Ts, last illusory level ST0 set.Simultaneously, in the first initial time section Ts, the following illusory level STn+1 that provides initial pulse Vst resets, and this point shall be described in more detail below.That is to say that as shown in Figure 5, initial pulse Vst is provided for down the gate terminal of the reverser device Tr_R among the illusory level STn+1.As a result, the reverse voltage V_R of reverser device Tr_R conducting and low state offers set node Q by the reverser device Tr_R of conducting.Therefore, aaset bit node Q discharges and ends thus by last drag switch device Trpu and the 3rd switching element T r3 that its gate terminal is connected to the set node Q after the discharge.Because second switch device Tr2 is by always keeping conducting as the charging voltage VDD of the dc voltage of high state, so charging voltage VDD offers reset node QB by second switch device Tr2.As a result, reset node QB is charged and be connected to pull down switch the device Trpd and the first switching element T r1 conducting thus of the reset node QB after the charging by its gate terminal.

The first switching element T r1 of conducting provides sparking voltage VSS to set node Q, so that set node Q can more stably remain on its discharge condition.And the first switching element T r1 of conducting provides sparking voltage VSS to n level STn.By this way, in the first initial time section Ts, following illusory level STn+1 resets.

Next, with the operation that is described in the second initial time section T0.In the second initial time section T0, only the first illusory time clock DCLK1 remains on high state, and initial pulse Vst all remains on low state with all time clock CLK1～CLK4.In the second initial time section T0, initial pulse Vst becomes low state from high state, and the forward switching element T r_F in the last illusory level ST0 ends thus, thereby makes the set node Q in the illusory level ST0 float.As a result, the charging voltage VDD that offers the set node Q in the illusory level ST0 in the first initial time section Ts is maintained at set node Q place, though in the second initial time section T0 too.

Because the set node Q in the last illusory level ST0 keeps charging by the charging voltage VDD that applies in the first initial time section Ts, last drag switch device Trpu and the 3rd switching element T r3 maintenance conducting in the above illusory level ST0 of institute.At this moment, because the first illusory time clock DCLK1 is applied to the drain terminal of the last drag switch device Trpu of conducting, so the charging voltage VDD that charges in the unsteady set node Q place in last illusory level ST0 amplifies by boostrap circuit (bootstrapping).

Therefore, the first illusory time clock DCLK1 that is applied to the drain terminal of the last drag switch device Trpu in the illusory level ST0 stablizes output by the source terminal (lead-out terminal) of last drag switch device Trpu.This first illusory time clock DCLK1 by last drag switch device Trpu output goes up illusory scanning impulse Vout0.Go up illusory scanning impulse Vout0 and be provided for first order ST1 to be used to enable first order ST1.That is to say that the last illusory scanning impulse Vout0 that exports from last illusory level ST0 is provided for the first forward switching element T r_F1 the first order ST1, each gate terminal that the 3rd forward switch is adorned the Tr_F3 and the second forward switching element T r_F2.

Then, the first forward switching element T r_F1, the 3rd forward switching element T r_F3 and the second forward switching element T r_F2 conducting, thus make the first forward switching element T r_F1 of forward voltage V_F by conducting of high state be applied to the first set node Q1.As a result, the first set node Q1 is charged and by its gate terminal be connected to the first set node Q1 after the charging first on drag switch device Trpu1, the 3rd switching element T r3, the 6th switching element T r6 and the 15 switching element T r15 conducting thus.Sparking voltage VSS offers the first reset node QB1 by the 3rd switching element T r3 of conducting, thereby the first reset node QB1 is discharged.As a result, being connected to first of the first reset node QB1 pull down switch device Trpd3 and the 9th switching element T r9 of device Trpd1, the first switching element T r1, the 3rd that pull down switch by its gate terminal ends.

On the other hand, owing to remain high state, provide the 4th switching element T r4 maintenance conducting of an AC voltage Vac1 at first frame period at an AC voltage Vac1 in first frame period.The one AC voltage Vac1 offers the first common node CN1 of first order ST1 by the 4th switching element T r4 of conducting.At this moment, the sparking voltage VSS of the output of the 6th switching element T r6 by conducting also is provided for the first common node CN1.That is to say that an AC voltage Vac1 of high state and the sparking voltage VSS of low state are provided for the first common node CN1 together.

Significantly, because the size that provides the size of the 6th switching element T r6 of sparking voltage VSS to be set to larger than the 4th switching element T r4 that an AC voltage Vac1 is provided, so sparking voltage VSS remains on the first common node CN1.On the other hand, the sparking voltage VSS that closes device Tr7 output by the minion of conducting is further provided to the first common node CN1, and this names a person for a particular job and is described afterwards.As a result, the first common node CN1 is discharged and end thus by the 5th switching element T r5 that its gate terminal is connected to the first common node CN1 after the discharge.

On the other hand, in the second initial time section T0, the forward voltage V_F of high state is applied to the second set node Q2 by the second forward switching element T r_F2 of conducting.As a result, the second set node Q2 is charged and by its gate terminal be connected to the second set node Q2 after the charging second on drag switch device Trpu2, the 11 switching element T r11, the 14 switching element T r14 and minion close device Tr7 conducting thus.Sparking voltage VSS offers the second reset node QB2 by the 11 switching element T r11 of conducting, thereby the second reset node QB2 is discharged.As a result, being connected to the 4th of the second reset node QB2 pull down switch device Trpd2 and the second switch device Tr2 of device Trpd4, the tenth switching element T r10, second that pull down switch by its gate terminal ends.

On the other hand, owing to remain on low state, provide the twelvemo pass device Tr12 remain off of the 2nd AC voltage Vac2 at first frame period at first frame period the 2nd AC voltage Vac2.The sparking voltage VSS of the 15 switching element T r15 output by conducting is provided for the second common node CN2.As a result, the second common node CN2 is discharged, and end by the 13 switching element T r13 that its gate terminal is connected to the second common node CN2 after the discharge.

On the other hand, in the second initial time section T0, the forward voltage V_F of high state is applied to the 3rd common node CN3 by the 3rd forward switching element T r_F3 of conducting.As a result, the 3rd common node CN3 is charged, and close device Tr8 conducting thus by gauge tap device Tr_C and octavo that its gate terminal is connected to the 3rd common node CN3 after the charging.The gauge tap device Tr_C of conducting provides sparking voltage VSS to the first reset node QB1, so that stable its discharge condition that remains on of the first reset node QB1.And the octavo of conducting is closed device Tr8 and is provided sparking voltage VSS to the second reset node QB2, so that the second reset node QB2 more stably remains on its discharge condition.

By this way, in the second initial time section T0, the first and second set node Q1 and the Q2 of first order ST1 charged, and the first and second reset node QB1 and the QB2 of first order ST1 discharged, enable first order ST1 thus.

Next, with the operation that is described in the very first time section T1.As shown in Figure 2, in very first time section T1, only the first time clock CLK1 remains high state, and remaining time clock CLK2～CLK4 comprises that initial pulse Vst all remains low state.

Because the first set node Q1 in the first order ST1 keeps charging by the charging voltage VDD that applies in the first initial time section Ts, so drag switch device Trpu1 keeps conducting on first in the first order ST1.At this moment and since the first time clock CLK1 be applied to conducting first on the drain terminal of drag switch device Trpu1, so the charging voltage VDD that charges in the first set node Q1 place of floating in first order ST1 amplifies by boostrap circuit.

Therefore, the first time clock CLK1 that is applied to the drain terminal of drag switch device Trpu1 on first in the first order ST1 stablizes output by the source terminal (the first lead-out terminal 111a) of drag switch device Trpu1 on first.This first time clock CLK1 by drag switch device Trpu1 output on first is the first scanning impulse Vout1.The first scanning impulse Vout1 is provided for first select lines, second level ST2 and last illusory level ST0.As a result, in very first time section T1, first select lines is driven, and second level ST2 is enabled, and last illusory level ST0 is disabled.

According to the identical mode of mode that in the first initial time section Ts, enables the aforesaid operations of first order ST1, carry out the operation in very first time section T1, enable second level ST2.On the other hand, in very first time section T1, the first scanning impulse Vout1 that exports from first order ST1 is provided for last illusory level ST0, so that last illusory level ST0 is disabled.Will hereafter be described in more detail this deactivation operation.

That is to say that the first scanning impulse Vout1 is provided for the gate terminal of the reverser device Tr_R in the illusory level ST0.As a result, the reverse voltage V_R of reverser device Tr_R conducting and low state offers the set node Q of last illusory level ST0 by the reverser device Tr_R of conducting.Therefore, aaset bit node Q discharges and ends thus by last drag switch device Trpu and the 3rd switching element T r3 that its gate terminal is connected to the set node Q after the discharge.

Because the 3rd switching element T r3 in the last illusory level ST0 ends, so the high state charging voltage VDD by second switch device Tr2 output is provided for the reset node QB in the last illusory level ST0.So reset node QB is charged and is connected to pull down switch the device Trpd and the first switching element T r1 conducting thus in the last illusory level ST0 of the reset node QB after the charging by its gate terminal.The device Trpd that pulls down switch of conducting provides sparking voltage VSS to first order ST1.

The set node Q that the first switching element T r1 in the last illusory level ST0 makes progress in the illusory level ST0 provides sparking voltage VSS, thereby set node Q is more stably remained on its discharge condition.

Next, with the operation that is described in the second time period T2.In the second time period T2, only the first and second time clock CLK1 and CLK2 remain on high state, and remaining time clock CLK3 and CLK4 comprise that initial pulse Vst all remains on low state.Drag switch device Trpu1 exports the first scanning impulse Vout1 in response to the first time clock CLK1 with complete form in the first order ST1 first.In this second time period T2, enable second level ST2 by the first scanning impulse Vout1.

And drag switch device Trpu2 begins to export the second scanning impulse Vout2 in response to second clock pulse CLK2 on second in the first order ST1.That is to say, because the second set node Q2 in the first order ST1 keeps charging by the charging voltage VDD that applies in the first initial time section Ts, so drag switch device Trpu2 keeps conducting on second in the first order ST1.At this moment and since second clock pulse CLK2 be applied to conducting second on the drain terminal of drag switch device Trpu2, so the charging voltage VDD that charges in the second set node Q2 place of floating in first order ST1 amplifies by boostrap circuit.

Therefore, the second clock pulse CLK2 that is applied to the drain terminal of drag switch device Trpu2 on second in the first order ST1 stablizes output by the source terminal (the second lead-out terminal 111b) of drag switch device Trpu2 on second.This second clock pulse CLK2 by drag switch device Trpu2 output on second is the second scanning impulse Vout2.The second scanning impulse Vout2 is provided for second select lines to drive second select lines.

Next, with the operation that is described in the 3rd time period T3.In the 3rd time period T3, only the second and the 3rd time clock CLK2 and CLK3 remain on high state, and remaining time clock CLK1 and CLK4 comprise that initial pulse Vst all remains on low state.

Drag switch device Trpu2 exports the second scanning impulse Vout2 in response to second clock pulse CLK2 with complete form in the first order ST1 second.This second scanning impulse Vout2 is provided for second select lines.And drag switch device Trpu1 begins to export the 3rd scanning impulse Vout3 in response to the 3rd time clock CLK3 on first in the ST2 of the second level.

In this 3rd time period T3, be provided for the 3rd select lines beginning driving the 3rd select lines from the 3rd scanning impulse Vout3 of second level ST2, and the 3rd scanning impulse Vout3 also is provided for third level ST3, to enable third level ST3.

Next, with the operation that is described in the 4th time period T4.In the 4th time period T4, only the third and fourth time clock CLK3 and CLK4 remain on high state, and remaining time clock CLK1 and CLK2 comprise that initial pulse Vst all remains on low state.

Drag switch device Trpu1 exports the 3rd scanning impulse Vout3 in response to the 3rd time clock CLK3 with complete form in the ST2 of the second level first.This 3rd scanning impulse Vout3 is provided for the 3rd select lines and fourth stage ST4.And drag switch device Trpu2 exports the 4th scanning impulse Vout4 in response to the 4th time clock CLK4 on second in the ST2 of the second level.This 4th scanning impulse Vout4 is provided for the 4th select lines beginning driving the 4th select lines, and the 4th scanning impulse Vout4 also is provided for first order ST1, with forbidding first order ST1.

Hereinafter will describe the operation of forbidding first order ST1 in detail.That is to say that the 4th scanning impulse Vout4 is provided for first order ST1 interior first reverser device Tr_R1, the second reverser device Tr_R2 and each gate terminal of the 3rd reverser device Tr_R3.As a result, the first reverser device Tr_R1, the second reverser device Tr_R2 and the 3rd reverser device Tr_R3 conducting.

The first reverser device Tr_R1 of the reverse voltage V_R of low state by conducting offers the first set node Q1 in the first order ST1.The result, the first set node Q1 is discharged, and by its gate terminal be connected to the first set node Q1 after the discharge first on drag switch device Trpu1, the 3rd switching element T r3, the 6th switching element T r6 and the 15 switching element T r15 end thus.

And the second reverser device Tr_R2 of the reverse voltage V_R of low state by conducting offers the second set node Q2 in the first order ST1.The result, the second set node Q2 is discharged, and by its gate terminal be connected to the second set node Q2 after the discharge second on drag switch device Trpu2, the 11 switching element T r11, the 14 switching element T r14 and minion close device Tr7 and end thus.

And the three reverser device Tr_R3 of the reverse voltage V_R of low state by conducting offers the 3rd common node CN3 in the first order ST1.As a result, the 3rd common node CN3 is discharged, and be connected to the gauge tap device Tr_C of the 3rd common node CN3 after the discharge and octavo by its gate terminal and close device Tr8 and end thus.

Because the 6th and minion among the first order ST1 are closed device Tr6 and Tr7 ends, so the AC voltage Vac1 by the 4th switching element T r4 output is provided for the first common node CN1 in the first order ST1.The result charges to the first common node CN1, and is connected to the 5th switching element T r5 conducting thus of the first common node CN1 after the charging by its gate terminal.

Then, the five switching element T r5 of an AC voltage Vac1 by conducting offers the first reset node QB1 in the first order ST1.The result, the first reset node QB1 is charged, and be connected to first in the first order ST1 of the first reset node QB1 after the charging pull down switch device Trpd1, the 3rd pull down switch device Trpd3, the first switching element T r1 and the 9th switching element T r9 conducting thus by its gate terminal.

The first switching element T r1 of sparking voltage VSS by conducting offers the first set node Q1 in the first order ST1, thereby makes the set node Q1 that wins can more stably remain on its discharge condition.And the nine switching element T r9 of sparking voltage VSS by conducting offers the second set node Q2 in the first order ST1, thereby makes the second set node Q2 can more stably remain on its discharge condition.

By this way, in the 4th time period T4, by to the first and second set node Q1 in the first order ST1 with Q2 discharges, the first reset node QB1 in the first order ST1 is charged, and the second reset node QB2 in the first order ST1 discharged, make that first order ST1 is disabled.

As mentioned above, in the 4th time period T4, device Trpd1 and the 3rd device Trpd3 conducting that pulls down switch because first of first order ST1 pulls down switch, so first pulls down switch device Trpd1 by first lead-out terminal 111a output sparking voltage VSS, to provide sparking voltage VSS to first select lines, second level ST2 and last illusory level ST0, and the 3rd pulls down switch device Trpd3 by second lead-out terminal 111b output sparking voltage VSS, to provide sparking voltage VSS to second select lines.And the level V that drives in proper order subsequently according to mode same as described above arrives illusory down level ST5 to STn+1.On the other hand, in second frame period, an AC voltage Vac1 bears, and the 2nd AC voltage Vac2 is positive.Therefore, at the forbidding in second frame period in the time period, the first reset node QB1 of each grade ST1～STn is discharged, and its second reset node QB2 is charged.Therefore, at the forbidding in first frame period in the time period, pull down switch device Trpd2 and Trpd4 of the second and the 4th of each grade ST1～STn operated.

Next, with reference to Fig. 3, Fig. 4, Fig. 5 and Fig. 6 description operation based on the shift register of reverse drive mode.Because the operation of shift register is based on reverse drive mode, so as shown in Figure 3, time clock CLK1～CLK4 is according to exporting to the order of the first time clock CLK1 from the 4th time clock CLK4, and forward voltage V_F is in low state, and reverse voltage V_R is in high state.

At first, with the operation in the first initial time section Ts in first frame period of description.In first frame period, an AC voltage Vac1 is positive, and the 2nd AC voltage Vac2 bears.As shown in Figure 3, in the first initial time section Ts, only the initial pulse Vst from timing controller output remains on high state, and all remains low state from the time clock CLK1～CLK4 of timing controller output.

Offer last illusory level ST0 and down illusory level STn+1 from the initial pulse Vst of timing controller output.That is to say that as shown in Figure 5, initial pulse Vst is provided for down the gate terminal of the reverser device Tr_R in the illusory level STn+1.As a result, reverser device Tr_R conducting, and the reverser device Tr_R of the reverse voltage V_R of high state by conducting offers set node Q.Therefore, aaset bit node Q charges, and is connected to last drag switch device Trpu and the 3rd switching element T r3 conducting thus of the set node Q after the charging by its gate terminal.

Sparking voltage VSS offers reset node QB by the 3rd switching element T r3 of conducting.On the other hand, because second switch device Tr2 is by always keeping conducting as the charging voltage VDD of the dc voltage of high state, so charging voltage VDD offers reset node QB by second switch device Tr2.As a result, the sparking voltage VSS of the charging voltage VDD of the high state by second switch device Tr2 output and the low state by the 3rd switching element T r3 output is provided for reset node QB together.At this moment, because the size of the 3rd switching element T r3 is set to larger than the size of second switch device Tr2, so the sparking voltage VSS of reset node QB by the low state that provides via the 3rd switching element T r3 discharges.Therefore, pull down switch device Trpd and the first switching element T r1 that is connected to reset node QB after the discharge by its gate terminal ends.

On the other hand since in the first initial time section Ts not from the output of n level STn, the interior forward switching element T r_F remain off of the following illusory level STn+1 of institute.By this way, in the first initial time section Ts, following illusory level STn+1 set.Simultaneously, in the first initial time section Ts, the last illusory level ST0 that provides initial pulse Vst resets, and this point shall be described in more detail below.

That is to say that as shown in Figure 4, initial pulse Vst offers the gate terminal of the forward switching element T r_F in the illusory level ST0.As a result, the forward voltage V_F of forward switching element T r_F conducting and low state offers set node Q by the forward switching element T r_F of conducting.Therefore, aaset bit node Q discharges, and ends thus by last drag switch device Trpu and the 3rd switching element T r3 that its gate terminal is connected to the set node Q after the discharge.

Because second switch device Tr2 is by always keeping conducting as the charging voltage VDD of the dc voltage of high state, so charging voltage VDD offers reset node QB by second switch device Tr2.As a result, QB charges to reset node, and is connected to pull down switch the device Trpd and the first switching element T r1 conducting thus of the reset node QB after the charging by its gate terminal.

The first switching element T r1 of conducting provides sparking voltage VSS to set node Q, so that set node Q can more stably remain on its discharge condition.And first switching device of conducting provides sparking voltage VSS to first order ST1.By this way, in the first initial time section Ts, last illusory level ST0 resets.

Next, with the operation of describing in the second initial time section T0.In the second initial time section T0, only the second illusory time clock DCLK2 remains on high state, and initial pulse Vst and all time clock CLK1～CLK4 all remain on low state.In the second initial time section T0, initial pulse Vst becomes low state from high state, and the illusory grade of interior reverser device Tr_R of STn+1 ends thus down, thereby makes that the interior set node Q of illusory down level STn+1 is unsteady.As a result, the charging voltage VDD that offers the set node Q in the following illusory level STn+1 in the first initial time section Ts remains on set node Q place, even at the second initial time section T0 also be.

Because the set node Q in the down illusory level STn+1 keeps charging by the charging voltage VDD that applies in the first initial time section Ts, last drag switch device Trpu and the 3rd switching element T r3 maintenance conducting in the following illusory level STn+1 of institute.At this moment, because the second illusory time clock DCLK2 is applied to the drain terminal of the last drag switch device Trpu of conducting, so the charging voltage VDD that charges in the unsteady set node Q place in down illusory level STn+1 amplifies by boostrap circuit.

Therefore, the second illusory time clock DCLK2 that is applied to down the drain terminal of the last drag switch device Trpu in the illusory level STn+1 stablizes output by the source terminal (lead-out terminal) of last drag switch device Trpu.This second illusory time clock DCLK2 by last drag switch device Trpu output is following illusory scanning impulse Vout2n+1.Illusory scanning impulse Vout2n+1 is provided for n level STn to be used to enable n level STn down.That is to say, be provided for the first reverser device Tr_R1, the 3rd reverser device Tr_R3 in the n level STn and each gate terminal of the second reverser device Tr_R2 from the following illusory scanning impulse Vout2n+1 of down illusory level STn+1 output.

Then, the first reverser device Tr_R1, the 3rd reverser device Tr_R3 and the second reverser device Tr_R2 conducting, thus make the reverse voltage V_R of high state to be applied to the first set node Q1 by the first reverser device Tr_R1 of conducting.The result, the first set node Q1 is charged, and by its gate terminal be connected to the first set node Q1 after the charging first on drag switch device Trpu1, the 3rd switching element T r3, the 6th switching element T r6 and the 15 switching element T r15 conducting thus.Sparking voltage VSS is provided for the first reset node QB1 by the 3rd switching element T r3 of conducting, thereby the first reset node QB1 is discharged.As a result, being connected to first of the first reset node QB1 pull down switch device Trpd3 and the 9th switching element T r9 of device Trpd1, the first switching element T r1, the 3rd that pull down switch by its gate terminal ends thus.

On the other hand, owing to remain on high state, provide the 4th switching element T r4 maintenance conducting of an AC voltage Vac1 at first frame period at first frame period the one AC voltage Vac1.The one AC voltage Vac1 offers the first common node CN1 of n level STn by the 4th switching element T r4 of conducting.At this moment, the sparking voltage VSS of the output of the 6th switching element T r6 by conducting also is provided for the first common node CN1.That is to say that an AC voltage Vac1 of high state and the sparking voltage VSS of low state are provided for the first common node CN1 together.

Significantly, because the size that provides the size of the 6th switching element T r6 of sparking voltage VSS to be set to larger than the 4th switching element T r4 that an AC voltage Vac1 is provided, so at first common node CN1 place maintenance sparking voltage VSS.On the other hand, the sparking voltage VSS that closes device Tr7 output by the minion of conducting is further provided to the first common node CN1, and this names a person for a particular job and is described afterwards.As a result, the first common node CN1 is discharged, and end thus by the 5th switching element T r5 that its gate terminal is connected to the first common node CN1 after the discharge.

On the other hand, in the second initial time section T0, the reverse voltage V_R of high state offers the second set node Q2 by the second reverser device Tr_R2 of conducting.The result, the second set node Q2 is charged, and by its gate terminal be connected to the second set node Q2 after the charging second on drag switch device Trpu2, the 11 switching element T r11, the 14 switching element T r14 and minion close device Tr7 conducting thus.Sparking voltage VSS offers the second reset node QB2 by the 11 switching element T r11 of conducting, thereby the second reset node QB2 is discharged.As a result, being connected to the 4th of the second reset node QB2 pull down switch device Trpd2 and the second switch device Tr2 of device Trpd4, the tenth switching element T r10, second that pull down switch by its gate terminal ends.

On the other hand, owing to remain on low state, provide the twelvemo pass device Tr12 remain off of the 2nd AC voltage Vac2 at first frame period at first frame period the 2nd AC voltage Vac2.

The sparking voltage VSS of the 15 switching element T r15 output by conducting is provided for the second common node CN2.As a result, the second common node CN2 is discharged, and end by the 13 switching element T r13 that its gate terminal is connected to the second common node CN2 after the discharge.

On the other hand, in the second initial time section T0, the reverse voltage V_R of high state is applied to the 3rd common node CN3 by the 3rd reverser device Tr_R3 of conducting.As a result, the 3rd common node CN3 is charged, and close device Tr8 conducting thus by gauge tap device Tr_C and octavo that its gate terminal is connected to the 3rd common node CN3 after the charging.The gauge tap device Tr_C of conducting provides sparking voltage VSS to the first reset node QB1, so that the first reset node QB1 can stably remain on its discharge condition.And the octavo of conducting is closed device Tr8 and is provided sparking voltage VSS to the second reset node QB2, so that the second reset node QB2 can more stably remain on its discharge condition.By this way, in the second initial time section T0, the first and second set node Q1 and the Q2 of n level STn charged, and the first and second reset node QB1 and the QB2 of n level STn discharged, enable n level STn thus.

Next, with the operation that is described in the very first time section T1.As shown in Figure 3, in very first time section T1, only the 4th time clock CLK4 remains on high state, and remaining time clock CLK1～CLK3 comprises that initial pulse Vst all remains on low state.

Because the second set node Q2 in the n level STn keeps charging by the charging voltage VDD that applies in the first initial time section Ts, so drag switch device Trpu2 keeps conducting on second in the n level STn.At this moment and since the 4th time clock CLK4 be applied to conducting second on the drain terminal of drag switch device Trpu2, so the charging voltage VDD that charges in the second set node Q2 place of floating in n level STn amplifies by boostrap circuit.

Therefore, the 4th time clock CLK4 that is applied to the drain terminal of drag switch device Trpu2 on second in the n level STn stablizes output by the source terminal (the second lead-out terminal 111b) of drag switch device Trpu2 on second.This 4th time clock CLK4 by drag switch device Trpu2 output on second is the m scanning impulse.The m scanning impulse is provided for m select lines, (n-1) level STn-1 and down illusory level STn+1.As a result, in very first time section T1, the m select lines is driven, and (n-1) level STn-1 is enabled, and down illusory level STn+1 is disabled.Carry out the operation that in very first time section T1, enables (n-1) level STn-1 according to the mode identical with the aforesaid operations that in the first initial time section Ts, enables n level STn.

On the other hand, in very first time section T1, the m scanning impulse of exporting from n level STn is provided for down illusory level STn+1 to forbid down illusory level STn+1.Hereinafter this deactivation operation will be described in further detail.

That is to say that the m scanning impulse is provided for down the gate terminal of the forward switching element T r_F in the illusory level STn+1.As a result, forward switching element T r_F conducting, and the forward voltage V_F of low state offers down the set node Q of illusory level STn+1 by the forward switching element T r_F of conducting.Therefore, aaset bit node Q discharges, and ends thus by last drag switch device Trpu and the 3rd switching element T r3 that its gate terminal is connected to the set node Q after the discharge.

Because the 3rd switching element T r3 in the down illusory level STn+1 is cut off, so the charging voltage VDD of the high state by second switch device Tr2 output is provided for down the illusory grade of reset node QB in the STn+1.So QB charges to reset node, and be connected to pull down switch the device Trpd and the first switching element T r1 conducting thus in the following illusory level STn+1 of the reset node QB after the charging by its gate terminal.The device Trpd that pulls down switch of conducting provides sparking voltage VSS to n level STn.

Set node Q in the downward illusory level STn+1 of the first switching element T r1 in the illusory down level STn+1 provides sparking voltage VSS, thereby set node Q is more stably remained on its discharge condition.

Next, with the operation that is described in the second time period T2.In the second time period T2, only the 4th and the 3rd time clock CLK4 and CLK3 remain on high state, and remaining time clock CLK2 and CLK1 comprise that initial pulse Vst all remains on low state.Drag switch device Trpu2 exports the m scanning impulse in response to the 4th time clock CLK4 with complete form in the n level STn second.In this second time period T2, enable (n-1) level STn-1 by the m scanning impulse.

And drag switch device Trpu1 begins to export (m-1) scanning impulse in response to the 3rd time clock CLK3 on first in the n level STn.That is to say, because the first set node Q1 in the n level STn keeps charging by the charging voltage VDD that applies in the first initial time section Ts, so drag switch device Trpu1 keeps conducting on first in the n level STn.At this moment and since the 3rd time clock CLK3 be applied to conducting first on the drain terminal of drag switch device Trpu1, so the charging voltage VDD that charges in the first set node Q1 place of floating in n level STn amplifies by boostrap circuit.

Therefore, the 3rd time clock CLK3 that is applied to the drain terminal of drag switch device Trpu1 on first in the n level STn stablizes output by the source terminal (the first lead-out terminal 111a) of drag switch device Trpu1 on first.This 3rd time clock CLK3 by drag switch device Trpu1 output on first is (m-1) scanning impulse.(m-1) scanning impulse is provided for (m-1) select lines to drive (m-1) select lines.

Next, with the operation of describing in the 3rd time period T3.In the 3rd time period T3, only the 3rd and second clock pulse CLK3 and CLK2 remain on high state, and remaining time clock CLK4 and CLK1 comprise that initial pulse Vst all remains on low state.Drag switch device Trpu1 exports (m-1) scanning impulse in response to the 3rd time clock CLK3 with complete form in the n level STn first.This (m-1) scanning impulse is provided for (m-1) select lines.And drag switch device Trpu2 begins to export (m-2) scanning impulse in response to second clock pulse CLK2 on second in (n-1) level STn-1.In this 3rd time period T3, (m-2) scanning impulse from (n-1) level STn-1 is provided for (m-2) select lines beginning to drive (m-2) select lines, and this (m-2) scanning impulse also is provided for (n-2) level to enable (n-2) level.

Next, with the operation that is described in the 4th time period T4.In the 4th time period T4, only second the and first time clock CLK2 and CLK1 remain on high state, and remaining time clock CLK4 and CLK3 comprise that initial pulse Vst all remains on low state.Drag switch device Trpu2 exports (m-2) scanning impulse in response to second clock pulse CLK2 with complete form in (n-1) level STn-1 second.This (m-2) scanning impulse is provided for (m-2) select lines and (n-3) level.And drag switch device Trpu1 is in response to first time clock CLK1 output (m-3) scanning impulse on first in (n-1) level STn-1.This (m-3) scanning impulse is provided for (m-3) select lines beginning to drive (m-3) select lines, and this (m-3) scanning impulse also is provided for n level STn to forbid n level STn.

The operation of forbidding n level STn will be described in more detail below.That is to say that (m-3) scanning impulse is provided for n level the STn interior first forward switching element T r_F1, the second forward switching element T r_F2 and each gate terminal of the 3rd forward switching element T r_F3.As a result, the first forward switching element T r_F1, the second forward switching element T r_F2 and the 3rd forward switching element T r_F3 conducting.

The first forward switching element T r_F1 of the forward voltage V_F of low state by conducting offers the first set node Q1 in the n level STn.The result, the first set node Q1 is discharged, and by its gate terminal be connected to the first set node Q1 after the discharge first on drag switch device Trpu1, the 3rd switching element T r3, the 6th switching element T r6 and the 15 switching element T r15 end thus.And the second forward switching element T r_F2 of the forward voltage V_F of low state by conducting offers the second set node Q2 in the n level STn.The result, the second set node Q2 is discharged, and by its gate terminal be connected to the second set node Q2 after the discharge second on drag switch device Trpu2, the 11 switching element T r11, the 14 switching element T r14 and minion close device Tr7 and end thus.And the three forward switching element T r_F3 of the forward voltage V_F of low state by conducting offers the 3rd common node CN3 in the n level STn.As a result, the 3rd common node CN3 is discharged, and be connected to the gauge tap device Tr_C of the 3rd common node CN3 after the discharge and octavo by its gate terminal and close device Tr8 and end thus.

Because the 6th and minion in the n level STn are closed device Tr6 and Tr7 ends, so the AC voltage Vac1 by the 4th switching element T r4 output is provided for the first common node CN1 in the n level STn.As a result, the first common node CN1 is charged, and be connected to the 5th switching element T r5 conducting thus of the first common node CN1 after the charging by its gate terminal.

Then, the five switching element T r5 of an AC voltage Vac1 by conducting offers the first reset node QB1 among the n level STn.The result, the first reset node QB1 is charged, and be connected to first among the n level STn of the first reset node QB1 after the charging pull down switch device Trpd1, the 3rd pull down switch device Trpd3, the first switching element T r1 and the 9th switching element T r9 conducting thus by its gate terminal.

The first switching element T r1 of sparking voltage VSS by conducting offers the first set node Q1 among the n level STn, thereby makes the set node Q1 that wins can more stably remain on its discharge condition.And the nine switching element T r9 of sparking voltage VSS by conducting offers the second set node Q2 among the n level STn, thereby makes the second set node Q2 can more stably remain on its discharge condition.

By this way, in the 4th time period T4, by to the first and second set node Q1 in the n level STn with Q2 discharges, the first reset node QB1 in the n level STn is charged, and the second reset node QB2 in the n level STn is discharged, make that n level STn can be disabled.

As mentioned above, in the 4th time period T4, device Trpd1 and the 3rd device Trpd3 conducting that pulls down switch because first of n level STn pulls down switch, so first pulls down switch device Trpd1 by first lead-out terminal 111a output sparking voltage VSS, to provide sparking voltage VSS to (m-1) select lines, and the 3rd pulls down switch device Trpd3 by second lead-out terminal 111b output sparking voltage VSS, to provide sparking voltage VSS to m select lines, (n-1) level STn-1 and down illusory level STn+1.And, drive subsequently (n-4) level in proper order to last illusory level ST0 according to mode same as described above.

On the other hand, in second frame period, an AC voltage Vac1 bears, and the 2nd AC voltage Vac2 is positive.Therefore, at the forbidding in second frame period in the time period, the first reset node QB1 of each grade ST1～STn is discharged and its second reset node QB2 is charged.Therefore, at the forbidding in first frame period in the time period, pull down switch device Trpd2 and Trpd4 of the second and the 4th of each grade ST1～STn operated.

By this way, according to the present invention, can control the scanning impulse outbound course of each grade by direction of scanning controller SDC.On the other hand, last illusory level and down each among illusory grade of ST0 and the STn+1 can have and the first order each identical circuit structure in n level ST1～STn.

Fig. 7 is the block diagram that illustrates according to the structure of the shift register of second illustrative embodiments of the present invention.Shift register second embodiment of the invention comprises n level ST1～STn and two illusory level ST0 and STn+1, as shown in Figure 7.At a frame period, level ST1～STn respectively exports two scanning impulses.Each grade ST1～STn utilizes scanning impulse to drive coupled select lines, and utilizes the operation of scanning impulse control downstream stage and upstream stage.As shown in Figure 2, provide signal to shift register, as shown in Figure 3, provide signal to shift register according to second illustrative embodiments in the reverse drive mode according to second illustrative embodiments in the forward drive mode.And, according to the last illusory level ST0 in the shift register of second embodiment and illusory down level STn+1 respectively with according to the last illusory level ST0 in the shift register of first embodiment with illusory grade of STn+1 is identical down.

In general, except the inter-stage signal transfer system, according to the shift register of second illustrative embodiments with identical according to the shift register of first embodiment.To be described this difference hereinafter.

At first, enable operation will be described.Under the forward drive pattern, each grade ST1～STn in response to from it upstream stage two scanning impulses and be enabled.That is to say that level ST1～STn respectively comprises two sub levels.In these two sub levels of an output front scanning impulse one is enabled in response to one of front from two scanning impulses of upstream stage output.Comparatively speaking, another in these two sub levels of the scanning impulse in output back is enabled in response to one of back from two scanning impulses of upstream stage output.Specifically, in two sub levels in the j level of an output front scanning impulse one is enabled in response to one of front from two scanning impulses of (j-1) level output, and in two sub levels in the j level of the scanning impulse in output back another is enabled in response to one of back from two scanning impulses of (j-1) level output.

For example, export in two sub levels among the third level ST3 of the 5th scanning impulse Vout5 one in response to from the 3rd scanning impulse Vout3 of second level ST2 and be enabled, and export in two sub levels among the third level ST3 of the 6th scanning impulse Vout6 another in response to from the 4th scanning impulse Vout4 of second level ST2 and be enabled.Yet under the forward drive pattern, top or first order ST1 is in response to being enabled from the last illusory scanning impulse Vout0 of last illusory level ST0.Last illusory level ST0 is in response to being enabled from the initial pulse Vst of initial conveyer line.

Comparatively speaking, under reverse drive mode, each grade ST1～STn in response to from it downstream stage two scanning impulses and be enabled.That is to say that level ST1～STn respectively comprises two sub levels.In two sub levels of an output front scanning impulse one is enabled in response to one of front from two scanning impulses of downstream stage output.Comparatively speaking, another in two sub levels of the scanning impulse in output back is enabled in response to one of back from two scanning impulses of downstream stage output.Specifically, in two sub levels in the j level of an output front scanning impulse one is enabled in response to one of front from two scanning impulses of (j+1) level output, and in two sub levels in the j level of the scanning impulse in output back another is enabled in response to one of back from two scanning impulses of (j+1) level output.For example, export in two sub levels among the third level ST3 of the 5th scanning impulse Vout5 one in response to from the 7th scanning impulse Vout7 of fourth stage ST4 and be enabled, and export in two sub levels among the third level ST3 of the 6th scanning impulse Vout6 another in response to from the 8th scanning impulse Vout8 of fourth stage ST4 and be enabled.

Yet under reverse drive mode, end level or n level STn are in response to being enabled from the following illusory scanning impulse Vout2n+1 that descends illusory level STn+1.Down illusory level STn+1 is in response to being enabled from the initial pulse Vst of initial conveyer line.

Next, deactivation operation will be described.Under the forward drive pattern, each grade ST1～STn in response to from it two scanning impulses of downstream stage and disabled.That is to say that level ST1～STn respectively comprises two sub levels.In two sub levels of the scanning impulse in output front one is disabled in response to one of front from two scanning impulses of downstream stage output.Comparatively speaking, another in two sub levels of the scanning impulse in output back is disabled in response to one of back from two scanning impulses of downstream stage output.Specifically, in two sub levels in the j level of an output front scanning impulse one is disabled in response to one of front from two scanning impulses of (j+1) level output, and in two sub levels in the j level of the scanning impulse in output back another is disabled in response to one of back from two scanning impulses of (j+1) level output.For example, export in two sub levels among the third level ST3 of the 5th scanning impulse Vout5 one in response to from the 7th scanning impulse Vout7 of fourth stage ST4 and disabled, and export in two sub levels among the third level ST3 of the 6th scanning impulse Vout6 another in response to from the 8th scanning impulse Vout8 of fourth stage ST4 and disabled.

Yet under the forward drive pattern, end level or n level STn are in response to from the following illusory scanning impulse Vout2n+1 of following illusory level STn+1 and disabled.Down illusory level STn+1 is in response to from the initial pulse Vst of initial conveyer line and disabled.

Comparatively speaking, under reverse drive mode, each grade ST1～STn in response to from it two scanning impulses of upstream stage and disabled.That is to say that level ST1～STn respectively comprises two sub levels.In two sub levels of the scanning impulse in output front one is disabled in response to one of front from two scanning impulses of upstream stage output.Comparatively speaking, another in two sub levels of the scanning impulse in output back is disabled in response to one of back from two scanning impulses of upstream stage output.Specifically, in two sub levels in the j level of an output front scanning impulse one is disabled in response to one of front from two scanning impulses of (j-1) level output, and in two sub levels in the j level of the scanning impulse in output back another is disabled in response to one of back from two scanning impulses of (j-1) level output.For example, export in two sub levels among the third level ST3 of the 5th scanning impulse Vout5 one in response to from the 3rd scanning impulse Vout3 of second level ST2 and disabled, and export in two sub levels among the third level ST3 of the 6th scanning impulse Vout6 another in response to from the 4th scanning impulse Vout4 of second level ST2 and disabled.

Yet under reverse drive mode, top or first order ST1 is in response to from the last illusory scanning impulse Vout0 of last illusory level ST0 and disabled.Last illusory level ST0 is in response to from the initial pulse Vst of initial conveyer line and disabled.

Fig. 8 is the circuit diagram of each grade ST1～STn among Fig. 7.Except the scanning impulse of each gate terminal of offering the second forward switching device, the first reverser device and the 3rd reverser device, the structure of Fig. 8 is basic identical with the structure of Fig. 6.

According to the structure of Fig. 8, the second forward switching element T r_F2 in the k level is switched on/ends in response to one of back from two scanning impulses of (k-1) level output, and is connected between the forward voltage line and the second set node Q2.For this reason, the gate terminal of the second forward switching element T r_F2 in the k level is connected to the second lead-out terminal 111b of (k-1) level, and drain terminal is connected to the forward voltage line, and source terminal is connected to the second set node Q2.

The first reverser device Tr_R1 in the k level is switched on/ends in response to one of front from two scanning impulses of (k+1) level output, and is connected between the first set node Q1 and the reverse voltage line.For this reason, the gate terminal of the first reverser device Tr_R1 in the k level is connected to the first lead-out terminal 111a of (k+1) level, and drain terminal is connected to the first set node Q1, and source terminal is connected to the reverse voltage line.

The 3rd reverser device Tr_R3 in the k level is switched on/ends in response to one of front from two scanning impulses of (k+1) level output, and is connected between reverse voltage line and the 3rd public electrode CN3.For this reason, the gate terminal of the 3rd reverser device Tr_R3 is connected to the first lead-out terminal 111a of (k+1) level, and drain terminal is connected to the reverse voltage line, and source terminal is connected to the 3rd common node CN3.

Can be arranged in the following liquid crystal display according to shift register of the present invention.Fig. 9 A and Fig. 9 B are respectively the synoptic diagram that has fluorescent light liquid crystal display backlight and have the liquid crystal display of LED backlight.

Above-mentioned shift register SR is installed in the non-display area of liquid crystal panel 701.For the liquid crystal display backlight that liquid crystal panel 701 is applied to have the fluorescent lamp drive type with have the driving liquid crystal display backlight of light emitting diode, need be with liquid crystal panel 701 Rotate 180s °.

For example, shown in Fig. 9 A, when liquid crystal panel 701 was installed in the liquid crystal display backlight with fluorescent lamp drive type, the first select lines GL1 was positioned at the top side of liquid crystal panel 701, and last select lines GL2n is positioned at the bottom side of liquid crystal panel 701.

Yet, when liquid crystal panel 701 is installed in when having in the driving liquid crystal display backlight of light emitting diode, owing between these two kinds of equipment, have system's difference, thereby need be with liquid crystal panel 701 Rotate 180s °.In this case, the first select lines GL1 is positioned at the bottom side of liquid crystal panel 701, and last select lines GL2n is positioned at the top side of liquid crystal panel 701.

The data output sequence of tentation data driver does not change, no matter the position of the first select lines GL1 of liquid crystal panel 701 how, all must at first drive the top select lines of the screen of liquid crystal panel 701, thus on the screen of liquid crystal panel 701 normal display image.

Specifically, shown in Fig. 9 A, the select lines of liquid crystal panel 701 must be begun to drive from the first select lines GL1 of the top side that is positioned at liquid crystal panel 701, and shown in Fig. 9 B, the select lines of liquid crystal panel 701 must be begun to drive from the last select lines GL2n of the top side that is positioned at liquid crystal panel 701.

According to of the present invention first or the use of the second shift register SR can satisfy the driving order of these two kinds of equipment.For example, in the liquid crystal display shown in Fig. 9 A,, can begin to drive the select lines of liquid crystal panel 701 from the first select lines GL1 of the top side that is positioned at liquid crystal panel 701 by operate shift register SR under the forward drive pattern.Comparatively speaking, in the liquid crystal display shown in Fig. 9 B,, can begin to drive the select lines of liquid crystal panel 701 from the last select lines GL2n of the top side that is positioned at liquid crystal panel 701 by operate shift register SR under reverse drive mode.

On the other hand, the reference marker D-IC that the front is not described represents to drive the data-driven integrated circuit (IC) of the data line of liquid crystal panel, T represents that the band that data-driven IC is installed carries encapsulation (TCP), and PCB represents to be equipped with the data pcb of timing controller TC.A plurality of TCP T are connected between data pcb PCB and liquid crystal panel 701.

Can be clear that from the above description shift register according to the present invention has following effect.Shift register of the present invention can change the output order of level by the direction of scanning controller.Therefore, shift register of the present invention can be applicable to the display device of various models.In addition, the 3rd forward switching device and the 3rd reverser device are used for complementation is carried out in the operation each other of forward operation and reverse operating, thereby do not need extra switching device just can finish forward drive and reverse drive effectively.Therefore, can reduce the interior zone of shift register.

To those skilled in the art clearly, under the condition that does not depart from the spirit or scope of the present invention, can make various modifications and variations to shift register of the present invention.Thereby, be intended to contain modification of the present invention and modification under the condition of the present invention in the scope that falls into claims and equivalent thereof.

Claims

1, a kind of shift register, this shift register comprises:

A plurality of scanning stages, it is to the pulse of many select lines output scannings;

The first illusory level, its in described a plurality of scanning stages first is exported the first illusory scanning impulse; And

The second illusory level, its last in described a plurality of scanning stages is exported the second illusory scanning impulse.

2, shift register according to claim 1, wherein, the described first illusory scanning impulse carries out set according to direction in described a plurality of scanning stages first and according to inverse direction in described a plurality of scanning stages first is resetted, and the described second illusory scanning impulse resets in described a plurality of scanning stages last according to described direction and according to described inverse direction in described a plurality of scanning stages last carried out set.

3, shift register according to claim 1, wherein, described a plurality of scanning stages respectively are connected to two select liness.

4, shift register according to claim 1, wherein, each exports at least one scanning impulse to previous stage or next stage described a plurality of scanning stages.

5, shift register according to claim 4, wherein, each exports two scanning impulses in proper order to described previous stage or described next stage described a plurality of scanning stages.

6, shift register according to claim 1, wherein, described a plurality of scanning stage respectively comprises the direction of scanning controller, and this direction of scanning controller is in response to optionally exporting forward voltage and the reverse voltage with opposite voltage level from the scanning impulse of prime and back level.

7, shift register according to claim 5, wherein, described a plurality of scanning stage also respectively comprises Node Controller, and this Node Controller is in response to the signal condition of controlling a plurality of set nodes and a plurality of reset nodes from the output signal of described direction of scanning controller.

8, shift register according to claim 6, wherein, described a plurality of scanning stage also respectively comprises output unit, this output unit is based on the voltage of described a plurality of set nodes and described a plurality of reset nodes and order is exported first scanning impulse and second scanning impulse, and provides described first scanning impulse and described second scanning impulse to described back level and described prime respectively.

9, shift register according to claim 1, wherein, the described first illusory scanning stage comprises:

The first direction of scanning controller, it optionally exports forward voltage and the reverse voltage with opposite voltage level in response to outside initial pulse;

The first node controller, it is in response to the first node of controlling the described first illusory level from the output signal of the described first direction of scanning controller and the signal condition of Section Point; And

First output unit, it exports the described first illusory scanning impulse based on the voltage of the described first node of the described first illusory level and described Section Point, and in described a plurality of scanning stages first provides the described first illusory scanning impulse.

10, shift register according to claim 1, wherein, the described second illusory scanning stage comprises:

The second direction of scanning controller, it optionally exports forward voltage and the reverse voltage with opposite voltage level in response to outside initial pulse;

The Section Point controller, it is in response to the first node of controlling the described second illusory level from the output signal of the described second direction of scanning controller and the signal condition of Section Point; And

Second output unit, it exports the described second illusory scanning impulse based on the voltage of the described first node of the described second illusory level and described Section Point, and in described a plurality of scanning stages last provides the described second illusory scanning impulse.

11, shift register according to claim 1, wherein,

In described a plurality of scanning stage each in response in a plurality of time clock any two and the order export described scanning impulse, described a plurality of time clock are out-phase each other,

The described first illusory level is exported the described first illusory scanning impulse in response to the first illusory time clock that comprises in described a plurality of time clock any one, and

The described second illusory level is exported the described second illusory scanning impulse in response to the second illusory time clock that comprises in described a plurality of time clock another.