KR101050286B1 - Integrated Gate Driver - Google Patents

Abstract

An embedded gate driver is disclosed that reduces costs, simplifies the process, and improves reliability.

The built-in gate driver of the present invention includes a plurality of shift registers embedded in a display panel and outputting output signals sequentially shifted according to the start signal, each shift register being between a start signal input line and a node. A first transistor connected to charge the start signal to the node; A third transistor connected between the node, a clock signal input line, and a gate line to output a predetermined clock signal as the output signal according to a start signal charged in the node; A second transistor connected between the node and a supply voltage input line to initialize the node by a predetermined supply voltage; And a fourth transistor connected between the clock signal input line and the gate line to discharge the output signal.

Liquid Crystal Display, Built-in Gate Driver, Transistor

Description

Built-in gate driver             

1 is a block diagram illustrating a gate driver of a general liquid crystal display device.

FIG. 2 is a diagram showing a detailed circuit configuration of the shift register shown in FIG.

3 is a diagram illustrating a voltage waveform of the shift register shown in FIG. 2;

4 is a diagram illustrating a detailed circuit configuration of a shift register included in an embedded gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is a view showing voltage waveforms of the shift register shown in FIG. 4; FIG.

FIG. 6 is a diagram illustrating a detailed circuit configuration of a shift register provided in an embedded gate driver according to another exemplary embodiment of the present invention. FIG.

<Explanation of symbols for the main parts of the drawings>

31, 32: clock signal input line 33: start pulse input line

34: supply voltage input line

35: output signal input line of next shift register

41, 45: control unit 43, 47: output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to an embedded gate driver which reduces cost, simplifies a process, and improves reliability.

In general, an apparatus for displaying an image by driving pixels arranged in an active matrix form, such as a liquid crystal display (LCD) or an organic light emitting diode (OLED), is actively studied. It is becoming.

In particular, the liquid crystal display device displays a desired image by supplying data voltages corresponding to image information to pixels arranged in an active matrix to adjust light transmittance of the liquid crystal layer. To this end, the liquid crystal display includes a liquid crystal panel in which pixels are arranged in a matrix form, a gate driver and a data driver for driving the liquid crystal panel.

Recently, in order to reduce manufacturing costs, an embedded liquid crystal display device in which the gate driver and / or the data driver is embedded on the liquid crystal panel has been developed.

In such a built-in liquid crystal display device, when the liquid crystal panel is manufactured, the gate driver is simultaneously manufactured. The data driver may or may not be embedded in the embedded liquid crystal display.

The gate driver includes a plurality of shift registers for sequentially supplying an output signal to each gate line. Of course, a plurality of shift registers may be provided in the data driver.

1 is a block diagram illustrating a gate driver of a general liquid crystal display device.

As illustrated in FIG. 1, the gate driver of the liquid crystal display includes a plurality of shift registers ST1 to STn cascading to each other. The plurality of shift registers ST1 to STn are connected to a start pulse SP input line 5 or an output line (ie, a gate line) connected to an output side of a previous shift register, and a four-phase clock signal ( C1 to C4) are connected to three clock signal input lines of the input lines 1, 2, 3, and 4; As shown in FIG. 3, the four-phase clock signals C1 to C4 are sequentially supplied in a phase delayed form by one clock. Each of the shift registers ST1 to STn shifts the start pulse SP by one clock using three clock signals among the four-phase clock signals C1 to C4. The output signals Vg1 to Vgn respectively output from the shift registers ST1 to STn are sequentially supplied to the corresponding gate lines GL1 to GLn, and are also supplied as start pulses of the next shift register.

As such, the gate driver includes a plurality of shift registers ST1 to STn connected to the gate lines GL1 to GLn, respectively. The shift registers ST1 to STn are cascaded to supply the output signals sequentially to the gate lines GL1 to GLn by shifting the start pulse by one clock.

Specifically, the start pulse SP is input to the first shift register ST1, and the output signals Vg1 to Vgn-1 of the previous shift register are input to the second to nth shift registers ST2 to STn. Is entered. As illustrated in FIG. 3, the shift registers ST1 to STn receive three clock signals among the first to fourth clock signals C1 to C4 which are sequentially delayed in phase. The shift registers ST1 to STn sequentially output the output signals Vg1 to Vgn by shifting the start pulse SP by one clock using the three clock signals.

FIG. 2 is a diagram showing a detailed circuit configuration of the shift register shown in FIG. Although only the first shift register ST1 is representatively shown in FIG. 2, the rest of the shift registers ST2 to STn are merely modifications of the first shift register ST1, and thus, the first shift register ST1 may be used. Will be fully understood.

Referring to FIG. 2, the first shift register ST1 may be connected to the first control unit 11 that controls the Q node according to the fourth clock signal C4 and the third clock signal C3 or the start pulse SP. And a second control unit 13 for controlling the QB node, and an output for selecting and outputting any one of the first clock signal C1 or the first supply voltage VSS according to the voltage of the Q node or the voltage of the QB node. The part 15 is provided.

The first control unit 11 controls the Q node to output the first clock signal C1 through the sixth transistor T6 of the output unit 15. The output first clock signal C1 is supplied to the first output signal Vg1 through the first gate line GL1. To this end, the first control unit 11 includes a first transistor T1 connected to the start pulse SP input line 5, a first transistor T1, and a fourth clock signal C4 input line 4. ) And a second transistor T2 connected between the Q node.

The second control unit 13 controls the QB node to output the first supply voltage VSS through the seventh transistor T7 of the output unit 15. The output first supply voltage VSS is supplied to the first output signal Vg1 through the first gate line GL1. To this end, the second controller 13 may include a fourth transistor T4 connected between the second supply voltage VDD input line 6, the third clock signal C3 input line 3, and the QB node. And a fifth transistor T5 connected between the fourth transistor T4, the start pulse SP input line 5, and the first supply voltage VSS input line 7.

The output unit 15 supplies a sixth transistor T6 that selects and supplies the first clock signal C1 to the first gate line GL1 according to the voltage of the Q node and a first supply according to the voltage of the QB node. A seventh transistor T7 selects and supplies a voltage VSS to the first gate line GL1.

In addition, the first control unit 11 is connected between the Q node, the QB node, and the first supply voltage VSS input line 7 to control the QB node in dual operation with the seventh transistor T7. (T3) is further provided.

As illustrated in FIG. 3, first to fourth clock signals C1 to C4 having a form in which phase delays are sequentially performed by one clock are provided to the first shift register ST1 having such a configuration. Here, the fourth clock signal C4 has a phase synchronized with the start pulse SP. The start pulse SP and the first to fourth clock signals C1 to C4 have a voltage swinging from -5V to 20V. In other words, it is normally applied at -5V and then applied at 20V while the pulse is turned on. Let -5V be the low voltage and 20V be the high voltage. The first supply voltage VSS has a negative polarity voltage (-5V), whereas the second supply voltage VDD has a positive polarity voltage 20V. The first and second supply voltages VSS and VDD always have a constant DC voltage. The fourth clock signal C4 section is the S1 period, the first clock signal C1 section is the S2 period, the second clock signal C2 section is the S3 period, and the third clock signal C3 section is the S4 period Respectively.

The operation of the first shift register ST1 will be described with reference to the driving waveform as follows.

When the start pulse SP and the fourth clock signal C4 become high at the same time in the S1 period, the first and second transistors T1 and T2 are turned on to charge the Q node with a voltage of about 20V. . As a result, the sixth transistor T6 having the gate terminal connected to the Q node is gradually turned on. In addition, the fifth transistor T5 is turned on by the start pulse SP in the high state, and a voltage of −5 V from the first supply voltage VSS input line 7 is charged to the QB node. Accordingly, the third and seventh transistors T3 and T7 having gate terminals connected to the QB node are turned off. As a result, a voltage of −5 V of the first clock signal C1, which is maintained at the low state through the turned-on sixth transistor T6, is supplied to the gate line GL1 of the first shift register ST1 to be low. -5V).

When the start pulse SP and the fourth clock signal C4 are in the low state and the first clock signal C1 is in the high state in the S2 period, an internal portion formed between the gate terminal and the source terminal of the sixth transistor T6. Bootstrapping occurs under the influence of capacitance (Cgs), and the Q node charges up to about 40V, resulting in a high state. This bootstrapping phenomenon is possible because all of the first to third transistors T1 to T3 are turned off and the Q node is in a floating state. Accordingly, the sixth transistor T6 is surely turned on so that the high voltage 20V of the first clock signal C1 is rapidly charged to the first gate line GL1 to be charged to the high state of 20V. do.

When the first clock signal C1 becomes low in the S3 period and the second clock signal C2 becomes high, the voltage of the Q node drops back to about 20V and passes through the turned-on sixth transistor T6. The low voltage (-5V) of the first clock signal C1 is charged in the first gate line GL1.

When the third clock signal C3 becomes high in the period S4, the fourth transistor T4 is turned on so that the second supply voltage VDD of 20V is charged to the QB node so that the third and seventh transistors T3 are turned on. , T7) is turned on. Accordingly, the voltage of about 20 V charged to the Q node via the turned-on third transistor T3 is changed to −5 V, and the first supply voltage VSS is passed through the turned-on seventh transistor T7. A voltage of −5 V supplied from the input line 7 is charged to the first gate line GL1 in a low state. This state is maintained until the start pulse SP and the fourth clock signal C4 are supplied again in the next frame. That is, the high voltage is output through the sixth transistor T6 by the Q node charged to 40V during the S2 period. At this time, the QB node is charged with a low voltage of -5V. From the S4 period until the start pulse SP and the fourth clock signal C4 are supplied in the next frame, the low voltage is maintained at the Q node, and the high voltage is applied to the QB node. As a result, the high voltage is maintained at the QB node during most of the period of one frame. Therefore, when it is operated in such a state for a long time, deterioration occurs in the seventh transistor T7 having the gate terminal connected to the QB node, thereby degrading transistor characteristics. In severe cases, a fatal damage may occur to the seventh transistor T7 and the liquid crystal display may not operate. As a result, a desired image is not displayed on the screen, resulting in a deterioration in image quality.

On the other hand, the second shift register ST2 has the same configuration as the first shift register ST1 described above. However, the second shift register ST2 outputs the clock signals (for example, C1, C2, and C4) delayed by one clock in the first shift register ST1 and the high state of the first shift register ST1. The signal Vg1 is used to operate like the first shift register ST1. Accordingly, the second shift register ST2 outputs the high output signal Vg2 shifted by one clock relative to the first shift register ST1.

The remaining shift registers ST3 to STn are operated in the same manner as described above. Accordingly, the output signals Vg3 to Vgn in the high state are sequentially output to the corresponding gate lines GL3 to GLn.

That is, the output signals Vg1 to Vgn of the high state are sequentially outputted by the shift registers ST1 to STn connected to the gate lines GL1 to GLn for one frame, and the process is repeated for each frame. To operate.

In the above-described gate driver, the time (20 ms) for supplying the output signals Vg1 to Vgn in the high state to the gate lines GL1 to GLn for one frame period (16.67 ms) becomes very short. On the other hand, the output signals Vg1 to Vgn in the low state are supplied to the gate lines GL1 to GLn for most of the time (90% or more) of one frame period. At this time, while the output signals Vg1 to Vgn in the low state are supplied, the high voltage (that is, the voltage of the QB node) is maintained at the gate terminal of the seventh transistor T7. That is, in order to maintain the low voltage in the gate lines GL1 to GLn for most of the time in each frame, the high voltage must be maintained at the gate terminal of the seventh transistor T7. As this process is continuously repeated, the stress voltage is accumulated in the seventh transistor T7 to cause deterioration. As a result of the deterioration, the threshold voltage of the seventh transistor T7 is changed and mobility is reduced. As a result, the device performance deteriorates and the operation of the seventh transistor T7 is not accurately controlled, thereby preventing the desired image from being displayed on the screen, leading to deterioration in image quality. In addition, there is a problem that the life of the liquid crystal display device is shortened by such deterioration.

On the other hand, in general, transistors T1 to T7 included in the embedded gate driver occupy a huge area, unlike thin film transistors provided in the liquid crystal panel. In particular, the gate terminal of the seventh transistor T7 is mainly maintained in a high state voltage, so that the area of the seventh transistor T7 is different from other transistors, that is, the first to first to maintain the high state voltage. It is much larger than the sixth transistors T1 to T6. In addition, seven transistors are provided for each shift register of the gate driver, and the number of each shift register generally corresponds to the number of gate lines. In general, since 768 gate lines exist in an XGA-class liquid crystal display device, the number of shift registers included in the gate driver must also be 768. Therefore, a total of 768 * 7 = 5376 transistors are required in the gate driver.

Therefore, it is difficult to manufacture a large number of transistors that occupy a large area, and there is a problem that it becomes expensive. In addition, the overall area of a gate driver with many transistors occupying a large area becomes large. Such a gate driver is embedded in the liquid crystal panel. As the area of the gate driver increases, the display area in which the image is displayed is reduced, which may be a major obstacle in implementing a large area liquid crystal display.

An object of the present invention is to provide an embedded gate driver that can significantly reduce the area and size by reducing the number of transistors and also prevent malfunctions caused by stress.

According to a first preferred embodiment of the present invention for achieving the above object, an embedded gate driver includes a plurality of shift registers that are embedded in a display panel and output an output signal sequentially shifted according to a start signal. Each of the shift registers includes: a first transistor connected between a start signal input line and a node to charge the start signal to the node; A third transistor connected between the node, a clock signal input line, and a gate line to output a predetermined clock signal as the output signal according to a start signal charged in the node; A second transistor connected between the node and a supply voltage input line to initialize the node by a predetermined supply voltage; And a fourth transistor connected between the clock signal input line and the gate line to discharge the output signal.

According to a second preferred embodiment of the present invention, the embedded gate driver includes a plurality of shift registers embedded in the display panel and outputting output signals sequentially shifted according to the start signal, wherein each of the shift registers includes: A first transistor connected between a start signal input line and a node to charge the start signal to the node; A fourth transistor connected between the node and a clock signal input line and turned on by a start signal charged in the node to pass a predetermined clock signal; A third transistor connected between the clock signal input line, a fourth transistor, and a gate line and turned on by a clock signal passing through the fourth transistor to output the clock signal as the output signal; A second transistor connected between the node and a supply voltage input line to initialize the node by a predetermined supply voltage; And a fifth transistor connected between the gate terminal of the third transistor and the gate line to discharge the output signal.

According to the first and second embodiments of the present invention, the start signal may be supplied to the first shift register as a start pulse, and the remaining shift registers may be supplied as output signals output from the previous shift register.

According to the first and second embodiments of the present invention, the second transistor may be turned on by the output signal of the next shift register.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a diagram illustrating a detailed circuit configuration of a shift register included in an embedded gate driver according to an exemplary embodiment of the present invention.

As described above, the gate driver of the liquid crystal display includes a plurality of shift registers for sequentially outputting the output signals Vg1 to Vgn.

In the following description, the first shift register ST1 among these shift registers will be described. The remaining shift registers ST2 to STn may be performed in the same operation as the first shift register ST1. At this time, the high state output signal Vg1 of the first shift register ST1 is supplied to the start pulse of the next second shift register ST2 and the high state output output from the second shift register ST2. The signal Vg2 is supplied to the start pulse of the next third shift register ST3. The rest of the shift registers ST4 to STn may also receive output signals of the high state of the front end as a start pulse and output predetermined high state output signals shifted in phase by one clock.

Referring to FIG. 4, the first shift register ST1 includes a control unit 41 for controlling a Q node, and an output unit 43 for outputting a first clock signal C1 according to the Q node. .

The controller 41 controls the Q node to output the first clock signal C1 through the third transistor T3 of the output unit 43. Accordingly, the output first clock signal C1 is supplied to the high output signal Vg1 through the first gate line GL1. To this end, the controller 41 is configured to output the first transistor T1 connected between the start pulse SP input line 33 and the Q node, and the output signal Vg2 of the Q node and the next shift register ST2. A second transistor T2 is connected between the input line 35 and the supply voltage VSS input line 34.

The first transistor T1 has a diode function by connecting between a source terminal and a gate terminal. That is, the current flows from the source terminal to the drain terminal of the first transistor T1, but the current is blocked from the drain terminal to the source terminal. Therefore, the first transistor T1 prevents the start pulse SP from being charged to the Q node, but prevents the voltage charged at the Q node from flowing out through the first transistor T1.

The second transistor T2 initializes the Q node (-5V). When the second transistor T2 is turned on by the output signal Vg2 of the next shift register ST2, the supply voltage VSS of the low state (-5V) is turned on. ) Is charged to the Q node. Therefore, in the next frame, the high state start pulse SP is charged to the Q node to turn on the third transistor T3.

As a result, the Q node is charged with the start pulse SP to turn on the third transistor to supply the first clock signal C1 to the first gate line GL1 and to output the output signal of the next shift register ST2. The supply voltage VSS in a low state is charged to the Q node by the second transistor T2 turned on by Vg2 to initialize and turn off the third transistor T3. This process is repeatedly performed every frame.
At this time, when the current shift register is the last shift register, since there is no next stage shift register, it is impossible to initialize the Q node by the output signal of the next stage shift register. In this case, there may be various ways to initialize the Q node of the current shift register, which is the last shift register. The most representative method of initializing the Q node of the current shift register is a method of directly initializing the Q node of the current shift register by the output signal of the current shift register. That is, while the output signal of the high state is output from the current shift register and the second transistor is turned on by the high state output signal, the low supply voltage VSS is charged to the Q node and initialized. .

The output unit 43 supplies the first clock signal C1 having a high state to the first gate line GL1 according to the voltage of the Q node and at the same time the output signal Vg1 supplied to the first gate line GL1. ) Is discharged. To this end, the output unit 43 includes a third transistor T3 connected between the first clock signal C1 input line 31 and the Q node, and the third transistor T3 and the first clock signal. (C1) A fourth transistor T4 connected between the input lines 31 is provided.

The third transistor T3 is turned on by the high state start pulse SP charged in the Q node to supply the first clock signal C1 to the first gate line GL1. Therefore, the first clock signal C1 supplied to the first gate line GL1 is the same as the first output signal Vg1.

On the other hand, the first output signal Vg1 is input as a start pulse of the next stage shift register ST2. Accordingly, in the next shift register ST2, the second output signal Vg2 identical to the second clock signal C2 is output to the second gate line GL2. The second output signal Vg2 may be supplied to the output signal input line 35 of the next shift register ST2 of the first shift register ST1. The second transistor T2 is turned on by the second output signal Vg2, so that the low supply voltage VSS is charged to the Q node to complete initialization.

The fourth transistor T4 has a diode function by connecting a source terminal and a gate terminal. That is, although the current flows from the source terminal to the drain terminal, the fourth transistor T4 blocks current from the drain terminal to the source terminal. Accordingly, the fourth transistor T4 causes the output signal Vg1 supplied to the first gate line GL1 to be discharged, but the first clock signal C1 passes through the fourth transistor T4 to the first gate line. Prevents output to (GL1).

For example, when the third transistor T3 is turned on by the high state start pulse SP charged in the Q node, the first clock signal C1 of the high state 20V becomes the first gate line. It is output to GL1 and is charged.

Subsequently, when the first clock signal C1 falls from the high state 20V to the low state (-5V), the second clock signal C2 increases from the low state to the high state. At this time, the second transistor T2 is turned on by the output signal Vg2 of the next stage shift register ST2, so that the low supply voltage VSS is charged to the Q node. Accordingly, the third transistor T3 is turned off. At this time, the first clock signal C1 in the low state is applied to the drain terminal of the fourth transistor T4. In this case, the first output signal Vg1 of the high state is charged to the source terminal of the fourth transistor T4, and the first clock signal C1 of the low state is applied to the drain terminal. Since the voltage is greater than the voltage of the drain terminal, the first output signal Vg1 is discharged through the fourth transistor T4.

As shown in FIG. 5, the first and second clock signals C1 and C2 having the ON period are sequentially supplied to the first shift register ST1 according to the exemplary embodiment of the present invention having such a configuration. do. The first and second clock signals C1 and C2 and the start pulse SP have a voltage swinging from -5V to 20V. Let -5V be the low voltage and 20V be the high voltage. The supply voltage VSS has a low voltage of -5V. In this case, one shift register is operated in three sections (S1 to S3 sections). That is, the start pulse SP section is the S1 section, the first clock signal C1 section is the S2 section, and the second clock signal C2 section is the S3 section.

The operation of the first shift register ST1 according to an embodiment of the present invention will be described with reference to the driving waveform shown in FIG. 5 as follows.

First, when the start pulse SP of the high state 20V is input in the S1 period, the start node SP of the high state is charged to the Q node via the first transistor T1. As a result, the third transistor T3 having the gate terminal connected to the Q node is gradually turned on. At this time, since the third transistor T3 is not completely turned on, the first clock signal C1 in the high state cannot pass through the third transistor T3. Therefore, the output signal of the low state (-5V) is present in the first gate line GL1.

When the first clock signal C1 in the high state is applied instead of the start pulse SP falling to the low state in the S2 period, an internal capacitance Cgs formed between the gate terminal and the source terminal of the third transistor T3 is applied. As a result, bootstrapping occurs and the Q node is charged with a voltage of about 40V. This bootstrapping phenomenon is possible because the Q node is floating. That is, the first transistor T1 is turned off because no current flows from the drain terminal to the source terminal, and the output signal Vg2 of the second transistor T2 is applied to the next shift register ST2. Since it is turned off, the start pulse SP charged in the Q node is in a floating state. In this case, when the first clock signal C1 in the high state is applied to the source terminal of the third transistor T3, Q is caused by the internal capacitance Cgs between the source terminal and the gate terminal of the third transistor T3. A bootstrapping phenomenon in which a voltage equal to the first clock signal C1 in the high state is added to the node is generated. Accordingly, the Q node is charged with 40 V, which is the sum of the voltages of the start pulse SP in the high state and the first clock signal C1 in the high state. As a result, the third transistor T3 is completely turned on so that the first clock signal C1 in the high state is rapidly charged to the first gate line GL1.

If the second clock signal C2 in the high state is applied instead of the first clock signal C1 falling to the low state in the period S3, the output signal Vg2 of the next shift register ST2 is the second transistor T2. Is applied. In detail, in the first shift register ST1, the first clock signal C1 in the high state is charged to the first gate line GL1 as the first output signal Vg1. In the next shift register, that is, the second shift register ST2, the second clock signal C2 in the high state is charged to the second gate line GL2 as the second output signal Vg2. Similarly, in the third shift register ST3, the first clock signal C1 in the high state is charged to the third gate line GL3 as the third output signal Vg3. Through this process, the first and second clock signals C1 and C2 which are sequentially in a high state are output from the respective shift registers ST1 to Sn.

Therefore, when the second clock signal C2 in the high state is applied to the second clock signal input line 32, the second clock signal C2 in the high state is input to the next shift register ST2. The second clock signal C2 is charged to the second gate line GL2 connected to the next shift register ST2 as the second output signal Vg2. In this case, an output line Vg2 of the next stage shift register connected to the gate terminal of the second transistor T2 of the first shift register ST1 is connected to the second gate line GL2. Therefore, the second output signal Vg2 is applied to the gate terminal of the second transistor T2.

Accordingly, the second transistor T2 is turned on so that the low supply voltage VSS is charged to the Q node. At this time, the third transistor T3 connected to the Q node is turned off so that the first clock signal C1 in the low state is applied to the drain terminal of the fourth transistor T4. At this time, the first gate line GL1 connected to the source terminal of the fourth transistor T4 is charged with the output signal Vg1 in the high state. Therefore, the fourth transistor T4 is turned on, and the output signal Vg1 in the high state is discharged.

On the other hand, the next shift register, that is, the second shift register ST2 has the same configuration as the above-described first shift register ST1. However, the second shift register ST2 receives the clock signal (eg, C2) and the high output signal Vg1 of the first shift register ST1 which are phase-delayed by one clock in the first shift register ST1. By using the same as the first shift register (ST1). Accordingly, the second shift register ST2 outputs the high output signal Vg2 shifted by one clock relative to the first shift register ST1.

The remaining shift registers ST3 to STn are operated in the same manner as described above. Accordingly, the output signals Vg3 to Vgn in the high state are sequentially output to the corresponding gate lines GL3 to GLn. That is, the output signals Vg1 to Vgn of the high state are sequentially outputted by the shift registers ST1 to STn connected to the gate lines GL1 to GLn for one frame, and the process is repeated for each frame. To operate.

FIG. 6 is a diagram illustrating a detailed circuit configuration of a shift register included in an embedded gate driver according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the first shift register ST1 includes a control unit 45 for controlling a Q node, and an output unit 47 for outputting a first clock signal C1 according to the Q node.

The controller 45 controls the Q node to output the first clock signal C1 through the third transistor T3 of the output unit 47. Accordingly, the output first clock signal C1 is supplied to the high output signal Vg1 through the first gate line GL1. To this end, the controller 41 may include a first transistor T1 connected between the start pulse SP input line 33 and the Q node, and an output signal input line of the Q node and the next shift register ST2. 35 and a second transistor T2 connected between a supply voltage VSS input line 34.

The first transistor T1 has a diode function by connecting a source terminal and a gate terminal. That is, in the first transistor T1, current flows from the source terminal to the drain terminal, whereas current is blocked from the drain terminal to the source terminal. Therefore, the first transistor T1 prevents the start pulse SP from being charged to the Q node, but prevents the voltage charged at the Q node from flowing out through the first transistor T1.

The second transistor T2 initializes the Q node (-5V). When the second transistor T2 is turned on by the output signal Vg2 of the next shift register ST2, the supply voltage VSS of the low state (-5V) is turned on. ) Is charged to the Q node. Therefore, in the next frame, the high state start pulse SP is charged to the Q node so that the third transistor T3 is turned on.

As a result, the third transistor T3 is turned on by the start pulse SP charged in the Q node, and the first clock signal C1 in the high state is output to the first gate line GL1 and the next shift is performed. The supply voltage VSS in the low state is charged to the Q node by the second transistor T2 turned on by the output signal Vg2 of the register ST2 and initialized to turn on the third transistor T3. Turn it off. This process is repeatedly performed every frame.
At this time, when the current shift register is the last shift register, since there is no next stage shift register, it is impossible to initialize the Q node by the output signal of the next stage shift register. In this case, there may be various ways to initialize the Q node of the current shift register, which is the last shift register. The most representative method of initializing the Q node of the current shift register is a method of directly initializing the Q node of the current shift register by the output signal of the current shift register. That is, while the output signal of the high state is output from the current shift register and the second transistor is turned on by the high state output signal, the low supply voltage VSS is charged to the Q node and initialized. .

The output unit 47 outputs the first clock signal C1 having a high state to the first gate line GL1 according to the voltage of the Q node and at the same time the output signal Vg1 output to the first gate line GL1. ) Is discharged. To this end, the output unit 47 includes a fourth transistor T4 connected between the first clock signal C1 input line 31 and the Q node, and the first clock signal C1 input line 31. And a third transistor T3 connected between the fourth transistor T4 and a fifth transistor T5 connected between the gate terminal of the third transistor T3 and the gate line GL1.

The fourth transistor T4 is turned on by the high state start pulse SP charged in the Q node, and the first clock signal C1 in the high state is applied to the gate terminal of the third transistor T3. To be.

The third transistor T3 is turned on by the first clock signal C1 in the high state applied via the fourth transistor T4 to thereby turn the first clock signal C1 in the high state into a first state. Output to the gate line GL1. Therefore, the first clock signal C1 output to the first gate line GL1 is the same as the first output signal Vg1.

On the other hand, the first output signal Vg1 is input as a start pulse of the next stage shift register ST2. Accordingly, in the next shift register ST2, the second output signal Vg2 identical to the second clock signal C2 is output to the second gate line GL2. The second output signal Vg2 may be supplied to an output signal input line of the next shift register ST2 of the first shift register ST1. The second transistor T2 is turned on by the second output signal Vg2, so that the low supply voltage VSS is charged to the Q node to complete initialization.

The fifth transistor T5 has a diode function by connecting a drain terminal and a gate terminal. That is, in the fifth transistor T5, current flows from the drain terminal to the source terminal, but on the contrary, current flows from the source terminal to the drain terminal. Accordingly, the fifth transistor T5 causes the output signal Vg1 supplied to the first gate line GL1 to be discharged through the fifth transistor T5, but is in a high state via the fourth transistor T4. Prevents the first clock signal C1 from being output to the first gate line GL1 through the fifth transistor T5. Since a detailed description thereof has been described above, further description thereof will be omitted.

As shown in FIG. 4, the first shift register ST1 according to another exemplary embodiment of the present invention having the configuration described above also has the first and second clock signals C1 and S1 having on-clock intervals sequentially. C2) is supplied. The first and second clock signals C1 and C2 and the start pulse SP have a voltage swinging from -5V to 20V. Let -5V be the low voltage and 20V be the high voltage. The supply voltage VSS has a low voltage of -5V. In this case, one shift register is operated in three sections (S1 to S3 sections). That is, the start pulse SP section is the S1 section, the first clock signal C1 section is the S2 section, and the second clock signal C2 section is the S3 section.

The operation of the first shift register ST1 according to another embodiment of the present invention will be described with reference to the driving waveform shown in FIG. 5 as follows.

First, when the start pulse SP of the high state 20V is input in the S1 period, the start node SP of the high state is charged to the Q node via the first transistor T1. Accordingly, the third transistor T3 having the gate terminal connected to the Q node is gradually turned on. At this time, since the third transistor T3 is not completely turned on, the first clock signal C1 in the high state cannot pass through the third transistor T3. Therefore, the output signal of the low state (-5V) is present in the first gate line GL1.

When the first clock signal C1 in the high state is applied instead of the start pulse SP falling to the low state in the S2 period, an internal capacitance Cgs formed between the gate terminal and the source terminal of the fourth transistor T4 is applied. As a result, bootstrapping occurs and the Q node is charged with a voltage of about 40V. Accordingly, the third transistor T3 is completely turned on and the first clock signal C1 in the high state is applied to the gate terminal of the third transistor T3 via the fourth transistor T4. The third transistor T3 is turned on by the first clock signal C1 in the high state, and the first clock signal C1 in the high state is quickly charged to the first gate line GL1.

If the second clock signal C2 in the high state is applied instead of the first clock signal C1 falling to the low state in the period S3, the output signal Vg2 of the next shift register ST2 is the second transistor T2. Is applied. In detail, in the next shift register ST2, the second clock signal C2 in the high state is charged to the second gate line GL2 as the second output signal Vg2. The second output signal Vg2 is applied to the second transistor T2 of the first shift register ST1. Accordingly, the second transistor T2 is turned on by the second output signal Vg2, so that the supply voltage VSS in the low state is charged to the Q node. At this time, the fourth transistor T4 connected to the Q node is turned off so that the first clock signal C1 in the low state is not applied to the gate terminal of the third transistor T3 via the fourth transistor T4. Do not. Instead, the gate terminal of the third transistor T3 has a low state. Therefore, while the source terminal of the fifth transistor T5 is low, the drain terminal becomes the output signal Vg1 of the high state, and thus the fifth transistor T5 is turned on so that the output signal Vg1 becomes the fifth. It is discharged via the transistor T5.

On the other hand, the next shift register, that is, the second shift register ST2 has the same configuration as the above-described first shift register ST1. However, the second shift register ST2 receives the clock signal (eg, C2) and the high output signal Vg1 of the first shift register ST1 which are phase-delayed by one clock in the first shift register ST1. By using the same as the first shift register (ST1). Accordingly, the second shift register ST2 outputs the high output signal Vg2 shifted by one clock relative to the first shift register ST1.

The remaining shift registers ST3 to STn are operated in the same manner as described above. Accordingly, the output signals Vg3 to Vgn in the high state are sequentially output to the corresponding gate lines GL3 to GLn. That is, the output signals Vg1 to Vgn of the high state are sequentially outputted by the shift registers ST1 to STn connected to the gate lines GL1 to GLn for one frame, and the process is repeated for each frame. To operate.

 As described above, according to the present invention, since only four to five transistors are provided in the first shift register ST1, three more transistors are provided in comparison with the seven transistors provided in the first shift register ST1. Less. In addition, the reduction of the transistors is equally applied to the respective shift registers, thereby significantly reducing the area of the embedded gate driver including several hundred shift registers. As a result, the cost is greatly reduced, and further, it is easy to make such transistors, thereby simplifying the process.

In addition, as shown in FIG. 2, by removing the second control unit 13 for driving the seventh transistor T7 in the related art, deterioration that may occur in the third transistor T3 of the present invention is fundamentally performed. It can improve reliability by eliminating the possibility of malfunction due to stress by blocking.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

In the gate driver built into the display panel, A plurality of shift registers for outputting an output signal sequentially shifted according to the start signal, Each of the shift registers, A first transistor connected between a start signal input line and a node to charge the start signal to the node; A third transistor connected between the node, a clock signal input line, and a gate line to output a clock signal as the output signal according to a start signal charged to the node; A second transistor connected between said node and a supply voltage input line for initializing said node by a supply voltage; And A fourth transistor connected between the clock signal input line and the gate line to discharge the output signal Built-in gate driver comprising a. The embedded gate driver of claim 1, wherein the first and fourth transistors have a function of a diode passing voltage in only one direction. In the gate driver built into the display panel, A plurality of shift registers for outputting an output signal sequentially shifted according to the start signal, Each of the shift registers, A first transistor connected between a start signal input line and a node to charge the start signal to the node; A fourth transistor connected between the node and a clock signal input line and turned on by a start signal charged in the node to pass a clock signal; A third transistor connected between the clock signal input line, a fourth transistor, and a gate line and turned on by a clock signal passing through the fourth transistor to output the clock signal as the output signal; A second transistor connected between said node and a supply voltage input line for initializing said node by a supply voltage; And A fifth transistor connected between the gate terminal of the third transistor and the gate line to discharge the output signal Built-in gate driver comprising a. 4. The embedded gate driver of claim 3, wherein the first and fifth transistors have a function of a diode passing voltage in only one direction. 4. The embedded gate driver of claim 1 or 3, wherein the start signal is supplied to the first shift register as a start pulse, and the remaining shift registers are supplied as output signals output from the previous shift register. 4. The embedded gate driver of claim 1 or 3, wherein the clock signal and the start signal are high voltages, and the supply voltages are low voltages. 4. The embedded gate driver of claim 1 or 3, wherein the second transistor is turned on by an output signal of a next stage shift register. 8. The embedded gate driver of claim 7, wherein when the shift register is a last shift register, the second transistor of the shift register is turned on by an output signal of the shift register.

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