KR100590934B1 - Shift register for lcd - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register for a liquid crystal display device which prevents deterioration of operating characteristics of the shift register in a low temperature state. According to the present invention, there is provided a shift register for a liquid crystal display device having a plurality of stages connected in cascade form, the shift register receiving a first output signal of each stage and applying it to a next stage of each stage. Way; Second transfer means for receiving an output signal of the next stage and applying the output signal to each stage and the next stage; And a common connection terminal of an output terminal of the first and second transmission means and an input terminal of the next stage, so that an input signal of the next stage received from the first and second transmission means maintains a constant level. Capacitor means; is provided.

Description

Shift register for LCD

1 is a diagram for explaining a conventional shift register for a liquid crystal display device.

2 is a diagram for explaining a conventional shift register operation for a liquid crystal display device;

3 is a view for explaining a shift register for a liquid crystal display device according to the present invention;

4 is a view for explaining the operation of the shift register for a liquid crystal display device according to the present invention.

5 is a view for explaining each stage in the shift register for a liquid crystal display device according to the present invention;

Explanation of symbols on the main parts of the drawings

51, 52: control means 53: bootstrap means

311,312,313,321,322,323: Delivery means

331,332,333: capacitor means

The present invention relates to a shift register for a liquid crystal display device, and more particularly, to a shift register for a liquid crystal display device which prevents the operation characteristics of the shift register from deteriorating in a low temperature state.

The liquid crystal display device applies an electric field to the liquid crystal interposed between the two substrates, and adjusts the intensity of the electric field to adjust the amount of light transmitted through the substrate to obtain an image signal desired by the user. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix to display an image, and a driving device for driving the liquid crystal panel. The driving device may include a gate driver for driving gate lines of the liquid crystal panel, a data driver for driving data lines, a timing controller for supplying timing control signals and pixel data to the gate driver and the data driver, and a power supply voltage. It includes a power supply.

Meanwhile, the driver IC includes a shift register for sequentially applying a driving signal to the gate line and the data line. The shift register for a conventional liquid crystal display device will be described with reference to FIG. 1.

1 is a block diagram showing a shift register for a conventional liquid crystal display device.

A conventional shift register for a liquid crystal display device includes a plurality of stages connected in a cascade form by sequentially applying output signals out1, out2, ..., outn-2, and outn-1 to each gate line of the liquid crystal display device. (ST1, ST2, ..., STn-2, STn-1) and preliminary stage STn. The clock signals clk and clkb and the power supply voltage VSS are applied to each of the stages ST1, ST2, ..., STn-2, STn-1, STn, and each of the stages ST1, ST2, ..., STn-2, The output signals out1, out2, ..., outn-2, and outn-1 of STn-1 are applied to each gate line of the liquid crystal display device. Further, the output signals out1, out2, ..., outn-2, and outn-1 are the next stages ST2, ..., STn-2 of the stages ST1, ST2, ..., STn-2, STn-1. , STn-1, STn). The next stage output signals out2, ..., outn-2, outn-1, outn are applied to the immediately preceding stages ST1, ST2, ..., STn-2, STn-1. In particular, the output signal outn of the preliminary stage STn is applied only to the previous stage STn-1 and the preliminary stage STn but not to the gate line of the liquid crystal display device. In addition, an externally applied control signal ste is applied to the first stage ST1 to operate the shift register, and the clock signals clk and clkb are signals in which phases of the same period are opposite to each other.

In such a shift register for a conventional liquid crystal display device, the clock signals clk and clkb are applied to the respective stages ST1, ST2, ..., STn-2, STn-1, STn, and the control signal ste. Is applied to the first stage ST1, each stage ST1, ST2, ..., STn-2, STn-1, STn is an output signal out1, out2, ..., outn-2, outn-1 which is a pulse signal. , outn) are printed sequentially. For example, as shown in FIG. 2, when the clock signals clk and clkb and the control signal ste are applied to a shift register for a conventional liquid crystal display device, each stage STn at a cycle of the clock signals clk and clkb. -2, STn-1, STn output pulse signals outn-2, outn-1, outn. At this time, the output signal outn-2 of the n-2th stage STn-2 becomes the input signal inn-1 of the n-1st stage STn-1, and the n-1th stage ( The output signal outn-1 of STn-1 becomes the input signal of the nth stage STn. In addition, the output signal outn-1 of the n-1th stage STn-1 becomes a reset signal of the n-2nd stage STn-2, and the output signal of the nth stage STn outn becomes a reset signal of the n-th stage Stn-1 and the n-th stage STn.

However, each of the stages ST1, ST2, ..., STn-2, STn-1, STn includes a plurality of transistors, and these transistors change in characteristics with temperature change. In particular, when the temperature is lowered and the temperature is low, the mobility of the electrons is reduced and the voltage level of the threshold voltage is increased in the characteristics of the transistors, so that each stage ST1, ST2, ..., STn-2, STn-1 The operating characteristic of (STn) may be degraded. In other words, due to the temperature drop, the electron mobility of the transistor decreases and the voltage level of the threshold voltage rises. As a result of the change in the characteristics of the transistor, the operation characteristics of the shift register may be degraded, thereby increasing the rising time of the output signals out1, out2, ..., outn-2, outn-1, and outn. As a result, there is a limit in improving the image quality of the liquid crystal display and reproducing a high speed video.

Therefore, the present invention was created to solve the problems inherent in the shift register for a liquid crystal display device according to the prior art as described above, an object of the present invention, the pulse signal is constant without changing the operating characteristics even with temperature changes The present invention provides a shift register for a liquid crystal display device capable of improving the image quality of a liquid crystal display device and reproducing a moving picture by outputting the.

In order to achieve the object as described above, according to the present invention, there is provided a shift register for a liquid crystal display device having a plurality of stages connected in cascade form: the shift register receives an output signal of each stage to receive each of the shift registers. First transfer means for applying to the next stage of the stage; Second transfer means for receiving an output signal of the next stage and applying the output signal to each stage and the next stage; And a common connection terminal of an output terminal of the first and second transmission means and an input terminal of the next stage, so that an input signal of the next stage received from the first and second transmission means maintains a constant level. Capacitor means; is provided.

In the above configuration, the plurality of stages and the capacitor means are connected to a power supply voltage terminal, and the plurality of stages receive a first clock signal externally applied and a second clock signal in which the first clock signal is inverted.

In the above configuration, the first stage of the plurality of stages receives a control signal as an input signal for enabling the shift register.

In the above arrangement, the output signal of the last stage of the plurality of stages is applied only to the second transfer means connected to the previous stage of the last stage.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view for explaining a shift register for a liquid crystal display according to the present invention.

The shift register for a liquid crystal display according to the present invention includes a plurality of stages ST1, ST2, which sequentially apply output signals out1, out2, ..., outn-2, and outn-1 to respective gate lines of the liquid crystal display. ..., STn-2, STn-1, preliminary stage STn, first and second transfer means 311, 312, 313, 321, 322, 323, and capacitor means 331, 332, 333.

Each stage ST1, ST2, ..., STn-2, STn-1, STn are connected in a cascade form. The first transfer means 311, 312, 313 is an output terminal of each stage ST1, ST2, ..., STn-2, STn-1, and a bar of each stage ST1, ST2, ..., STn-2, STn-1. The input terminals of the next stages ST2, ..., STn-2, STn-1, STn are connected. That is, the output signals out1, out2, ..., outn-2, and outn-1 of each of the stages ST1, ST2, ..., STn-2, STn-1 are immediately passed through the first transmission means 311, 312, 313. It is applied to the stages ST2, ..., STn-2, STn-1, STn.

The second transfer means (321, 322, 323) has an output terminal of the next stage (ST2, ..., STn-2, STn-1, STn) and an input terminal of the previous stage (ST1, ST2, ..., STn-2 STn-1). And then input terminals of the stages ST2, ..., STn-2, STn-1, STn. That is, the output signals out2, ..., outn-2, outn-1, and outn of the next stages ST2, ..., STn-2, STn-1, STn pass through the second transfer means 321, 322, 323, and It is again applied to the stages ST1, ST2, ..., STn-2, STn-1 and the next stages ST2, ..., STn-2, STn-1, STn. Capacitor means (331, 332, 333), the output terminal of the first and second transfer means (311, 312, 313, 321, 322, 323) and the power supply voltage (VSS) connected in common.

Here, the first and second transfer means (311, 312, 313, 321, 322, 323) are composed of NMOS transistors having a gate terminal and a drain terminal connected to their input terminals, and a source terminal connected to their output terminals. In addition, the capacitor means 331, 332, 333 may include an NMOS transistor having a drain terminal connected to an output terminal of the first and second transfer means 311, 312, 313, 321, 322, 323, and a gate terminal and a source terminal connected to a power supply voltage VSS. In other words, the output signals out1, out2, ..., outn-2, and outn-1 of each stage ST1, ST2, ..., STn-2, STn-1 are NMOSs provided in the first transfer means 311, 312, 313. It is applied to the drain terminal and the gate terminal of the transistor, the output signal (out2, ..., outn-2, outn-1, outn) of the next stage (ST2, ..., STn-2, STn-1, STn) is a second It is applied to the drain terminal and the gate terminal of the NMOS transistor provided in the transfer means (321, 322, 323).

The clock signals clk and clkb and the power supply voltage VSS are applied to the stages ST1, ST2, ..., STn-2, STn-1, STn of the shift register for a liquid crystal display according to the present invention having such a structure. The first stage ST1 receives a control signal ste applied externally to operate the shift register. Here, the clock signals clk and clkb are signals in which phases of the same period are opposite to each other. In this way, the clock signals clk and clkb and the power supply voltage VSS are applied to the stages ST1, ST2, ..., STn-2, STn-1, STn, and the control signal ste is applied to the first stage ST1. When applied to, each stage ST1, ST2, ..., STn-2, STn-1, STn sequentially outputs the output signals out1, out2, ..., outn-2, outn-1, outn which are pulse signals. Output The output signals out1, out2, ..., outn-2, outn-1 of each stage ST1, ST2, ..., STn-2, STn-1 except the output signal outn of the last stage Stn are Each gate line of the liquid crystal display device is applied.

Further, the output signals out1, out2, ..., outn-2, and outn-1 are first transmission means 311, 312, 313 connected to the output terminals of the respective stages ST1, ST2, ..., STn-2, STn-1. Is applied to the input signal of the stages ST2, ..., STn-2, STn-1, STn immediately following each of the stages ST1, ST2, ..., STn-2, STn-1. The output signals out2, ..., outn-2, outn-1, and outn of the next stage ST2, ..., STn-2, STn-1, STn are each of the next stages ST2, ..., STn-2, It is applied as a reset signal of the previous stages ST1, ST2, ..., STn-2, STn-1 via the second transfer means 321, 322, 323 connected to the output terminals of STn-1, STn. Further, the output signals out2, ..., outn-2, outn-1, outn feed back to the next stages ST2, ..., STn-2, STn-1, STn via the second transfer means 321, 322, 323. Is applied as an input signal.

At this time, a pulse signal in which the output signals out1, out2, ..., outn-2, outn-1, outn of each stage ST1, ST2, ..., STn-2, STn-1, STn In other words, when the high level is reached, the first and second transfer means 311, 312, 313, 321, 322, 323 are turned on to output the output signals out1, out2,..., Outn-2, outn-1, and outn to each stage ST1. , ST2, ..., STn-2, STn-1, STn). In addition, the capacitor means (331, 332, 333) to the input signal transmitted to each stage (ST2, ..., STn-2, STn-1, STn) by the first and second transfer means (311, 312, 313, 321, 322, 323) to have a stable constant level . In other words, when the first transmission means 311, 312, 313 applies the input signal of each stage ST2,..., STn-2, STn-1, STn, and then the second transmission means 321, 322, 323 applies the input signal. Therefore, the level shift of the input signal does not occur.

Hereinafter, an operation of the shift register for a liquid crystal display according to the present invention will be described.

4 is a waveform diagram showing the operation waveforms of the stages STn-2, STn-1, STn of the shift register for liquid crystal display according to the present invention.

When the clock signals clk and clkb, the power supply voltage VSS, and the control signal ste are applied to the shift register for the liquid crystal display according to the present invention, each stage STn-2, in the cycle of the clock signals clk and clkb, is applied. STn-1 and STn output pulse signals outn-2, outn-1 and outn. At this time, the output signal outn-2 of the n-th stage STn-2 is n-1 through the first transmission means 312 connected to the input terminal of the n-th stage STn-1. The input signal inn-1 of the second stage STn-1 is applied. The n-1th stage STn-1, which has received the output signal outn-2 of the n-2th stage STn-2, outputs the output signal outn-1 to the input terminal of the nth stage STn. Is applied to the first transmission means 313 connected to the second transmission means 322 connected to the output terminal of the n-th stage STn-1. The second transfer means 322 converts the output signal outn-1 into the reset signal of the n-2th stage STn-2 and the input signal inn-1 of the n-1th stage STn-1. Is applied. As a result, the n-th stage STn-2 is reset, and the input signal inn-1 of the n-1st stage STn-1 operates the nth stage STn to output the output signal outn. Is applied to the n-th stage STn-1 at a high level until a time point t1 at which the output signal is output.

In this manner, the shift register for a liquid crystal display device according to the present invention has each stage (ST2, ..., STn-2, STn-1, STn) in each stage (ST2, ..., STn-2, STn-1, STn). The timing at which the input signal is applied to each of the stages ST2, ..., STn-2 STn-1, STn by feeding back the output signals out2, ..., outn-2, outn-1, outn as an input signal. The interval is increased by about twice that of the shift register for a conventional liquid crystal display device. As a result, each stage (ST2, ..., STn-2, STn-1, STn) becomes low temperature due to the temperature drop, and the output signal (out1, out2) is continuously applied even though the characteristics of the transistor decrease. It is possible to prevent an increase in the rise time of ..., ..., outn-2, outn-1, outn).

Fig. 5 is a circuit diagram showing the stages ST1, ST2, ..., STn-2, STn-1, STn of the shift register for a liquid crystal display according to the present invention.

Each stage ST1, ST2, ..., STn-2, STn-1, STn includes control means 51, 51 and bootstrap means 53. FIG. The first control means 51 has an NMOS transistor having a drain terminal and a gate terminal connected to the input terminal of the first control means 51 in common, and a source terminal connected to the output terminal of the first control means 51. T1). The first control means 51 receives an input signal in from the first and second transfer means 311, 312, 313, 321, 322, 323, and bootstrap means when the input signal in is at a high level. Forward to 53. The second control means 52, the drain terminal is connected to the output terminal of the second control means 52, the gate terminal is connected to the input terminal of the second control means 52, the power supply voltage (VSS) The NMOS transistor T2 has a source terminal connected thereto. The second control means 52 receives a reset signal from the second transfer means 321, 322, 323, and bootstrap means 53 when the reset signal is at a high level. To pass on.

The bootstrap means 53 includes an NMOS transistor T3 and capacitors C1, C2, C3, C4. The NMOS transistor T3 receives the first clock signal clk as a drain terminal, and outputs out1 and out2 of each stage ST1, ST2, ..., STn-2, STn-1, STn through a source terminal. ,…, Outn-2, outn-1, outn). The first capacitor C1 has the same capacitance as the parasitic capacitance of the second capacitor C2, and cancels the second clock signal clkb to the first clock signal clk or replaces the first clock signal clk. It is a capacitor for canceling with the second clock signal clkb. The second capacitor C2 is a parasitic capacitor inside the bootstrap means 53 including the NMOS transistor T3. The third capacitor C3 pumps charge by the input signal in, and supplies the charge to the gate terminal of the NMOS transistor T3. The fourth capacitor C4 is an output load capacitor of the bootstrap means 53 including the NMOS transistor T3.

When the high level input signal in is applied to each of the stages ST1, ST2, ..., STn-2, STn-1, STn through the first transfer means 311, 312, 313, the high level input signal. in is transmitted to the bootstrap means 53 via the first control means 51. At this time, bootstrap is performed by charges charged in the third capacitor C3 by the input signal in, and the charges are transferred to the gate terminal of the NMOS transistor T3. Accordingly, the NMOS transistor T3 is turned on so that the bootstrap means 53 outputs a high level output signal out. The high level output signal out is applied to the first control means 51 as an input signal in via the second transfer means 321, 322, 323, and as a result, the operating characteristic of the bootstrap means 53 is improved. .

That is, as the temperature is lowered due to the decrease in temperature, the characteristics of the transistors T1, T2, and T3 change to decrease the electron mobility of the transistors T1, T2, and T3, and the voltage level of the threshold voltage increases. Even if the high level section of the input signal in is increased, the operating characteristics of the bootstrap means 53 can be improved. As a result, an increase in the rise time of the output signals out1, out2, ..., outn-2, outn-1, and outn of each stage ST1, ST2, ..., STn-2, STn-1, STn can be prevented. . After that, when the reset signal reset is applied to the second control means 52 through the second transfer means 321, 322, 323, a low level signal, which is a ground level, is applied to the bootstrap means 53 so that the NMOS transistor T3. Is turned off, the bootstrap means 53 is turned off and the output signal out is at a low level. As a result, the output signals out1, out2, ..., outn-2, outn-1, and outn of each stage ST1, ST2, ..., STn-2, STn-1, STn become low level.

According to the above configuration of the present invention, by increasing the enable period of each stage input signal, it is possible to prevent the deterioration of the operating characteristics of the shift register even in a low temperature state. As a result, a pulse signal is constantly output even without a change in operating characteristics even with a change in temperature. As a result, the image quality of the liquid crystal display can be improved and a moving picture can be reproduced.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (6)

A shift register for a liquid crystal display device having a plurality of stages connected in a cascade form, First transfer means for receiving an output signal of each stage and applying it to a next stage of each stage; Second transfer means for receiving an output signal of the next stage and applying the output signal to each stage and the next stage; And It is connected to the output terminal of the first and second transmission means and the common connection terminal of the input terminal of the next stage, the input signal of the next stage received from the first and second transmission means to maintain a constant level And a capacitor means. A shift register for a liquid crystal display device, comprising: a capacitor; The method of claim 1, The plurality of stages and the capacitor means are connected to a power supply voltage terminal, And the plurality of stages receive a first clock signal applied from the outside and a second clock signal in which the first clock signal is inverted. The method of claim 1, And a first stage of the plurality of stages receives a control signal for enabling the shift register as an input signal. The method of claim 1, And an output signal of the last stage of the plurality of stages is applied only to the second transfer means connected to the previous stage of the last stage. The method of claim 1, In the first and second transfer means, a drain terminal and a gate terminal are commonly connected to input terminals of the first and second transfer means, and a source terminal is common to the output terminals of the first and second transfer means. A shift register for a liquid crystal display, characterized by comprising connected NMOS transistors. The method of claim 1, The capacitor means has a shift terminal for the liquid crystal display device, characterized in that the source terminal and the gate terminal is commonly connected to the ground terminal, the output terminal of the first and second transfer means is composed of an NMOS transistor connected in common to the drain terminal. register.

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