KR20050104895A - Shift register and method for driving the same - Google Patents

Abstract

The present invention provides a shift register capable of preventing the voltage of the node Q controlling the pull-up transistor from being changed by the parasitic capacitor and preventing the gate bias stress of the control node QB of the pull-down transistor. To provide.

To this end, the shift register according to the embodiment of the present invention comprises: a pull-up transistor, each of the plurality of stages, controlled by a first node to supply a clock signal to an output line; First and second pull-down transistors respectively controlled by a second node and a third node to supply a first driving voltage to the output line; A first control unit for pre-charging and discharging the first node; And a second control unit configured to prevent the first node from floating by using first and second clock signals and the first node, and to alternately drive the second and third nodes.

Description

SHIFT REGISTER AND METHOD FOR DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and more particularly to a shift register using an amorphous-silicon thin film transistor.

A liquid crystal display device used as a display device of a television and a computer displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel. The data driver supplies a video signal to each of the data lines whenever a scan signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

In this driving circuit, the gate driver generates a scan signal for sequentially driving the gate lines using the shift register. The data driver generates a sampling signal for sequentially sampling the video signal input from the outside by a predetermined unit using the shift register.

FIG. 1 is a block diagram showing a general two-phase shift register, in which the shift register shown in FIG. 1 has first to nth stages connected in cascade.

The clock signals C1 and the second clock signal C2 are commonly supplied to the first to nth stages together with the high potential and the high potential driving voltages (not shown), and the output signal of the start pulse Vst or the previous stage is provided. Is supplied. The first stage outputs the first output signal Out1 in response to the start pulse Vst, the clock signal C1, and the second clock signal C2. The second to nth stages output the second to nth output signals Out2 to Outn in response to the output signal, the clock signal C1, and the second clock signal C2 of the previous stage. These first to nth stages have the same circuit configuration and sequentially shift the specific voltage of the start pulse Vst. The first to n th output signals Out1 to Outn are supplied as scan signals for sequentially driving the gate lines of the liquid crystal panel, or as sampling signals for sequentially sampling the video signals in the data driver.

FIG. 2 shows a detailed circuit configuration of one stage shown in FIG. 1.

The stage shown in FIG. 2 outputs the fifth NMOS transistor T5 outputting the first clock signal C1 to the output line under the control of the Q node, and the low potential driving voltage VSS under the control of the QB node. An output buffer unit 20 composed of a sixth NMOS transistor T6 outputted as a line, and a control unit 10 composed of first through fourth NMOS transistors T1 through T4 controlling the Q node and the QB node. .

The high potential and low potential voltages VDD and VSS are supplied to the stage, and a start pulse Vst, a clock signal C1, and a second clock signal C2 are supplied. Here, a high state voltage and a low state voltage having a constant pulse width are alternately supplied to the clock signal C1, and the second clock signal C2 (not shown) is the first clock signal C1. It is supplied to have the opposite polarity. The start pulse Vst is supplied from the outside or the output signal of the previous stage is supplied. Hereinafter, an operation process of the stage will be described with reference to the driving waveform shown in FIG. 3.

In the period A, the high voltage of the start pulse Vst is supplied in synchronization with the high voltage of the second clock signal C2. Accordingly, the first NMOS transistor T1 is turned on by the high voltage of the second clock signal C2 so that the high voltage of the start pulse Vst is supplied to the Q node, that is, pre-charged. The fifth NMOS transistor T5 is turned on by the high voltage pre-charged to the Q node to supply the low voltage of the clock signal C1 to the output line. In this case, the second NMOS transistor T2 is also turned on by the high voltage of the second clock signal C2 to supply the high potential driving voltage VDD to the QB node, and the high potential driving voltage (supplied to the QB node). The sixth NMOS transistor T6 is also turned on by VDD to supply the low potential driving voltage VSS. Accordingly, in the period A, the output line of the stage outputs the output signal OUT in the low state.

The fifth NMOS transistor T5 is turned on because the first NMOS transistor T1 is turned off by the low voltage of the second clock signal C2 in the period B and the Q node floats to a high state. . At this time, the Q node floated as the high voltage is supplied to the clock signal C1 is bootstrapping under the influence of the parasitic capacitor CGD formed by overlapping the gate electrode and the drain electrode of the fifth NMOS transistor T5. . As a result, the Q-node voltage further increases to ensure that the fifth NMOS transistor T5 is turned on reliably so that the high voltage of the clock signal C1 is quickly supplied to the output line. The fourth NMOS transistor T4 is turned on by the Q node floated to the high state, and the third NMOS transistor T3 is turned on by the clock signal C1 in the high state, and the low potential driving voltage is applied to the QB node. Since the VSS is supplied, the sixth NMOS transistor T6 is turned off. Accordingly, in the period B, the output line of the stage outputs the output signal OUT in the high state.

In the C period, since the first NMOS transistor T1 is turned on by the high voltage of the second clock signal C2 and the low voltage of the start pulse Vst is supplied to the Q node, the fifth NMOS transistor T5 is turned on. -Off. At this time, the second NMOS transistor T2 is turned on by the high voltage of the second clock signal C2 and the high potential driving voltage VDD is supplied to the QB node, thereby turning on the sixth NMOS transistor T6. The low potential driving voltage VSS is output to the output line. At this time, the third NMOS transistor T3 is turned off by the low voltage of the clock signal C1, and the fourth NMOS transistor T4 is turned off by the low voltage of the Q node to drive the high potential to the QB node. The voltage VDD is maintained. Accordingly, in the C period, the output line of the stage outputs the output signal OUT in the low state.

In the D period, since the first NMOS transistor T1 is turned off by the low voltage of the second clock signal C2, the Q node is floated to the low state. Since the fourth NMOS transistor T4 is turned off by the Q node in which the second NMOS transistor T2 is turned off and floated to the low state by the low voltage of the second clock signal C2, the QB node is turned off. Although the third NMOS transistor T3 is turned on due to the high voltage of the clock signal C1, P is floated while maintaining a high state slightly lower than the high potential driving voltage VDD supplied in the previous period C. Accordingly, the sixth NMOS transistor T6 maintains the turn-on state and outputs the low potential driving voltage VSS to the output line. As a result, in the D period, the output line of the stage outputs the output signal OUT in the low state.

In the remaining periods, since the C and D periods are alternately repeated, the output signal OUT of the stage is kept low.

Here, each of the first to sixth NMOS transistors T1 to T6 formed by the amorphous-silicon thin film transistor process has a structure in which the gate electrode overlaps with each of the source and drain electrodes, which is inevitably parasitic capacitors CGS and CGD. It includes. In particular, as the fifth and sixth NMOS transistors T5 and T6 constituting the output buffer unit 20 are largely formed to compensate for the low mobility of the amorphous-silicon thin film transistor, the parasitic capacitors CGS and CGD are also formed. Will increase.

Here, in the fifth NMOS transistor T5, which is a pull-up transistor, the first parasitic capacitor CGD formed at an overlapping portion of the gate electrode and the drain electrode becomes useful for bootstrapping the Q node. However, when the clock signal C1 supplied to the source electrode transitions from low to high as shown in FIG. 3, the second parasitic capacitor CGS formed at the overlapping portion of the gate electrode and the source electrode of the fifth NMOS transistor T5. There is a problem that the output voltage Vout is also shaken by varying the voltage of the Q node in the floating state every time.

Referring to FIG. 3, as the clock signal C1 transitioned to the high voltage in the D period is induced through the second parasitic capacitor CGS of the fifth NMOS transistor T5, the voltage of the Q node floated to the low state is increased. It can be seen that the voltage fluctuates slightly, so that the output voltage OUT also rises slightly from the low voltage. Since the distorted output voltage OUT is used as the input of the next stage, the distortion amount of the output voltage OUT increases as the plurality of stages pass, which may cause a circuit malfunction at some point.

In addition, the amorphous-silicon thin film transistor has a bias temperature stress characteristic that causes malfunction due to bias stress when a direct current (DV) voltage is continuously supplied to the gate terminal during high temperature operation.

However, in the conventional shift register, as shown in FIG. 3, the QB node, which is the gate node of the sixth NMOS transistor T6, is subjected to most of the period (that is, during the remaining periods except for the A and B periods in which the Q node becomes high). It can be seen that the driving voltage VDD is applied in the form of direct current. Accordingly, the conventional shift register has a problem in that the sixth NMOS transistor T6 malfunctions due to a gate bias stress when operating at a high temperature.

Accordingly, an object of the present invention is to prevent the voltage of the node Q controlling the pull-up transistor from being changed by the parasitic capacitor, and at the same time, to prevent the gate bias stress of the control node QB of the pull-down transistor. Is to provide a shift register.

In order to achieve the above object, a shift register according to an embodiment of the present invention is a shift register composed of a plurality of stages for shifting a start pulse and supplying each output signal and a next stage start pulse, each of the plurality of stages. A pull-up transistor controlled by the first node for supplying a clock signal to the output line; First and second pull-down transistors respectively controlled by a second node and a third node to supply a first driving voltage to the output line; A first control unit for pre-charging and discharging the first node; And a second control unit configured to prevent the first node from floating by using first and second clock signals and the first node, and to alternately drive the second and third nodes.

The first control unit includes: a first transistor configured to pre-charge the start pulse to the first node in response to the start pulse; And a second transistor configured to supply the first driving voltage to the first node in response to an output signal of a next stage.

The second control unit includes: third and fourth transistors controlled by the second and third nodes, respectively, to alternately supply the first driving voltage to the first node; A fifth transistor controlled by a second driving voltage to supply the first clock signal to the second node; A sixth transistor controlled by the first node to supply the first driving voltage to the second node; A seventh transistor controlled by the second driving voltage to supply the second clock signal to the third node; And an eighth transistor controlled by the first node to supply the first driving voltage to the second node.

When the fifth and sixth transistors are turned on at the same time, the sixth transistor is formed larger than the fifth transistor so that the first driving voltage is supplied to the second node.

When the seventh and eighth transistors are turned on at the same time, the sixth transistor is formed larger than the fifth transistor so that the first driving voltage is supplied to the second node.

The third and fourth transistors alternately supply the first driving voltage to the first node in a period other than a period in which the first node turns on the pull-up transistor.

The fifth to eighth transistors are configured to alternately drive the second and third nodes in periods other than a period in which the first node turns on the pull-up transistor, thereby driving the first and second pull-down transistors. Alternately turn on.

The first driving voltage is low potential, and the second driving voltage is high potential voltage.

The stage is composed of transistors of the same channel type.

The stage consists of NMOS transistors.

In the driving method of the shift register according to the present invention, the second and third transistors are disposed by the fifth to eighth transistors in a period other than a period in which the pull-up transistor is turned on by the first node. AC-driven a node to alternately turn on the first and second pull-down transistors to supply the first drive voltage to the output line, and to allow the third and third nodes to operate by the second and third nodes. Four transistors are alternately turned on to supply the first driving voltage to the first node.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 illustrates a detailed circuit of any one of a plurality of stages that are cascaded in a shift register according to an exemplary embodiment of the present invention, and FIG. 5 illustrates driving waveforms of the stage.

The stage of the shift register shown in Fig. 4 is a pull-up NMOS transistor T9 for outputting the first clock signal C1 to the output line under the control of the Q node, and low potential driving under the control of the QB1 and QB2 nodes. An output buffer unit 50 including first and second pull-down NMOS transistors T10 and T11 for outputting a voltage VSS to an output line; A first controller 30 composed of first and second NMOS transistors T1 and T2 for pre-charging and discharging the Q node; A second control section 40 composed of third to eighth NMOS transistors T3 to T8 for preventing Q node fluctuation and alternatingly driving QB1 and QB2 is provided.

The first NMOS transistor T1 of the first control unit 30 is connected to the start pulse Vst input line in the form of a diode to pre-charge the high voltage Q node of the start pulse Vst. The second NMOS transistor T2 is controlled by the next output voltage OUTi + 1 to supply the low potential voltage VSS to the Q node.

The second controller 40 controls the third and fourth NMOS transistors T3 and T4 for supplying the low potential voltage VSS to the Q node under the control of the QB1 and QB2 nodes, and the first clock signal C1 and Q. Fifth and sixth NMOS transistors T5 and T6 for controlling QB1 using a node, and seventh and eighth NMOS transistors for controlling QB2 opposite to QB1 using a second clock signal C2 and a Q node ( T7, T8).

Since the fifth and seventh NMOS transistors T5 and T7 are controlled by the high potential supply voltage VDD, the fifth and seventh NMOS transistors T5 and T7 are always turned on to supply the first and second clock signals C1 and C2 to the QB1 and QB2 nodes, respectively. Feed each one. The sixth and eighth NMOS transistors T6 and T8 are controlled according to the Q node to supply the low potential voltage VSS to the QB1 and QB2 nodes, respectively. Such fifth to eighth NMOS transistors T5 to T8 may prevent the gate electrodes of the first and second pull-down transistors T10 and T11 from undergoing a gate bias stress by causing the QB1 and QB2 nodes to be AC-driven. Will be. The third and fourth NMOS transistors T3 and T4 alternately supply the low potential voltage VSS to the Q node after the high output voltage OUTi is output at the current stage under the control of QB1 and QB2. This prevents the Q node from floating. Accordingly, the voltage variation of the Q node due to the coupling of the second parasitic capacitor CGS of the pull-up transistor T9 may be prevented. Here, the first and second clock signals C1 and C2 are supplied opposite to each other.

The operation of the shift register having such a configuration will be described with reference to the driving waveform shown in FIG.

In the period A, the low voltage of the clock signal C1, the high voltage of the second clock signal C2, and the high voltage of the start pulse Vst are supplied. The first NMOS transistor T1 is turned on by the high voltage of the start pulse Vst so that the high voltage of the start pulse Vst is supplied to the Q node, that is, pre-charged, and the next stage output signal OUTi + 1. The second NMOS transistor T2 is turned off by the low voltage of. The pull-up NMOS transistor T8 is turned on by the high voltage of the Q node, and the low voltage of the first clock signal C1 is supplied to the output line of the stage. At this time, the fifth and seventh NMOS transistors T5 and T7 are simultaneously turned on by the high potential voltage VDD and the sixth and seventh NMOS transistors T6 and T7 are turned on by the high voltage of the Q node. Here, the sixth and eighth NMOS transistors T6 and T8 are formed larger than the fifth and seventh NMOS transistors T5 and T6, so that the low potential voltage VSS is supplied to the QB1 and QB2 nodes. For example, the sixth and eighth NMOS transistors T6 and T8 and the fifth and seventh NMOS transistors T5 and T7 are formed to have a ratio of about 3: 1. The first and second pull-down NMOS transistors T10 and T11 are turned off by the low voltages of QB1 and QB2. Accordingly, in the period A, the output line of the stage outputs the output signal OUTi in the low state.

In the period B, the high voltage of the clock signal C1, the low voltage of the second clock signal C2, and the low voltage of the start pulse Vst are supplied. The first NMOS transistor T1 is turned off by the low voltage of the start pulse Vst, and the second NMOS transistor T2 is turned off by the low voltage of the next output signal OUTi + 1 so that the Q node is turned off. Floats to a high state. The Q node floated to the high state is bootstrapping along the high voltage of the clock signal C1 due to the coupling action of the first parasitic capacitor CGD formed by overlapping the gate electrode and the source electrode of the pull-up NMOS transistor T9. (Bootstrapping) As a result, the Q-node voltage further rises to reliably turn on the pull-up NMOS transistor T9 so that the high voltage of the clock signal C1 is rapidly supplied to the output line. Here, in order to increase the bootstrapping effect of the Q node, a separate capacitor may be formed in parallel with the first parasitic capacitor CGD. At this time, since the fifth to eighth NMOS transistors T5 to T8 operate in the same manner as the period A, and the nodes QB1 and QB2 are in a low state, the third and fourth NMOS transistors T3 and T4 and the first and second nodes are low. Pull-down NMOS transistors T10 and T11 are turned off. Accordingly, in the period B, the output line of the stage outputs the output signal OUTi in the high state.

In the C period, the low voltage of the clock signal C1, the high voltage of the second clock signal C2, and the low voltage of the start pulse Vst are supplied. The first NMOS transistor T1 is turned off by the low voltage of the start pulse Vst, and the second NMOS transistor T2 is turned on by the high voltage of the next output signal OUTi + 1 so that the Q node is turned on. Since the low potential voltage VSS is supplied to the pull-up NMOS transistor T9, the power is turned off. At this time, the sixth and eighth NMOS transistors T6 and T8 are turned off by the low voltage of the Q node. The low voltage of the first clock signal C1 is applied to the QB1 node, and the low voltage is applied to the QB2 node by the fifth and seventh NMOS transistors T5 and T7 which are turned on by the high potential voltage VDD. The high voltage of the two clock signals C2 is supplied. Accordingly, the third NMOS transistor T3 is turned off by the low voltage of QB1, and the fourth NMOS transistor T4 is turned on by the high voltage of QB2 to apply the low potential voltage VSS to the Q node. Supply. In addition, the first pull-down transistor T10 is turned off by the low voltage of QB1, and the second pull-down transistor T11 is turned on by the high voltage of QB2, and the low potential voltage VSS is applied to the output line. ) Is supplied. Accordingly, in the C period, the output line of the stage outputs the output signal OUT in the low state.

In the D period, the high voltage of the clock signal C1, the low voltage of the second clock signal C2, and the low voltage of the start pulse Vst are supplied. The first and second NMOS transistors T1 and T2 are turned off by the low voltage of the start pulse Vst and the next output signal OUTi + 1, so that the Q node maintains the previous low state. Transistor T7 is turned off. At this time, the sixth and eighth NMOS transistors T6 and T8 are turned off by the low voltage of the Q node. The high voltage of the first clock signal C1 is applied to the QB1 node and the second voltage is applied to the QB2 node by the fifth and seventh NMOS transistors T5 and T7 maintained in the turn-on state by the high potential voltage VDD. The low voltage of the two clock signals C2 is supplied. Accordingly, the third NMOS transistor T3 is turned on by the high voltage of QB1 to supply the low potential voltage VSS to the Q node, and the fourth NMOS transistor T4 is turned on by the low voltage of QB2. Is off. Therefore, since the Q node is not floated, the coupling operation of the second parasitic capacitor CGS of the pull-up NMOS transistor T9 may be prevented from changing along the high voltage of the clock signal C1. As a result, it is possible to prevent the distortion of the output signal OUTi due to the variation of the Q node voltage in the D period. In addition, the first pull-down transistor T10 is turned on by the high voltage of QB1 to supply the low potential voltage VSS to the output line, and the second pull-down transistor T11 by the low voltage of QB2. Is turned off. As a result, in the D period, the output line of the stage outputs the output signal OUTi in the low state.

In the remaining periods such as E and F, the C and D periods are alternately repeated, and the output line of the stage outputs the output signal OUTi in the low state. Therefore, in the remaining period, the Q node is fixed by the low potential voltage VSS by the QB1 and QB2 nodes which are AC-driven as in the C and D periods, and the first and second pull-down NMOS transistors T10 and T11. ) Gate electrode can be prevented from being subjected to gate bias stress.

As described above, the shift register according to the present invention prevents the Q node from floating while driving the QB1 and QB2 nodes by the second controller during most of the period during which the output signal is low.

Accordingly, since the DC bias is not applied to the gate electrode of the pull-down transistor, it is possible to prevent a circuit malfunction due to the gate bias stress. In addition, the coupling action of the parasitic capacitor of the pull-up transistor prevents the voltage of the Q node from being changed by the first clock signal having a high voltage, thereby preventing distortion of the output signal.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing a conventional two-phase shift register.

FIG. 2 is a detailed circuit diagram of the first stage shown in FIG. 1. FIG.

3 is a drive waveform diagram of the stage shown in FIG.

4 is a circuit diagram illustrating one stage of a shift register according to an output unit according to an exemplary embodiment of the present invention.

FIG. 5 is a drive waveform diagram of the stage shown in FIG. 4; FIG.

<Description of Main Parts of Drawing>

10, 30, 40: control unit 20, 50: output buffer unit

Claims (11)

A shift register comprising a plurality of stages for shifting start pulses and supplying each output signal and a next stage start pulse, wherein each of the plurality of stages A pull-up transistor controlled by the first node to supply a clock signal to the output line; First and second pull-down transistors respectively controlled by a second node and a third node to supply a first driving voltage to the output line; A first control unit for pre-charging and discharging the first node; And a second control unit configured to prevent the first node from floating by using first and second clock signals and the first node, and to alternately drive the second and third nodes. . The method of claim 1, The first control unit A first transistor that pre-charges the start pulse to the first node in response to the start pulse; And a second transistor configured to supply the first driving voltage to the first node in response to an output signal of a next stage; The method of claim 2, The second control unit Third and fourth transistors controlled by the second and third nodes, respectively, to alternately supply the first driving voltage to the first node; A fifth transistor controlled by a second driving voltage to supply the first clock signal to the second node; A sixth transistor controlled by the first node to supply the first driving voltage to the second node; A seventh transistor controlled by the second driving voltage to supply the second clock signal to the third node; And an eighth transistor controlled by the first node to supply the first driving voltage to the second node. The method of claim 3, wherein And the sixth transistor is larger than the fifth transistor so that the first driving voltage is supplied to the second node when the fifth and sixth transistors are turned on at the same time. The method of claim 3, wherein And the sixth transistor is larger than the fifth transistor so that the first driving voltage is supplied to the second node when the seventh and eighth transistors are turned on at the same time. The method of claim 3, wherein The third and fourth transistors And the first driving voltage is alternately supplied to the first node in a period other than a period in which the first node turns on the pull-up transistor. The method of claim 3, wherein The fifth to eighth transistors The first and second pull-down transistors are alternately turned on by alternately driving the second and third nodes in a period other than a period during which the first node turns on the pull-up transistor. And a shift register. The method according to any one of claims 1 to 6, And the first driving voltage is a low potential, and the second driving voltage is a high potential voltage. The method according to any one of claims 1 to 6, And the stage comprises a transistor of the same channel type. The method of claim 9, And said stage comprises an NMOS transistor. In the method of driving the shift register according to claim 3, In periods other than a period during which the pull-up transistor is turned on by the first node,  The second to third nodes are alternately driven by the fifth to eighth transistors so that the first and second pull-down transistors are alternately turned on to supply the first driving voltage to the output line. , And the third and fourth transistors are alternately turned on by the second and third nodes to supply the first driving voltage to the first node.