KR20050037709A - Gate driver - Google Patents

Abstract

The present invention relates to a gate driving circuit, and more particularly, each stage includes a plurality of switching elements and a plurality of inverters, and each stage includes a gate driving circuit including a shift register for outputting a square wave of a half clock period. In an embodiment, a signal having a half clock period difference output from the (m-1) and m stages of the shift register is received as an input, an output voltage is generated and applied to an Nth gate line to charge an Nth gate line. A half of the charges charged in the N-th gate line through the charge sharing switching element Q7 and the charge sharing switching element Q7 to the (N + 1) -th gate line to share charge. And a charge sharing connector for reducing power consumption and electrically connecting both gate lines.

Description

Gate driver circuit. {Gate driver}

Currently, various displays are being developed or commercialized in addition to the traditional CRT (Cathod Ray Tube). Among them, Liquid Crystal Display (OLED), Organic Light Emitting Display (OLED), Plasma Display Panel (PDP), and FED (Field) Emission Display).

In order to implement an image of the displays, an electric circuit for selecting lines in each horizontal direction is sequentially configured in the vertical direction, and an image signal voltage is input to each pixel of the selected horizontal line.

For this electrical function, as shown in FIG. 1, a plurality of gate driving integrated circuits for driving gate lines and data driving integrated circuits for processing data signals are used.

In general, the output signal voltage of the gate driving circuit generates square waves sequentially as shown in FIG. 1, and when the gate line of the square wave is applied with an offset time between signal square waves as shown in FIG. 2. There is also a patent to prevent the adverse effect of the signal delay as shown in FIG.

When switching elements such as a thin film transistor are connected to each pixel unit in the gate line, each switching element is turned on by a square wave applied to the gate line, and image signals input through the data line are switched. Is written to the pixel via.

5 is a configuration diagram of a conventional shift register, and FIG. 6 is a timing diagram of a conventional shift register.

When the start pulse SP, the clock signal CK, and the inverted clock signal CKB as shown in FIG. 6 are applied to the shift register circuit, at each of A, B, C, and D points, FIG. An output waveform as shown at (4, 5, 6, 7) is shown.

The process of obtaining the output waveform is as follows.

In FIG. 5, when the transistor Q1 connected to the input terminal to which the start pulse is input is turned on by the high-level clock signal CK, the signal output from the inverter I1 becomes low-level. Since the signal output from the inverter I1 becomes the input signal of the inverter I2, the signal output from the inverter I2 becomes high-level.

A low-level inversion clock signal CKB is applied to the transistor Q5 connected to the inverter I2 so that the transistor Q5 is turned off, so that the signal is not transmitted to the second stage shift register unit 2. Do not.

On the other hand, the output voltage of the inverter I2 is fed back to the input of the inverter I2 through the feedback inverter I3 when the inverted clock signal CKB becomes high-level. Since the transistor Q2 connected to the feedback inverter I3 is turned on and the feedback is operated, the signal voltage is maintained.

On the other hand, when the clock signal CK becomes low-level and the inverted clock signal CKB becomes high-level, the transistor Q5 at the inlet of the shift register section 2 of the second stage is turned on. The output signal of the inverter I5 becomes low-level, and passes again through the inverter I6 to output a high-level voltage signal. Therefore, at the point B of the second stage shift register section 2, a high-level voltage appears at a half clock difference from the point A of the first stage shift register section 1.

When the clock signal becomes high-level again, and the inverted clock signal becomes low-level, a low-level start pulse is input to the inverter I1 of the first stage and goes low-level through two inverters I1 and I2. Is output at point A.

On the other hand, since the waveform output at each of the points A, B, C, and D passes through the NAND gate and the inverter, each of the outputs (a, b, c) finally applied to the gate line is shown in FIGS. A sequential output voltage waveform as shown at 10) appears.

When the output voltage (a, b, c) of the gate driving circuit applied to the gate line is lowered from the high level to the low level, the pixel voltage fluctuates due to capacitive coupling between the pixel and the gate line. There is a problem in that image quality deteriorates due to a change in the pixel voltage.

In order to reduce the fluctuation of the pixel voltage, Korean Patent Laid-Open Publication No. 1996-0032327 discloses that the output voltage of a gate driving circuit applied to a gate line is changed in two stages as shown in FIG. To reduce the fluctuation of the pixel voltage.

However, the Republic of Korea Patent Publication (Application No. 1996-0032327) does not provide a method for making a waveform of the gate voltage as shown in the accompanying drawings, Figure 4 separately from the waveform of the gate voltage shown in FIG. There is a problem that must be supplied.

In addition, when the output voltage of the gate driving circuit applied to the gate line is high-level, charge is charged to the gate line. When the output voltage changes from high level to low level, the charged charges discharge.

Therefore, there is a problem that power consumption occurs due to the charge and discharge of the charge.

SUMMARY OF THE INVENTION An object of the present invention devised to solve the above problems is to provide a gate driving circuit for reducing the fluctuation of pixel voltage due to coupling and preventing deterioration of image quality by generating an output waveform varying in three steps in the gate line. have.

Another object of the present invention is to provide a gate driving circuit for reducing power consumption by charge and discharge of charge through charge sharing between gate lines.

The main component of the gate driving circuit of the present invention for achieving the above object is that each stage is composed of a plurality of switching elements and a plurality of inverters, each stage comprises a shift register for outputting a square wave of a half clock period In the gate driving circuit, a signal having a half clock period difference output from the (m-1) and m stages of the shift register is received as an input, an output voltage is generated, and applied to an Nth gate line, and applied to the Nth gate line. A driving circuit waveform generation unit for charging electric charges; Half of the charges charged in the gate line at the Nth stage are transferred to the gate line at the (N + 1) th stage through the charge sharing switching element Q7 to share the charge, thereby reducing power consumption and electrically connecting both gate lines. Characterized in that it further comprises; charge sharing connection for connecting to.

In addition, the driving circuit waveform generation unit of the present invention, the selection signal control unit for controlling the selection signal voltage source, the switching element Q3 connected to the selection signal control unit, and the selection signal connected to any one electrode except the gate electrode of the switching element. A voltage source, an off signal controller for controlling the off signal voltage source, a switching element Q4 connected to the off signal controller, and an off signal voltage source connected to any one of the electrodes except the gate electrode of the switching element. do.

In addition, the charge sharing connecting unit of the present invention is characterized in that the charge sharing switching element (Q7) and the charge sharing switching element control unit for controlling the charge sharing switching element (Q7).

In addition, the selection signal controller of the present invention receives a signal of the difference between the half clock periods output from the (m-1) stage and the m stage of the shift register through two input terminals of the NAND gate (NAND 1). It is characterized in that for controlling the selection signal voltage source by applying a signal output from the inverter I4 connected in series with the NAND 1) and the NAND gate NAND 1 to the switching element Q3.

In addition, the off-signal control unit of the present invention receives the signal of the difference between the half clock period output from the (m-1) stage and the m stage of the shift register through the two input terminals of the NOR gate (NOR 1), the NOR gate ( The off signal voltage source is controlled by applying a signal output from NOR 1) to the switching element Q4.

In addition, the switching device control unit for charge sharing according to the present invention receives a signal of the difference between the half clock periods output from the m stage and the (m + 1) stage of the shift register through the NAND gate NAND 2, and then the NAND gate ( And a charge sharing transistor using a voltage signal output from the NAND 2) and the inverter I8 connected in series with the NAND gate NAND 2.

Hereinafter, the configuration of the present invention will be described in detail with reference to the accompanying drawings.

7 is a structural diagram of a gate driving circuit according to the present invention.

Preferably, the switching element used in the present invention is a transistor, and the transistor is composed of three parts: a gate electrode, a source electrode, and a drain electrode, and can be realized by any of n-type and p-type transistors. In the present specification, one of the source electrode and the drain electrode is referred to as a first electrode, and the other electrode is described as a second electrode in order to avoid technical confusion.

The gate driving circuit according to the present invention has a configuration of an additional circuit in the configuration of the conventional shift register.

 In the configuration of the conventional shift register, the driving circuit waveform generation unit 30 and the charge sharing connection unit 40 are further configured.

The driving circuit waveform generator 40 includes a selection signal controller 60, an off signal controller 70, a selection signal voltage source VDD, an off signal voltage source VSS, and a plurality of switching elements Q3 and Q4. . The selection signal controller 60 includes a NAND gate NAND 1 and an inverter I4, and the off signal controller 70 includes a NOR gate NOR 1.

The charge sharing connector 50 includes a charge sharing switching element controller 80 and a charge sharing switching element Q7. The charge sharing switching device controller 80 includes a NAND gate NAND 2 and an inverter I8.

The two input terminals of the NAND gate NAND 1 and the NOR gate NOR 1 of the driving circuit waveform generator 40 are located at the node A and the m-th stage shifted in the (m-1) th stage shift register 10, respectively. The waveform output from the B node located in the register 20 is received. The NAND gate NAND 1 and the NOR gate NOR 1 are connected in parallel, and an inverter I4 is connected in series to the NAND gate NAND 1.

The inverter I4 is connected to the gate electrode of the transistor Q3, the first electrode of the transistor Q3 is connected to the selection signal voltage source VDD, and the second electrode is connected to the Nth gate line.

The NOR gate NOR 1 is connected to the gate electrode of the transistor Q4, the first electrode of the transistor Q4 is connected to the off signal voltage source VSS, and the second electrode is connected to the Nth gate line. .

That is, the first electrode of the transistor Q3 and the first electrode of the transistor Q4 are commonly connected to the Nth gate line.

The signal input to the input terminal of the NAND gate NAND 1 is applied to the transistor Q3 via the NAND gate NAND 1 and the inverter I4. The signal applied to the transistor Q3 is as shown in FIG. 8 (8) and serves to control the selection signal voltage source VDD.

The signal input to the input terminal of the NOR gate NOR 1 is applied to the gate electrode of the transistor Q4 through the NOR gate NOR 1. The signal passing through the NOR gate NOR 1 is illustrated in FIG. 8 (9) of the accompanying drawings, and serves to control the off signal voltage source VSS.

The driving circuit waveform generator 40 generates an output waveform that is changed in three steps, and moves charge from the Nth gate line to the (N + 1) th gate line through the charge sharing connector 50.

Two input terminals of the NAND gate NAND 2 in the charge sharing connector 50 receive signals output from the nodes B and C. The NAND gate NAND 2 is connected in series with the inverter I8.

The inverter I8 is connected to the gate electrode of the sharing transistor Q7, the first electrode of the sharing transistor Q7 is connected to the Nth gate line, and the second electrode is the (N + 1) th gate. Connected to the line.

The signal passing through the inverter I8 is shown in FIG. 8 (10) of the accompanying drawings, and when the signal is applied to the transistor Q7 in a high-level state, the transistor Q7 is in an on-state. do.

The conductive transistor Q7 serves as a connection for transferring charge charged in the N-th gate line to the (N + 1) -th gate line.

The structure of the gate line after the (N + 1) th stage is also the same as that of the Nth stage gate line.

Referring to the operation of the present invention configured as described above in detail.

When the transistor Q1 to which the voltage signal of the node A of FIG. 7 is input is turned on by the high-level clock signal CK, the voltage signal that was high-level at the node A turns off the inverter I1. To the low level, and again to the high level at node B via inverter I2.

At this time, a low-level inverted clock signal CKB is applied to the transistor Q5 connected to the node B so that the signal is not transmitted to the next stage.

The output voltage signal of the inverter I2 is fed back to the input of the inverter I2 via the feedback inverter I3. As the transistor Q2 connected to the feedback inverter I3 is turned on, the feedback is operated to maintain the signal voltage.

On the other hand, when the inverted clock signal CKB becomes high-level, the transistor Q5 connected to the node B is turned on and the high-level signal of the inverter I2 located at the m th stage 20 is ( It passes through the inverter I5 of the m + 1) th stage 30 and becomes low-level, and passes through the inverter I6 again, and a high-level signal appears at the node C.

Therefore, as shown in FIG. 7, a signal of a half clock difference appears at the B node of the m th stage 20 and at the C node of the (m + 1) th stage 30.

When the clock signal CK becomes high-level again and the inverted clock signal CKB becomes low-level, a low-level voltage signal is input to the input of the m-th stage 20, and two inverters I1, Through node I2), the low-level output voltage appears at node B.

8 shows a voltage signal appearing at each node through the above process.

As shown in FIG. 8, the voltage signals output from the A and B nodes are respectively input to two input terminals of the NAND gate NAND 1 and the NOR gate NOR 1.

First, signals of node A and node B are input to two input terminals of the NAND gate, and when the signal passes through the NAND gate NAND 1, a signal width is reduced in half and a signal whose phase is reversed is output. .

The signal is reversed again through the inverter I4, and the output signal (signal at node a) is halved as shown in (8) of the accompanying drawings.

The signal appearing at the node a is applied to the gate electrode of the transistor Q3, and the signal becomes a waveform for output of the selection voltage signal source VDD. That is, the waveform shown at the node a in FIG. 8 is applied to the gate electrode of the transistor Q3 to control the selection voltage signal VDD.

Signals of node A and node B are input to an input terminal of the NOR gate NOR 1. The input signal is applied to the gate electrode of the transistor Q4 through the NOR gate NOR 1.

The waveform of the voltage signal applied to the gate electrode of the transistor Q4 is shown in FIG. 8 (9) of the accompanying drawings. The signal is a waveform appearing at node b and becomes a waveform for output of the off-voltage signal source VSS. That is, the waveform appearing at the node b is applied to the transistor Q4 to control the off voltage signal VSS.

Output voltage signals of the B and C nodes are input to the input terminals of the NAND gate 2. The input signal passes through the NAND gate NAND 2 and the signal width is reduced by half, and the phase is reversed. The signal passing through the NAND gate becomes the input signal of the inverter I8, and the phase is reversed again through the inverter I8.

The signal output from the inverter I8 (a signal appearing at the node c) has a signal width that is reduced by half as compared to the signal input to the NAND gate NAND 2 as shown in FIG. The signal output from the inverter I8 (a signal appearing at the node c) is applied to the gate electrode of the sharing transistor Q7 to conduct the sharing transistor Q7.

On the other hand, when the signal shown in (8) of FIG. 8 is applied to the gate electrode of the transistor Q3 in a high-level state, the selection signal voltage VDD is applied to the N-th gate line.

On the other hand, when the signal shown in (10) of FIG. 8 is applied to the gate electrode of the transistor Q7 in a high-level state, the transistor Q7 is turned on, and the selection signal voltage VDD The charge charged in the N-th gate line is transferred to the (N + 1) -th gate line. The charge transfer occurs until the N-th gate line and the (N + 1) -th gate line become the same voltage.

While the selection signal voltage is input to the gate line of the Nth stage and charge sharing is performed with the gate line of the (N + 1) th stage, the low-level voltage of the node b as shown in (9) of FIG. 8 is shown. The off signal voltage source VSS is electrically isolated from the gate line by the signal being applied to the transistor Q4.

In addition, during the charge sharing process, the transistor Q3 is turned off because the output signal of the node a as shown in (8) of FIG. 8 is low-level. Thus, the selection signal voltage source VDD is electrically isolated from the gate line. This is to prevent the signal source from being applied to the gate line during the charge sharing.

8 (11) is input to the gate line as a voltage signal appearing at the node N. As shown in FIG. Among these, the intermediate voltage is due to charge distribution between gate lines through the charge sharing process. Since the voltage finally applied to the gate line is changed in three steps as shown in (11) of FIG. 8, the variation of the pixel voltage due to the coupling can be reduced.

By the above process, even when the selection signal voltage is applied to the gate line of the (N + 1) th stage, half of the charges charged in the gate line of the Nth stage are recycled, thereby reducing the (N + 1) th stage of the (N + 1) th stage. The charge can be preliminarily charged to the gate line, thereby reducing power consumption.

According to the present invention configured as described above, since the charge can be recycled through the charge sharing process, it is possible to achieve the effect of reducing the power consumption.

In addition, according to the present invention, by changing the waveform finally applied to the gate line in three steps, it is possible to achieve the effect of reducing the adverse effect caused by the coupling between pixels and to improve the image quality of the display.

1 is a view showing an output waveform of a general gate driving circuit.

2 is a view showing an output waveform for preventing adverse effects due to time delay of a gate driving voltage.

3 is a view showing an output waveform of the gate driving circuit changed by the time delay of the gate line.

4 is a diagram showing an output waveform of a gate driving circuit for reducing fluctuation in pixel voltage.

5 is a configuration diagram of a conventional shift register.

6 is a timing diagram of a conventional shift register.

7 is a configuration diagram of a gate driving circuit according to the present invention.

8 is a timing diagram of a gate driving circuit according to the present invention;

<Explanation of symbols for main parts of drawing>

1: first stage shift register 2: second stage shift register

10: (m-1) th stage shift register 20: mth stage shift register

30: (m + 1) th stage shift register 40: drive circuit waveform generator

50: charge sharing connection 60: selection signal control unit

70: off-signal control unit 80: switching element control unit for charge sharing

Q1 to Q14: Transistors I1 to I16: Inverter

NAND 1 ~ NAND 4: NAND gate

NOR 1 ~ NOR 2: NOR gate

VDD: selection signal voltage source VSS: off signal voltage source

Claims (9)

In the gate driving circuit each stage is composed of a plurality of switching elements and a plurality of inverters, each shift stage comprises a shift register for outputting a square wave of half clock period A drive circuit for charging the N-th gate line by charging the N-th gate line by generating an output voltage and receiving the signal having a half clock period difference output from the (m-1) and m stages of the shift register as an input. A waveform generator;   Half of the charges charged in the gate line at the Nth stage are transferred to the gate line at the (N + 1) th stage through the charge sharing switching element Q7 to share the charge, thereby reducing power consumption and electrically connecting both gate lines. A charge sharing connection part for connecting; Gate drive circuit further comprises a. The waveform generator of claim 1, wherein the driving circuit waveform generator comprises: A selection signal control unit for controlling a selection signal voltage source, a switching element Q3 connected to the selection signal control unit, a selection signal voltage source connected to any electrode except the gate electrode of the switching element, and an off signal voltage source for controlling the selection signal voltage source An off-signal control source, an off-signal voltage source connected to any one of the electrodes except the switching element Q4 and the gate electrode of the switching element, Gate drive circuit comprising a. The method of claim 2, wherein the selection signal control unit A signal having a half clock period difference output from the (m-1) terminal and the m terminal of the shift register is input through two input terminals of the NAND gate (NAND 1), and the NAND gate (NAND 1) and the NAND gate (NAND). A gate drive circuit for controlling the selection signal voltage source by applying a signal output from the inverter I4 connected in series with 1) to the switching element Q3. The method of claim 2, wherein the off-signal control unit, A signal having a half clock period difference output from the (m-1) and m stages of the shift register is input through two input terminals of the NOR gate NOR 1, and the signal output from the NOR gate NOR 1 is switched. A gate driving circuit for controlling the off-signal voltage source by applying it to the element Q4. The method of claim 1, wherein the charge sharing connection portion A gate driving circuit comprising a charge sharing switching element (Q7) and a charge sharing switching element control unit for controlling the charge sharing switching element (Q7). The method of claim 5, wherein the charge sharing switching device control unit, After receiving the signal of the half clock period difference output from the m stage and the (m + 1) of the shift register through the NAND gate (NAND 2), and the NAND gate (NAND 2) and the NAND gate (NAND 2) A gate drive circuit for controlling the charge sharing transistor using the voltage signal output from the inverter (I8) connected in series. The switching element according to any one of claims 1 to 6, A gate drive circuit comprising an N-type transistor. The switching element according to any one of claims 1 to 6, A gate driving circuit comprising a p-type transistor. The method of claim 1, wherein the output voltage of the drive circuit waveform generation unit, Gate driving circuit, characterized in that to reduce the fluctuation of the pixel voltage due to coupling by changing in three steps