TW202215398A - Shift register and display device - Google Patents

Abstract

A shift register includes a plurality of core circuits (RGs) connected to a plurality of scan lines, respectively, and connected in cascade. Each core circuit (RG) includes an input unit (20), a first inverter circuit (21o), a second inverter circuit (21e), an output unit (22), a first pull-down transistor, and a second pull-down transistor, wherein the input unit (20) transfers an input signal to a first node, the first inverter circuit (21o) is activated by a first frame signal, and holds an inverted signal of a first node at a second node, the second inverter circuit (21e) is activated by a second frame signal and holds an inverted signal of the first node at a third node, the output unit (22) includes an output transistor and a capacitor, the first pull-down transistor is connected to the first inverter circuit (21o), and the second pull-down transistor is connected to the second inverter circuit (21e).

Description

Shift register and display device

The present invention relates to a shift register and a display device.

An active matrix type liquid crystal display device using a thin film transistor (TFT; Thin Film Transistor) as an active element, or an organic EL (electroluminescence; electroluminescence) display device is equipped with TFTs arranged in a matrix. substrate (called TFT substrate). The TFT substrate has a plurality of signal lines respectively extending in the row (column) direction and to which image signals are input, and a plurality of scanning lines respectively extending in the column (row) direction.

In recent years, gate drivers for driving scanning lines have been formed on TFT substrates, resulting in cost reduction of driver ICs (Integrated Circuits) and narrowing of display panels. . In addition, by forming the gate driver on the TFT substrate, the limitation of the scan line wiring is eliminated, so it is a technology that can also be used for "special-shaped display panels" that are highly required for automotive applications. The above technology is called GIP (Gate driver in panel; gate driver in panel) or GOA (Gate driver on array; gate driver array).

In the scanning line driving circuit formed by TFT, a shift register for sequentially outputting a pulse signal to a plurality of scanning lines is used. The shift register includes a TFT (referred to as an output TFT) that outputs a pulse wave signal to a scan line, a TFT (referred to as a pull-down TFT) that pulls down the scan line when the scan line is not selected, and Inverter circuit. The purpose of having an inverter circuit is to inhibit the output TFT from passing through the gate. The so-called self-turn-on phenomenon in which the parasitic capacitance between the drains causes malfunction of itself.

This inverter circuit must operate so as to keep the scan line off when the scan line is not selected. Therefore, a forward bias (bias) is continuously applied to the gate of the pull-down TFT, and the characteristics of the TFT change with time (for example, a threshold voltage shift (shift)). At this time, malfunctions due to malfunction of the inverter circuit and malfunction of the pull-down of the scanning line occur. [Prior Art Literature] [Patent Literature]

Patent Document 1: Japanese Patent No. 5190281 Patent Document 2: Japanese Patent No. 5399555

[The problem to be solved by the invention]

The present invention provides a shift register and a display device capable of suppressing malfunction. [means to solve the problem]

The shift register according to the first aspect of the present invention includes a plurality of core circuits connected to a plurality of scan lines respectively and connected in series. Each of the above-mentioned plurality of core circuits includes: an input unit that transfers an input signal corresponding to an output signal of the core circuit of the previous stage to a first node (node); a first inverter circuit that uses the first The frame signal is set to be enabled, and the inverted signal of the first node is maintained at the second node; the second inverter circuit is set to the second frame signal complementary to the first frame signal. enable, hold the inverted signal of the first node at the third node; the output part includes an output transistor and a capacitor (capacitor), the output transistor system has a gate connected to the first node, receives the first A first terminal of a clock signal or a second clock signal, and a second terminal connected to the scan line, the capacitor has a first electrode connected to the first node, and a first electrode connected to the scan line. two electrodes; a first pull-down transistor having a gate connected to the second node, a first terminal connected to the scan line, and a second terminal to which a reference voltage is supplied; and a second pull-down transistor having A gate connected to the third node, a first terminal connected to the scanning line, and a second terminal to which the reference voltage is supplied. The odd-numbered core circuits receive the first clock signal; the even-numbered core circuits receive the second clock signal complementary to the first clock signal.

The shift register of the second aspect of the present invention is the shift register of the first aspect, further comprising a first transistor, and the first transistor system is connected between the second node and the third between the nodes, and has a gate connected to the first node.

A shift register of a third aspect of the present invention is the shift register of the first or second aspect, wherein the first inverter circuit includes second and third transistors; the second The transistor system has a gate connected to the second node, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied; the third transistor system has a gate connected to the first node a gate, a first terminal connected to the second node, and a second terminal to which the reference voltage is supplied; the second inverter circuit includes fourth and fifth transistors; the fourth transistor has a connection A gate to the third node, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied; the fifth transistor system has a gate connected to the first node, connected to the The first terminal of the third node, and the second terminal to which the reference voltage is supplied.

The shift register of the fourth aspect of the present invention is in the shift register of the third aspect, when the channel width of the second transistor is set to be W1, and the width of the channel of the third transistor is set to be W1. When the channel width is W2, there is a relationship of “W2≦W1≦2×W2”.

The shift register of the fifth aspect of the present invention is in the shift register of the first or second aspect, and the first inverter circuit includes the step of transferring the first frame signal to the first frame signal. The sixth transistor of the second node; the second inverter circuit includes a seventh transistor that transfers the second frame signal to the third node.

In the shift register of the sixth aspect of the present invention, in the shift register of the first or second aspect, the input portion includes a reset transistor, and the reset transistor system has A gate to which a reset signal corresponding to an output signal of the core circuit of the next stage is input, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied.

In the shift register of the seventh aspect of the present invention, in the shift register of the sixth aspect, the gate of the reset transistor included in the core circuit of the last stage is input at the last The output signal of the core circuit of the segment is set to be enabled and then set to be the enabled clear signal.

In the shift register of the eighth aspect of the present invention, in the shift register of the first or second aspect, the input part of the core circuit of the first stage is inputted with a start for starting the scanning operation. (start) signal.

A display device of a ninth aspect of the present invention includes the shift register of the first aspect.

The display device of the tenth aspect of the present invention is the display device of the ninth aspect, further including a pixel array including a plurality of pixels. The plurality of scan lines are connected to the pixel array. [Effect of invention]

According to the present invention, it is possible to provide a shift register and a display device capable of suppressing malfunction.

[Form for carrying out the invention]

Hereinafter, the embodiment will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of each drawing may not necessarily be the same as the actual size. Moreover, even if the same part is shown between drawings, the relationship and ratio of a dimension may differ from each other. Specifically, the several embodiments shown below are examples of apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not limited by the shape, structure, arrangement, etc. of the constituent parts. . In the following description, elements having the same functions and configurations are given the same reference numerals, and overlapping descriptions are omitted.

[1] Configuration of the liquid crystal display device 1

In the present embodiment, as a display device, a liquid crystal display device will be described as an example.

FIG. 1 is a layout diagram of a liquid crystal display device 1 according to an embodiment of the present invention. The liquid crystal display device 1 of the present embodiment is constituted by, for example, a GIP (gate driver in panel) or GOA (gate driver on array) type LCD (liquid crystal display; liquid crystal display). The liquid crystal display device 1 includes a pixel array 10 , scanning line drivers (denoted as GIPs) 11 - 1 and 11 - 2 , and an integrated circuit (IC; integrated circuit) 2 .

The pixel array 10 is provided with a plurality of scanning lines GL each extending in the X direction, and a plurality of signal lines SL each extending in the Y direction intersecting the X direction.

Scan line drivers 11 - 1 and 11 - 2 are arranged on both sides of the pixel array 10 in the X direction, respectively. The scan line driver 11-1 is connected to the odd-numbered scan line GL. The scan line driver 11-2 is connected to the even-numbered scan line GL.

The integrated circuit 2 is connected to a plurality of signal lines SL. Further, the integrated circuit 2 is connected to the scanning line drivers 11-1 and 11-2. The integrated circuit 2 is constituted by an IC chip.

FIG. 2 is a block diagram of the liquid crystal display device 1 according to the embodiment. The liquid crystal display device 1 includes a pixel array 10 , a scanning line driving circuit 11 , a signal line driving circuit 12 , a common electrode driving circuit 13 , a voltage generating circuit 14 , and a control circuit 15 . The scanning line drivers 11-1 and 11-2 shown in FIG. 1 correspond to the scanning line driving circuit 11 shown in FIG. 2 . The integrated circuit 2 shown in FIG. 1 includes the signal line driver circuit 12 , the common electrode driver circuit 13 , the voltage generation circuit 14 , and the control circuit 15 shown in FIG. 2 .

The pixel array 10 includes a plurality of pixels PX arranged in a matrix. The pixel array 10 is provided with a plurality of scan lines GL1 to GLm extending in the X direction, respectively, and a plurality of signal lines SL1 to SLn extending in the Y direction, respectively. "m" and "n" are each an integer of 2 or more. The pixel PX is arranged in the intersection area of the scanning line GL and the signal line SL.

The scan line driving circuit 11 is electrically connected to a plurality of scan lines GL. The scan line driver circuit 11 transmits, to the pixel array 10 , scan signals for turning on/off switching elements included in the pixels PX according to control signals sent from the control circuit 15 .

The signal line driving circuit 12 is electrically connected to the plurality of signal lines SL. The signal line driving circuit 12 receives control signals and display data from the control circuit 15 . The signal line driving circuit 12 sends the tone signal (driving voltage) corresponding to the display data to the pixel array 10 according to the control signal.

The common electrode driving circuit 13 generates a common voltage Vcom, and supplies the common voltage Vcom to the common electrodes in the pixel array 10 . The common electrode is an electrode provided so as to face the plurality of pixel electrodes provided for each of the plurality of pixels PX with the liquid crystal layer interposed therebetween.

The voltage generation circuit 14 generates various voltages necessary for the operation of the liquid crystal display device 1, and supplies these voltages to corresponding circuits.

The control circuit 15 systematically controls the operation of the liquid crystal display device 1 . The control circuit 15 receives the image data DT and the control signal CNT from the outside. The control circuit 15 generates various control signals based on the image data DT, and sends these control signals to corresponding circuits.

[2] Circuit configuration of pixel PX

Next, the circuit configuration of the pixels PX included in the pixel array 10 will be described. FIG. 3 is a circuit diagram of the pixel array 10 shown in FIG. 2 .

The pixel PX includes a switching element (active element) 16 , a liquid crystal capacitor (liquid crystal element) Clc, and a storage capacitor Cs. For the switching element 16, for example, a TFT (Thin Film Transistor) or an n-channel TFT is used.

The source of the TFT 16 is connected to the signal line SL, the gate is connected to the scan line GL, and the drain is connected to the liquid crystal capacitor Clc. The liquid crystal capacitor Clc, which is a liquid crystal element, is constituted by a pixel electrode, a common electrode, and a liquid crystal layer sandwiched by the two electrodes.

The storage capacitor Cs is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cs has a function of suppressing the potential fluctuation occurring in the pixel electrode and holding the driving voltage applied to the pixel electrode until the driving voltage corresponding to the next signal is applied. The storage capacitor Cs is composed of a pixel electrode, a storage electrode (also called a storage capacitor line), and an insulating film sandwiched by the two electrodes. The common voltage Vcom is applied to the common electrode and the storage electrode by the common electrode driving circuit 13 .

[3] Configuration of scanning line driver circuit 11

Next, the configuration of the scanning line driver circuit 11 will be described. The scanning line driver circuit 11 includes a shift register 11A. FIG. 4 is a block diagram of the shift register 11A included in the scan line driving circuit 11 .

The shift register 11A includes a plurality of core circuits RG1 to RGm. The core circuits RG1 to RGm are respectively provided corresponding to the scan lines GL1 to GLm. In this specification, the common description of the plurality of core circuits RG1 to RGm is denoted as "core circuit RG".

A plurality of core circuits RG1 to RGm are connected in series. Each core circuit RG functions as a register for temporarily storing input data. The shift register 11A operates in synchronization with the clock signal, and operates to sequentially shift the input data (pulse signal).

Each core circuit RG is configured to output a pulse wave signal according to the conditions of a plurality of signals input to itself. Each core circuit RG includes an input terminal V_IN, an output terminal OUT, a frame terminal Fr_o, a frame terminal Fr_e, a clock terminal CLK, a clear terminal CR, and a reset terminal RST_IN.

The plurality of core circuits RG1 to RGm are configured such that the output terminal OUT of an arbitrary core circuit RGi is connected to the input terminal V_IN of the core circuit RG(i+1) of the next stage, and is connected in series. i is any number from 1 to m. In addition, a start signal ST is input to the input terminal V_IN of the core circuit RG1 in the first stage.

A frame signal Frame_o is input to the frame terminals Fr_o of the core circuits RG1 to RGm. A frame signal Frame_e is input to the frame terminals Fr_e of the core circuits RG1 to RGm. A clear signal CLR is input to clear terminals CR of the core circuits RG1 to RGm.

The clock signal ClkA is input to the clock terminals CLK of the odd-numbered core circuits RG1 , RG3 , . . . The clock signal ClkB is input to the clock terminals CLK of the even-numbered core circuits RG2, RG4, . . . The clock signal ClkA and the clock signal ClkB have a complementary phase relationship.

The output terminal OUT of any core circuit RGi is connected to the reset terminal RST_IN of the core circuit RG(i-1) of the previous stage. A clear signal CLR is input to the reset terminal RST_IN of the core circuit RGm in the last stage.

The output terminals OUT of the plurality of core circuits RG1 to RGm are respectively connected to the scan lines GL1 to GLm. Regarding the capacitor connected to each scan line GL of FIG. 4 , it is a simplified representation of the capacitance of the pixel connected to the scan line.

The control circuit 15 generates the aforementioned frame signal Frame_o, frame signal Frame_e, clock signal ClkA, clock signal ClkB, and clear signal CLR, and supplies these signals to the shift register 11A.

(Concrete configuration of core circuit RG)

Next, the specific configuration of the core circuit RG will be described. FIG. 5 is a circuit diagram of the core circuit RG shown in FIG. 4 . The core circuit RG includes an input unit 20 , a register unit 21 , an output unit 22 , a pull-down unit 23 , and a clear unit 24 . The core circuit RG is configured using an N-type field effect transistor (FET; Field Effect Transistor). Hereinafter, the FET is simply referred to as a transistor. In the present embodiment, as an example, the transistor system constituting the core circuit RG is constituted by an N-channel TFT. In this specification, one of the source and drain of the transistor is also referred to as a first terminal, and the other is referred to as a second terminal.

The input unit 20 is a circuit for receiving the input signal VIN. The input unit 20 includes two transistors M2 and M5. The input signal VIN is input to the gate of the transistor M2 through the input terminal V_IN. The input signal VIN corresponds to the output signal of the core circuit RG of the previous stage. The drain of transistor M2 is connected to its gate. That is, the transistor M2 is connected as a diode. The source of transistor M2 is connected to node An. The transistor M2 transfers the input signal VIN to the node An when the input signal VIN is at a high level, and is turned off when the input signal VIN is at a low level.

The reset signal RST is input to the gate of the transistor (also called the reset transistor) M5 through the reset terminal RST_IN. The reset signal RST corresponds to the output signal of the core circuit RG of the next stage. The drain of transistor M5 is connected to node An. The source of the transistor M5 is connected to the power supply terminal to which the voltage Vgl is supplied. The voltage Vgl is a reference voltage for setting the signal to a low level, and is a voltage lower than the high level voltage of the signal. The voltage Vgl is, for example, a negative voltage lower than the ground voltage GND, and is set in the range of -10V to -20V.

The register part 21 is a circuit for holding the voltage applied between the capacitors Cb in the selected state and the non-selected state. The register unit 21 includes two inverter circuits 21o and 21e, and a transistor M1b.

The inverter circuit 21o includes three transistors M1o, M6o, and M7o. A frame signal Frame_o is input to the gate of the transistor M1o through the frame terminal Fr_o. The drain of transistor M1o is connected to its gate. The source of transistor M1o is connected to node Bno. The transistor M1o transfers the frame signal Frame_o to the node Bno when the frame signal Frame_o is at a high level, and is turned off when the frame signal Frame_o is at a low level. That is, the inverter circuit 21o is set to be enabled when the frame signal Frame_o is at a high level.

The gate of transistor M6o is connected to node Bno. The drain of transistor M6o is connected to node An. The source of the transistor M6o is connected to the power supply terminal to which the voltage Vgl is supplied. The transistor M6o has a function of pulling down the potential of the node An.

The gate of transistor M7o is connected to node An. The drain of transistor M7o is connected to node Bno. The source of the transistor M7o is connected to the power supply terminal to which the voltage Vgl is supplied. The transistor M7o has a function of pulling down the potential of the node Bno.

The inverter circuit 21e includes three transistors M1e, M6e, and M7e. A frame signal Frame_e is input to the gate of the transistor M1e through the frame terminal Fr_e. The drain of transistor M1e is connected to its gate. The source of transistor M1e is connected to node Bne. The transistor M1e transfers the frame signal Frame_e to the node Bne when the frame signal Frame_e is at a high level, and is turned off when the frame signal Frame_e is at a low level. That is, the inverter circuit 21e is set to be enabled when the frame signal Frame_e is at a high level.

The gate of transistor M6e is connected to node Bne. The drain of transistor M6e is connected to node An. The source of the transistor M6e is connected to the power supply terminal to which the voltage Vgl is supplied. The transistor M6e has a function of pulling down the potential of the node An.

The gate of transistor M7e is connected to node An. The drain of transistor M7e is connected to node Bne. The source of the transistor M7e is connected to the power supply terminal to which the voltage Vgl is supplied. The transistor M7e has a function of pulling down the potential of the node Bne.

The gate of transistor M1b is connected to node An. One end of the current path of transistor M1b is connected to node Bno. The other end of the current path of the transistor M1b is connected to the node Bne. The transistor M1b connects the node Bno and the node Bne when the node An is at a high level.

The output part 22 is a circuit for outputting an output signal to the scan line GL. The output unit 22 includes a transistor (also referred to as an output transistor) M3 and a capacitor Cb. The gate of transistor M3 is connected to node An. The clock signal Clk is input to the drain of the transistor M3. The clock signal Clk is one of the clock signals ClkA and ClkB, when the odd-numbered core circuit RG is the clock signal ClkA, and when the even-numbered core circuit RG is the clock signal ClkB. The source of transistor M3 is connected to node Qn.

One electrode of the capacitor Cb is connected to the node An, and the other electrode of the capacitor Cb is connected to the node Qn. The node Qn is connected to the corresponding scan line GL.

The pull-down portion 23 is a circuit for pulling down the potential of the node Qn. The pull-down portion 23 includes two transistors (also referred to as pull-down transistors) M4o and M4e. The gate of transistor M4o is connected to node Bno. The drain of transistor M4o is connected to node Qn. The source of the transistor M4o is connected to the power supply terminal to which the voltage Vgl is supplied.

The gate of transistor M4e is connected to node Bne. The drain of transistor M4e is connected to node Qn. The source of the transistor M4e is connected to the power supply terminal to which the voltage Vgl is supplied.

The clearing unit 24 is a circuit for clearing the node An and the node Qn. The clearing unit 24 includes two transistors M8 and M9. A clear signal CLR is input to the gate of the transistor M8 through the clear terminal CR. The drain of transistor M8 is connected to node Qn. The source of the transistor M8 is connected to the power supply terminal to which the voltage Vgl is supplied.

A clear signal CLR is input to the gate of the transistor M9 through the clear terminal CR. The drain of transistor M9 is connected to node An. The source of the transistor M9 is connected to the power supply terminal to which the voltage Vgl is supplied.

[4] Action

The operation of the liquid crystal display device 1 configured as described above will be described. FIG. 6 is a timing chart illustrating the basic operation of the liquid crystal display device 1 . The column numbers in FIG. 6 correspond to the numbers of the scan lines GL.

The control circuit 15 receives the signal Vsync from the outside. Once the signal Vsync becomes the low level, the period until the signal Vsync becomes the low level again is one frame. A single frame refers to a period during which all scanning lines are scanned once, and also refers to a period during which one image is displayed on the screen.

The shift register 11A operates according to a signal sent from the control circuit 15 . During one frame period, the core circuits RG1 to RGm included in the shift register 11A operate in a manner of sequentially outputting pulse signals.

FIG. 7 is a timing chart illustrating a more detailed operation of the liquid crystal display device 1 .

The frame signals Frame_o and Frame_e are alternately set to enable (high level) for each frame. The two inverter circuits 21o and 21e operate alternately in response to the frame signals Frame_o and Frame_e. The control circuit 15 switches the states of the frame signals Frame_o and Frame_e when the signal Vsync is at a low level.

As an example, it is assumed that the frame signal Frame_o is set to enabled (high level). The frame signal Frame_e is at a low level. When the frame signal Frame_o becomes a high level, the transistor M1o of the inverter circuit 21o is turned on, and the inverter circuit 21o is set to be enabled. The transistor M1e of the inverter circuit 21e is turned off, and the inverter circuit 21e is disabled.

After the frame signal Frame_o becomes a high level, the start signal ST is set to a high level. Thereby, the input signal VIN of the core circuit RG1 of the first stage becomes a high level. In this way, the transistor M2 of the input unit 20 is turned on, and the node An becomes a high level.

When the node An becomes a high level, the transistor M7o of the inverter circuit 21o is turned on, and the node Bno becomes a low level. That is, the inverter circuit 21o holds the inversion data of the node An at the node Bno. Thereby, the transistor M4o of the pull-down part 23 is turned off, and the pull-down operation of the node Qn is stopped.

In addition, when the node An becomes a high level, the transistor M3 of the output unit 22 is turned on. Next, the clock signal ClkA becomes a high level. As a result, the scan line GL1 becomes a high level.

The core circuit RG2 of the second stage receives the output signal from the core circuit RG1 of the previous stage as the input signal VIN. Next, the clock signal ClkB becomes a high level. In this way, the core circuit RG2 sets the scan line GL2 to a high level.

The core circuit RG1 of the first stage receives the output signal of the core circuit RG2 of the second stage as the reset signal RST. The reset signal RST is input to the gate of the transistor M5 of the input unit 20 . As a result, the transistor M5 is turned on, and the node An becomes a low level.

When the node An becomes a low level, the transistor M7o of the inverter circuit 21o is turned off, and the node Bno becomes a high level. That is, the inverter circuit 21o holds the inversion data of the node An at the node Bno. When the node Bno becomes a high level, the transistor M6o is turned on, and the node An remains at a low level. Thereby, the transistor M4o of the pull-down portion 23 is turned on, and the node Qn becomes a low level.

In addition, when the node An becomes a low level, the transistor M3 of the output unit 22 is turned off. Thereby, the scanning line GL1 is brought to a low level.

In addition, in the detailed design, it is designed so that the adjacent core circuits RG may not operate at the same time. Therefore, there is a space between the edges of each other so that the pulse wave of the clock signal ClkA and the pulse wave of the clock signal ClkB do not overlap.

Similarly, the core circuits RG3 to RGm sequentially output pulse signals.

After the core circuit RGm in the last stage outputs the pulse signal, the clear signal CLR is set to a high level. When the clear signal CLR becomes a high level, the transistors M8 and M9 of the clear unit 24 are turned on. In this way, the node Qn and the node An become low levels. Thereby, the core circuit RGm sets the scan line GLm to a low level.

Then, the frame signal Frame_e is set to a high level, and the frame signal Frame_o is set to a low level. In this way, the inverter circuit 21e of the core circuit RG is set to be enabled. Then, the scanning operation by the shift register 11A is repeated.

By the above-described operation, in the core circuit RG, the transistor to which the forward bias voltage is continuously applied can be removed. Thereby, it is possible to suppress deterioration of the characteristics of the transistors constituting the core circuit RG. Specifically, in the case of using a TFT as a transistor, when a forward bias voltage is continuously applied, the threshold voltage Vth is shifted. However, in the present embodiment, deterioration of the characteristics of the TFT can be suppressed.

Next, the inverter operation of the core circuit RG in the selection period will be described. The so-called selection period refers to the period during which the scan line is selected, and is the period during which the scan line outputs the pulse signal. The so-called non-selection period refers to a period other than the selection period, that is, a period in which no pulse signal is output from the scanning line.

FIG. 8 is a schematic diagram illustrating the inverter operation of the core circuit RG in the selection period. As an example, if the frame signal Frame_o is set to be enabled (high level (“Hi” in FIG. 8 )), the inverter circuit 21o performs the inverter operation. The frame signal Frame_e is at a low level (“Lo” in FIG. 8 ).

The input signal VIN of a high level (“ON” in FIG. 8 ) is input to the gate of the transistor M2 from the core circuit RG of the previous stage. Thereby, the transistor M2 is turned on, and the node An becomes a high level (“Hi” in FIG. 8 ).

A high-level frame signal Frame_o is input to the gate of the transistor M1o. Therefore, the transistor M1o is turned on, and the inverter circuit 21o is set to be enabled.

Since the node An is at a high level, the transistor M7o is turned on, and the node Bno is pulled down. Arrows in FIG. 8 indicate current flow.

In addition, the inverter operation in the selection period can also operate the transistor M7e of the inverter circuit 21e. That is, since the node An is at a high level, the transistors M1b and M7e are turned on. Therefore, node Bno is also pulled down by the paths of transistor M1b, node Bne, and transistor M7e. Thereby, the node Bno can be surely set to a low level.

The drive capability of the transistor M6o is set to be larger than the drive capability of the transistor M7o. During the non-selection period, the node An is pulled down by the transistor M6o, so that the node An can be surely set to the low level.

As for the conditions for realizing the above-described inverter operation, the transistors M6 and M7 are set so as to satisfy the following conditions. The transistor M6 refers to each of the transistors M6o and M6e, and the transistor M7 refers to each of the transistors M7o and M7e. The channel widths of the transistors M6 and M7 are denoted as W6 and W7, respectively. The channel width is also referred to as the gate width.

W7≦W6≦2×W7

By setting "W6≦2×W7", the combined driving capability of the transistors M7o and M7e is made larger than the driving capability of the transistor M6o (or the transistor M6e). Thereby, during the selection period, the node Bno can be surely set to the low level.

By setting "W7≦W6", the drive capability of the transistor M6 is made larger than the drive capability of the transistor M7. Thereby, during the non-selection period, the node An can be surely set to the low level.

Move your attention to the inverter circuit included in the core circuit RG near the last stage. Among the inverter circuits 21o and 21e, the potential of the node Bne of the disabled inverter circuit (for example, the inverter circuit 21e is assumed) is continuously lowered by the leak current of the transistor M1e. Therefore, in the core circuit RG near the last stage, by turning on the transistor M1b during the selection period, the node Bno and the node Bne on the enabled side are turned on, thereby making it possible to set more robustly. into a low-level architecture.

Next, detailed driving waveforms of the core circuit RG1 in the first stage will be described.

9 and 10 show the driving waveforms of the core circuit RG1 in the first stage. FIG. 9 shows the waveforms of nodes An, Bno, and Bne. FIG. 10 shows the waveforms of the frame signals Frame_o, Frame_e, and the scan line GL1. The horizontal axis of FIGS. 9 and 10 is time (msec), and the vertical axis is voltage (V). The waveform amplitude is Hi=11V, Lo=-10V. The pulse width of the scan line is about 70 μs, and the frame frequency is 60 Hz.

First, the frame signal Frame_o is enabled (high level), and the inverter circuit 21o is enabled. Next, the node An becomes the high level, and the node Bno becomes the low level by the inverter operation of the inverter circuit 21o. In addition, it can be seen that the node Bne of the inverter circuit 21e becomes the low level at the same time as the node Bno becomes the low level. Thereby, the gate voltages of the transistors M4e and M6e of the inverter circuit 21e are kept at a low level until the frame signal Frame_e becomes a high level. Then, at the timing when the clock signal ClkA is input, the pulse signal is output to the scan line GL1.

Next, the detailed driving waveform of the core circuit RGm in the last stage will be described.

11 and 12 are driving waveforms of the core circuit RGm in the last stage. FIG. 11 shows the waveforms of nodes An, Bno, and Bne. FIG. 12 shows the waveforms of the frame signals Frame_o, Frame_e, and the scan line GLm.

As in the case of the core circuit RG1, the node An becomes the high level, and the node Bno becomes the low level by the inverter operation of the inverter circuit 21o. Then, at the timing when the clock signal ClkA is input, the pulse signal is output to the scanning line GLm.

In addition, in the core circuit RGm in the last stage, the potential of the node Bne has become a low level before the scanning line GLm is selected due to the leakage current of the transistor M1e. Therefore, by turning on the transistor M1b to connect the node Bno and the node Bne, the node Bno can be set to a low level more robustly.

[5] Effects of Embodiment

According to the present embodiment, each core circuit RG includes two inverter circuits 21o and 21e, and the inverter circuits 21o and 21e are alternately enabled in response to the frame signals Frame_o and Frame_e. Therefore, it is possible to prevent the voltage from being continuously applied to the transistors (eg, TFTs) constituting the shift register 11A.

Specifically, deterioration of the characteristics of the transistor M6o whose gate is connected to the node Bno can be suppressed. Specifically, it is possible to suppress a shift in the threshold voltage of the transistor M6o. Thereby, it can suppress that the inverter circuit 21o becomes malfunctioning. The same applies to the transistor M6e. Therefore, malfunction of the shift register 11A can be suppressed.

Furthermore, it is possible to suppress deterioration of the characteristics of the transistor M4o whose gate is connected to the node Bno. Specifically, it is possible to suppress the shift of the threshold voltage of the transistor M4o. Thereby, the transistor M4o for pulling down the scanning line can be prevented from becoming malfunctioning. The same applies to the transistor M4e. Therefore, malfunction of the shift register 11A can be suppressed.

In addition, the node Bno and the node Bne are connected by the transistor M1b, and when the node An is at a high level, the node Bno and the node Bne are turned on. Thereby, for example, when the inverter circuit 21o is enabled, the node Bno can be set to the low level more reliably. Therefore, malfunction of the shift register 11A can be suppressed.

In addition, even if the number of scanning lines increases, the shift register 11A can be reliably operated.

In addition, in the above-mentioned embodiment, the voltage relationship between the frame signals Frame_o and Frame_e is switched every frame. However, it is not limited to this, and the voltage relationship between the frame signals Frame_o and Frame_e may be switched every two or more frame periods.

In addition, in the above-mentioned embodiment, the case where all the transistors are composed of N-type transistors has been described. However, it is not limited to this, and by inverting the polarities of the power supply voltage and the pulse signal, all the transistors can be formed of P-type transistors.

In addition, in the above-mentioned embodiment, the liquid crystal display device is taken as an example of a display device and demonstrated. However, it is not limited to this, and it can apply to other display apparatuses, such as an organic electroluminescent display apparatus.

The present invention is not limited to the above-described embodiment, and various modifications can be made in the implementation stage without departing from the gist of the present invention. In addition, each embodiment can also be implemented by combining suitably, and the effect of a combination can be acquired in this case. In addition, the above-mentioned embodiment includes various inventions, and various inventions can be extracted by a combination selected from a plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiment, as long as the problem can be solved and the effect can be obtained, the configuration of the deleted components can be extracted as an invention.

1: Liquid crystal display device 2, IC: integrated circuit 10: Pixel array 11: Scan line driver circuit 11-1, 11-2, GIP: scan line driver 11A: Shift register 12: Signal line driver circuit 13: Common electrode drive circuit 14: Voltage generation circuit 15: Control circuit 16: Switching element (active element) 20: Input section 21: Scratchpad Department 21e, 21o: Inverter circuit 22: Output part 23: Pull Down 24: Clearance Department An,Bne,Bno,Qn: Node Cb: capacitor Clc: Liquid crystal capacitor (liquid crystal element) Clk, ClkA, ClkB: clock signal CLK: Clock terminal CLR: clear signal CNT: control signal CR: Clear terminal Cs: storage capacitor DT: Image data Frame_e,Frame_o: Frame signal Fr_e,Fr_o: Frame terminals GL, GL1～GLm: scan line GND: ground voltage M1e, M1b, M1o, M2, M5, M6, M6e, M6o, M7, M7e, M7o, M8, M9: Transistor M3: Transistor (output transistor) M4e, M4o: Transistor (pull down transistor) OUT: output terminal px: pixel RG, RG1～RGm, RGi, RG(i+1): core circuit RST: reset signal RST_IN: reset terminal SL, SL1～SLn: Signal line ST: start signal Vcom: common voltage VIN: input signal Vgl: Voltage Vsync:Signal Vth: threshold voltage V_IN: input terminal W6, W7: The channel width of the transistor

FIG. 1 is a layout diagram of a liquid crystal display device according to an embodiment. FIG. 2 is a block diagram of the liquid crystal display device according to the embodiment. FIG. 3 is a circuit diagram of the pixel array shown in FIG. 2 . FIG. 4 is a block diagram of a shift register included in the scan line driving circuit. FIG. 5 is a circuit diagram of the core circuit shown in FIG. 4 . FIG. 6 is a timing chart illustrating the basic operation of the liquid crystal display device. FIG. 7 is a timing chart illustrating a more detailed operation of the liquid crystal display device. FIG. 8 is a schematic diagram illustrating the inverter operation of the core circuit during the selection period. FIG. 9 shows the driving waveforms of the core circuit of the first stage. FIG. 10 shows the driving waveforms of the core circuit of the first stage. Fig. 11 is the driving waveform of the core circuit of the last stage. Fig. 12 shows the driving waveforms of the core circuit of the last stage.

20: Input section

21: Scratchpad Department

21e, 21o: Inverter circuit

22: Output part

23: Pull Down

24: Clearance Department

An,Bne,Bno,Qn: Node

Cb: capacitor

Clk: clock signal

CLR: clear signal

Frame_e,Frame_o: Frame signal

GL: scan line

M1e, M1b, M1o, M2, M5, M6e, M6o, M7e, M7o, M8, M9: Transistor

M3: Transistor (output transistor)

M4e, M4o: Transistor (pull down transistor)

RG: core circuit

RST: reset signal

VIN: input signal

Vgl: Voltage

Claims (10)

A shift register is provided with a plurality of core circuits respectively connected to a plurality of scan lines and connected in series; Each of the aforementioned plurality of core circuits includes: an input part, which transfers the input signal corresponding to the output signal of the core circuit of the previous stage to the first node; a first inverter circuit, which is enabled by the first frame signal, and maintains the inverted signal of the first node at the second node; a second inverter circuit, which is set to be enabled by a second frame signal complementary to the first frame signal, and maintains the inverted signal of the first node at the third node; The output unit includes an output transistor and a capacitor, and the output transistor system has a gate connected to the first node, a first terminal that receives a first clock signal or a second clock signal, and a gate connected to the scan line. a second terminal, wherein the capacitor has a first electrode connected to the first node and a second electrode connected to the scan line; a first pull-down transistor having a gate connected to the second node, a first terminal connected to the scan line, and a second terminal supplied with a reference voltage; and a second pull-down transistor having a gate connected to the third node, a first terminal connected to the scan line, and a second terminal supplied with the reference voltage; The odd-numbered core circuits receive the aforementioned first clock signal; The even-numbered core circuits receive the second clock signal complementary to the first clock signal. The shift register of claim 1, further comprising a first transistor, the first transistor system is connected between the second node and the third node, and has a gate connected to the first node . The shift register of claim 1 or 2, wherein the first inverter circuit includes second and third transistors; the second transistor system has a gate connected to the second node, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied; the third transistor system has a gate connected to the first node, a first terminal connected to the second node, and a second terminal to which the reference voltage is supplied; The aforementioned second inverter circuit includes fourth and fifth transistors; the fourth transistor system has a gate connected to the third node, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied; The fifth transistor system has a gate connected to the first node, a first terminal connected to the third node, and a second terminal to which the reference voltage is supplied. The shift register of claim 3, wherein when the channel width of the second transistor is set to be W1, and the channel width of the third transistor is set to be W2, there is the following relationship: W2≦W1≦2×W2. The shift register of claim 1 or 2, wherein the first inverter circuit includes a sixth transistor that transfers the first frame signal to the second node; The second inverter circuit includes a seventh transistor that transfers the second frame signal to the third node. The shift register of claim 1 or 2, wherein the input part includes a reset transistor, and the reset transistor system has a gate to which a reset signal corresponding to the output signal of the core circuit of the next stage is input. pole, a first terminal connected to the first node, and a second terminal to which the reference voltage is supplied. The shift register of claim 6, wherein the gate of the reset transistor included in the core circuit of the last stage is set to enable after the output signal of the core circuit of the last stage is set to enable able to clear the signal. The shift register according to claim 1 or 2, wherein the input part of the core circuit of the first stage is input with a start signal for starting the scanning operation. A display device is provided with the shift register as claimed in item 1. The display device of claim 9, further comprising a pixel array comprising a plurality of pixels; The plurality of scan lines are connected to the pixel array.

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