TWI814290B - display device - Google Patents

Abstract

The display device of the present invention includes: a display area having a plurality of divided areas arranged in rows and columns; a pixel array having a plurality of sub-arrays respectively arranged in the plurality of divided areas; each of the plurality of sub-arrays has a plurality of pixels; A plurality of scan lines are provided in each of a plurality of sub-arrays and extend along the first direction; a plurality of signal lines are formed in a manner that is jointly connected to the sub-array groups of each row and are provided in the pixel array and extend along the second direction; A gate driver is configured in a plurality of divided areas, each of which is connected to a plurality of scan lines; a source driver is connected to a plurality of signal lines; and a control circuit controls a plurality of gate drivers and source drivers to be able to Drive complex subarrays individually.

Description

display device

The present invention relates to a display device.

An active matrix (active matrix) liquid crystal display device using thin film transistors (TFT; Thin Film Transistor) as an active element or an organic EL (electroluminescence; electroluminescence) display device has TFTs arranged in a matrix. The substrate made of it (called TFT substrate). The TFT substrate has a plurality of signal lines each extending in a column direction and receiving image signal input, and a plurality of scanning lines each extending in a column (row) direction.

In recent years, a gate driver that drives a scan line has been formed on a TFT substrate, thereby reducing the cost of a driver IC (Integrated Circuit) and narrowing the frame of a display panel. In addition, by forming the gate driver on the TFT substrate, the restriction of scanning line wiring is eliminated, so it becomes a technology that can also be used for special-shaped display panels with high requirements such as automotive applications. The above-mentioned technology is called GIP (Gate driver in panel; gate driver in panel), or GOA (Gate driver on array; gate driver array).

GIP or GOA is an extremely important technology for realizing narrow bezels and free-shaped display panels at low cost. However, in a structure in which circuits are arranged on the frame, a circuit arrangement area is required, so there is a limit to narrowing the frame. In addition, when considering reliability issues (especially light leakage), you have to accept some degree of bezel.

Under such circumstances, a technology has been proposed in which a gate driver is installed in the display area. This technology was developed for the purpose of splicing panels into multi-panels by narrowing the bezels, and for forming a foldable display structure. This technology has attracted attention as a technology suitable for narrow bezels and accompanying special-shaped displays. [Prior technical literature] [Patent Document]

Patent Document 1: Japanese Patent No. 6077704 Patent Document 2: Japanese Patent Application Publication No. 2019-91516

[Problem to be solved by the invention]

The present invention provides a display device capable of reducing power consumption. [Means used to solve problems]

According to a first aspect of the present invention, there is provided a display device including: a display area having a plurality of divided areas arranged in rows and columns; and a pixel array having a plurality of sub arrays respectively arranged in the plurality of divided areas. , each of the aforementioned plurality of sub-arrays has a plurality of pixels; a plurality of scan lines are provided in each of the aforementioned plurality of sub-arrays and extend along the first direction; a plurality of signal lines are jointly connected to the sub-array groups of each row. The method is configured and arranged in the aforementioned pixel array, extending along a second direction crossing the aforementioned first direction; a plurality of gate drivers are respectively arranged in the aforementioned plurality of divided areas, each of which is connected to the aforementioned plurality of scan lines; the source electrode (source) driver, connected to the aforementioned plurality of signal lines; and a control circuit, controlling the aforementioned plurality of gate drivers and the aforementioned source driver, capable of individually driving the aforementioned plurality of sub-arrays.

According to a second aspect of the present invention, there is provided a display device including: a display area including a plurality of divided areas arranged in rows and columns; a non-display area provided in at least one divided area among the plurality of divided areas; and No pixels are arranged; the pixel array has a plurality of sub-arrays respectively arranged in the remaining divided areas, and each of the plurality of sub-arrays has a plurality of pixels; and a plurality of scan lines are provided in each of the aforementioned plurality of sub-arrays along the first plurality of sub-arrays. Extending in the 1st direction; a plurality of signal lines are configured to be commonly connected to the sub-array groups of each row and are provided in the aforementioned pixel array, extending in a second direction that intersects the aforementioned 1st direction; a plurality of gate drivers are respectively arranged in Each of the aforementioned remaining divided areas is connected to the aforementioned plurality of scan lines; the source driver is connected to the aforementioned plurality of signal lines; and the control circuit controls the aforementioned plurality of gate drivers and the aforementioned source driver, and can individually drive the aforementioned plurality of gate drivers. Complex subarray.

According to a third aspect of the present invention, there is provided a display device of the first or second aspect, wherein the control circuit sequentially drives the sub-array groups arranged along the row direction.

According to a fourth aspect of the present invention, there is provided a display device of the first or second aspect, wherein the control circuit simultaneously drives the sub-array groups arranged in the column direction.

According to a fifth aspect of the present invention, there is provided a display device of the first or second aspect, in which a start signal for starting scanning is input to the gate driver groups of each column in common.

According to a sixth aspect of the present invention, there is provided a display device of the first or second aspect, in which a clock signal is commonly input to the gate driver groups of each column.

According to a seventh aspect of the present invention, there is provided a display device of the first or second aspect, in which clock signals are commonly input to the gate driver groups of each row.

According to an eighth aspect of the present invention, there is provided a display device according to a fifth aspect, wherein a clear signal for stopping scanning is input to each of the plurality of gate drivers.

According to a ninth aspect of the present invention, there is provided a display device of an eighth aspect, wherein the control circuit inputs the clear signal immediately after the start signal is input to the first gate driver, and the control circuit is connected to the first gate driver. The rewriting of data (data) in the subarray of the pole driver is stopped.

According to a tenth aspect of the present invention, there is provided a display device of the first or second aspect, wherein each of the plurality of gate drivers includes a shift buffer having a plurality of core circuits connected in series. (shift register); each of the plurality of core circuits mentioned above includes: an input part that transfers the input signal corresponding to the output signal of the core circuit in the previous stage to the first node; a first inverter ) circuit is enabled by the first frame signal and maintains the inversion signal of the first node at the second node; and the second inverter circuit is enabled by the first frame signal. The complementary second frame signal is set to enable, and the inversion signal of the first node is maintained at the third node.

According to an eleventh aspect of the present invention, there is provided a display device of a tenth aspect, wherein the core circuit includes an output unit; the output unit includes an output transistor and a capacitor; and the output transistor system has: connected to The gate of the aforementioned first node, the first terminal for receiving the clock signal, and the second terminal connected to the scan line; The capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line.

According to a twelfth aspect of the present invention, a display device of an eleventh aspect is provided, in which the odd-numbered core circuit receives a first clock signal; the even-numbered core circuit receives a third clock signal that is complementary to the first clock signal. 2 clock signal. [Effects of the invention]

According to the present invention, a display device capable of reducing power consumption can be provided.

[Form used to implement the invention]

Hereinafter, embodiments will be described with reference to the drawings. However, the diagrams are schematic or conceptual, and the size and ratio of each diagram may not be the same as the actual size. In addition, dimensional relationships and ratios may differ between drawings even if the same parts are shown. Specifically, several embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. The technical idea of the present invention is not limited by the shape, structure, arrangement, etc. of the constituent parts. . In addition, in the following description, elements having the same functions and structures are given the same reference numerals, and repeated descriptions are omitted.

In this embodiment, a liquid crystal display device will be described as an example of a display device. The liquid crystal display device of this embodiment has a structure in which a gate driver is arranged in a display area.

[1] First embodiment [1-1] Configuration of liquid crystal display device 1 FIG. 1 is a schematic layout diagram of a liquid crystal display device 1 according to the first embodiment of the present invention. In FIG. 1 , the X direction is the column direction in which the scanning lines GL extend, and the Y direction is the row direction in which the signal lines SL extend. The liquid crystal display device 1 includes a TFT substrate 2 , an integrated circuit (IC) 3 , a pixel array 10 , and a gate driver group 11 .

The TFT substrate 2 is composed of a transparent insulating substrate, such as a glass substrate or a plastic substrate. On the TFT substrate 2, a pixel array 10, a gate driver group 11, and an integrated circuit 3 are provided. A counter substrate (not shown) is disposed above the TFT substrate 2, and a liquid crystal layer (not shown) is disposed between the TFT substrate 2 and the counter substrate.

The pixel array 10 is provided with a plurality of scanning lines GL each extending in the X direction and a plurality of signal lines SL each extending in the Y direction. The area where the pixel array 10 is arranged corresponds to the display area.

The gate driver group 11 is arranged in the display area. In addition, a part of the gate driver group 11 is arranged in the peripheral area around the display area. The surrounding area corresponds to the border. The gate driver group 11 is connected to a plurality of scan lines GL.

The integrated circuit 3 is connected to a plurality of signal lines SL. In addition, the integrated circuit 3 is connected to the gate driver group 11 . The integrated circuit 3 is composed of an IC chip.

FIG. 2 is a block diagram of the liquid crystal display device 1 . The liquid crystal display device 1 includes a pixel array 10 , a gate driver group 11 , a source driver 12 , a common electrode driver 13 , a voltage generation circuit 14 , and a control circuit 15 . The integrated circuit 3 shown in FIG. 1 includes the source driver 12, the common electrode driver 13, the voltage generating circuit 14, and the control circuit 15 shown in FIG. 2.

The pixel array 10 includes a plurality of pixels arranged in a matrix. The pixel array 10 includes a plurality of sub-arrays arranged in a matrix. The specific structure of the subarray will be described later. The pixel array 10 is provided with a plurality of scanning lines GL each extending in the X direction and a plurality of signal lines SL each extending in the Y direction. Pixels are arranged in the intersection area of the scanning line GL and the signal line SL.

The gate driver group 11 is electrically connected to the plurality of scan lines GL. The gate driver group 11 includes a plurality of gate drivers corresponding to the aforementioned plurality of sub-arrays. The specific structure of the gate driver will be described later. The gate driver group 11 sends scanning signals for turning on/off the switching elements included in the pixels to the pixel array 10 based on the control signal sent from the control circuit 15 .

The source driver 12 is electrically connected to a plurality of signal lines SL. The source driver 12 receives control signals and display data from the control circuit 15 . The source driver 12 sends the tone signal (driving voltage) corresponding to the display data to the pixel array 10 according to the control signal.

The common electrode driver 13 generates a common voltage Vcom and supplies the common voltage Vcom to the common electrode in the pixel array 10 . The common electrode is an electrode provided to face the plurality of pixel electrodes provided for each of the plurality of pixels across the liquid crystal layer.

The voltage generation circuit 14 generates various voltages required for the operation of the liquid crystal display device 1 and supplies these voltages to corresponding circuits.

The control circuit 15 systematically controls the operation of the liquid crystal display device 1 . The control circuit 15 receives image data DT and control signal CNT from the outside. The control circuit 15 generates various control signals based on the image data DT, and sends these control signals to the corresponding circuits.

[1-1-1] Structure of display area 4 The area in the TFT substrate 2 where the pixel array 10 is disposed constitutes the display area 4 . Figure 3 is a schematic diagram showing area 4.

The display area 4 includes a plurality of divided areas DI_(1,1) to DI_(m,n) arranged in a matrix (m columns×n rows). "m" and "n" are each an integer of 2 or more. The number of divided areas DI included in the display area 4 can be set arbitrarily. In this embodiment, the description of the component symbol DI omitting the suffix (m, n) is commonly applied to a plurality of divided areas. The same applies to other component symbols with suffixes.

A sub-array SA and a gate driver GD are provided in each divided area DI.

FIG. 4 is a schematic diagram of the pixel array 10 shown in FIG. 2 . The pixel array 10 includes a plurality of sub-arrays SA_(1,1) to SA_(m,n) arranged in a matrix (m columns×n rows). The plurality of sub-arrays SA_(1,1) to SA_(m,n) are respectively located in the divided areas DI_(1,1) to DI_(m,n).

Each sub-array SA includes a plurality of pixels PX arranged in a matrix. A plurality of scanning lines GL are arranged in one sub-array SA. That is, a plurality of sub-arrays SA can be scanned individually. A plurality of sub-arrays SA included in each row (that is, a plurality of sub-arrays SA arranged along the row direction) are connected to a common signal line SL.

FIG. 5 is a schematic diagram of the gate driver group 11 shown in FIG. 2 . The gate driver group 11 includes a plurality of gate drivers GD_(1,1) to GD_(m,n) arranged in a matrix (m columns×n rows). The gate drivers GD_(1,1) to GD_(m,n) are respectively located in the divided areas DI_(1,1) to DI_(m,n). Each gate driver GD is connected to a plurality of scan lines GL configured in the corresponding sub-array SA, and scans the plurality of scan lines GL. FIG. 5 schematically shows how a plurality of circuit elements constituting the gate driver GD are dispersedly arranged in the divided area DI.

FIG. 6 is a circuit diagram of the sub-array SA shown in FIG. 4 . The sub-array SA is provided with a plurality of scanning lines GL1 to GLi and a plurality of signal lines SL1 to SLj. "i" and "j" are integers each of 2 or more.

The pixel PX system includes a switching element (active element) 16, a liquid crystal capacitor (liquid crystal element) Clc, and a storage capacitor Cs. For the switching element 16 , for example, a TFT (Thin Film Transistor) or an n-channel TFT is used. In addition, the source and drain of the transistor change according to the direction of the current flowing through the transistor. The following description is an example of the connection state of the transistor. However, it goes without saying that source and drain are not fixed by name.

The source of the TFT 16 is connected to the signal line SL, the gate is connected to the scanning line GL, and the drain is connected to an electrode of the liquid crystal capacitor Clc. The liquid crystal capacitor Clc as a liquid crystal element is composed of a pixel electrode, a common electrode, and a liquid crystal layer sandwiched between the pixel electrode and the common electrode. The common voltage Vcom is applied to the other electrode of the liquid crystal capacitor Clc through the common electrode driver 13 .

An electrode of the storage capacitor Cs is connected to an electrode of the liquid crystal capacitor Clc. The other electrode of the storage capacitor Cs is connected to the storage capacitor line (also called storage electrode) CsL. The storage capacitor Cs has the function of suppressing the potential variation occurring in the pixel electrode and maintaining the driving voltage applied to the pixel electrode until the driving voltage corresponding to the next signal is applied. The storage capacitor Cs is composed of a pixel electrode, a storage capacitor line CsL, and an insulating film sandwiched between the pixel electrode and the storage capacitor line CsL. The storage capacitor voltage Vcs is applied to the storage capacitor line CsL by the voltage generating circuit 14 . The storage capacitor voltage Vcs is set to the same voltage as the common voltage Vcom, for example.

[1-1-2] Structure of gate driver GD Next, the structure of the gate driver GD will be described. The gate driver GD has a shift register SR. Figure 7 is a block diagram of the shift register SR included in the gate driver GD.

The shift register SR has a plurality of core circuits RG1 to RGi. The core circuits RG1 to RGi are respectively designed to correspond to the scan lines GL1 to GLi.

A plurality of core circuits RG1 to RGi are connected in series. Each core circuit RG functions as a temporary register for temporarily storing input data. The shift register SR operates synchronously with the clock signal to sequentially shift the input data (pulse signal).

Each core circuit RG is configured to output a pulse wave signal in accordance with the conditions of a plurality of signals input to it. Each core circuit RG system has: an input terminal V_IN, an output terminal OUT, a frame terminal Fr_o, a frame terminal Fr_e, a clock terminal CLK, a clear terminal CR, and a reset terminal RST_IN.

The plurality of core circuits RG1 to RGi are configured in such a manner that the output terminal OUT of any core circuit RG is connected to the input terminal V_IN of the core circuit RG of the next stage to form a cascade connection. In addition, the start signal ST is input to the input terminal V_IN of the first-stage core circuit RG1.

The frame signal Frame_o is input to the frame terminals Fr_o of the core circuits RG1 to RGi. The frame signal Frame_e is input to the frame terminals Fr_e of the core circuits RG1 to RGi. The clear signal CLR is input to the clear terminal CR of the core circuits RG1 to RGi.

The clock signal ClkA is input to the clock terminal CLK of the odd-numbered core circuits RG1, RG3, .... The clock signal ClkB is input to the clock terminal CLK of the even-numbered core circuits RG2, RG4, .... The clock signal ClkA and the clock signal ClkB have a complementary phase relationship.

The output terminal OUT of any core circuit RG is connected to the reset terminal RST_IN of the core circuit RG in the previous section. The clear signal CLR is input to the reset terminal RST_IN of the core circuit RGi in the last stage.

The output terminals OUT of the plurality of core circuits RG1 to RGi are respectively connected to the scan lines GL1 to GLi. The capacitors connected to each scan line GL in FIG. 7 are simplified expressions of the capacitance of the pixels connected to the scan lines.

The control circuit 15 generates the aforementioned frame signal Frame_o, frame signal Frame_e, clock signal ClkA, clock signal ClkB, and clear signal CLR, and supplies these signals to the shift register SR.

[1-1-3] The specific composition of the core circuit RG Next, the specific structure of the core circuit RG will be described. FIG. 8 is a circuit diagram of the core circuit RG shown in FIG. 7 . The core circuit RG includes an input unit 20, a register unit 21, an output unit 22, a pull-down unit 23, and a clearing unit 24. The core circuit RG is composed of N-channel TFT. Hereinafter, TFT may be referred to as transistor in some cases. In this specification, one of the source and the drain of the transistor may be called a first terminal, and the other may be called a second terminal.

The input unit 20 is a circuit for receiving the input signal VIN. The input unit 20 is provided with two transistors M2 and M5. The input signal VIN is input to the gate of the transistor M2 through the input terminal V_IN. The input signal VIN corresponds to the output signal of the core circuit RG in the previous section. The drain of transistor M2 is connected to its gate. That is, the transistor M2 is connected as a diode. The source of transistor M2 is connected to node An. The transistor M2 transfers the input signal VIN to the node An when the input signal VIN is at a high level, and is turned off when the input signal VIN is at a low level.

The reset signal RST is input to the gate of the transistor (also called reset transistor) M5 through the reset terminal RST_IN. The reset signal RST corresponds to the output signal of the core circuit RG of the next section. The drain of transistor M5 is connected to node An. The source of transistor M5 is connected to a power terminal supplied with voltage Vgl. The voltage Vgl is a reference voltage used to set the signal to a low level, and is a voltage lower than the high level voltage of the signal. The voltage Vgl is, for example, a negative voltage lower than the ground voltage GND and is set in the range of -10V to -20V.

The register unit 21 is a circuit for holding the voltage applied to the capacitor Cb in the selected state and the non-selected state. The register unit 21 includes two inverter circuits 21o and 21e, and a transistor M1b.

The inverter circuit 21o includes three transistors M1o, M6o, and M7o. The frame signal Frame_o is input to the gate of the transistor M1o through the frame terminal Fr_o. The drain of transistor M1o is connected to its own gate. The source of transistor M1o is connected to node Bno. The transistor M1o transfers the frame signal Frame_o to the node Bno when the frame signal Frame_o is at a high level, and is turned off when the frame signal Frame_o is at a low level. That is, the inverter circuit 21o is set to be enabled when the frame signal Frame_o is at a high level.

The gate of transistor M6o is connected to node Bno. The drain of transistor M6o is connected to node An. The source of transistor M6o is connected to a power terminal supplied with voltage Vgl. The transistor M6o system has the function of pulling down the potential of the node An.

The gate of transistor M7o is connected to node An. The drain of transistor M7o is connected to node Bno. The source of transistor M7o is connected to a power terminal supplied with voltage Vgl. The transistor M7o has the function of pulling down the potential of the node Bno.

The inverter circuit 21e includes three transistors M1e, M6e, and M7e. The frame signal Frame_e is input to the gate of the transistor M1e through the frame terminal Fr_e. The drain of transistor M1e is connected to its gate. The source of transistor M1e is connected to node Bne. The transistor M1e transfers the frame signal Frame_e to the node Bne when the frame signal Frame_e is at a high level, and is turned off when the frame signal Frame_e is at a low level. That is, the inverter circuit 21e is enabled when the frame signal Frame_e is at a high level.

The gate of transistor M6e is connected to node Bne. The drain of transistor M6e is connected to node An. The source of transistor M6e is connected to a power terminal supplied with voltage Vgl. The transistor M6e has the function of pulling down the potential of the node An.

The gate of transistor M7e is connected to node An. The drain of transistor M7e is connected to node Bne. The source of the transistor M7e is connected to a power terminal supplied with the voltage Vgl. The transistor M7e has the function of pulling down the potential of the node Bne.

The gate of transistor M1b is connected to node An. One end of the current path of transistor M1b is connected to node Bno. The other end of the current path of transistor M1b is connected to node Bne. The transistor M1b connects the node Bno and the node Bne when the node An is at a high level.

The output unit 22 is a circuit for outputting an output signal to the scanning line GL. The output unit 22 includes a transistor (also referred to as an output transistor) M3 and a capacitor Cb. The gate of transistor M3 is connected to node An. The clock signal Clk is input to the drain system of the transistor M3. The clock signal Clk is any one of the clock signals ClkA and ClkB. When it is the odd-numbered core circuit RG, it is the clock signal ClkA, and when it is the even-numbered core circuit RG, it is the clock signal ClkB. The source of transistor M3 is connected to node Qn.

One electrode of the capacitor Cb is connected to the node An, and the other electrode of the capacitor Cb is connected to the node Qn. Node Qn is connected to the corresponding scan line GL.

The pull-down part 23 is a circuit for pulling down the potential of the node Qn. The pull-down part 23 is provided with two transistors (also called pull-down transistors) M4o and M4e. The gate of transistor M4o is connected to node Bno. The drain of transistor M4o is connected to node Qn. The source of transistor M4o is connected to a power terminal supplied with voltage Vgl.

The gate of transistor M4e is connected to node Bne. The drain of transistor M4e is connected to node Qn. The source of the transistor M4e is connected to a power terminal supplied with the voltage Vgl.

The clearing unit 24 is a circuit for clearing the node An and the node Qn. The cleaning unit 24 is provided with two transistors M8 and M9. The clear signal CLR is input to the gate of the transistor M8 through the clear terminal CR. The drain of transistor M8 is connected to node Qn. The source of transistor M8 is connected to a power terminal supplied with voltage Vgl.

The clear signal CLR is input to the gate of the transistor M9 through the clear terminal CR. The drain of transistor M9 is connected to node An. The source of transistor M9 is connected to a power terminal supplied with voltage Vgl.

[1-2] Configuration of gate driver GD Next, the configuration of the gate driver GD will be described. FIG. 9 is a schematic diagram illustrating the arrangement area GA of the gate driver GD.

The area between the pixels PX adjacent in the X direction and the area between the pixels PX adjacent in the Y direction are used as the gate driver arrangement area GA.

The gate driver GD system has a plurality of circuit components (active components) AE. The circuit element AE is composed of a transistor (TFT) and a capacitor. The circuit element AE is arranged in the gate driver arrangement area GA.

In the example of FIG. 9 , the gate driver arrangement area GA is provided with wiring constituting the node An (referred to as the An line) and a power supply line (referred to as the Vgl line) for supplying the voltage Vgl.

Hereinafter, the configuration of the register section 21, the output section 22, the clearing section 24, the input section 20, and the pull-down section 23 included in the core circuit RG will be described in order.

[1-2-1] Configuration of register section 21 FIG. 10 is a layout diagram of the register unit 21. FIG. 10 shows seven pixels PX connected to one scanning line GL and a gate driver arrangement area GA for one column.

The transistors M1b, M1e, M1o, M6e, M6o, M7e, and M7o constituting the register unit 21 are arranged in the gate driver arrangement area GA. In addition, the gate driver arrangement area GA is provided with an An line, a Vgl line, a wiring constituting the node Bne (called the Bne line), a wiring constituting the node Bno (called the Bno line), and a wiring supplying the frame signal Frame_e ( (called Frame_e line), and the wiring supplying the frame signal Frame_o (called Frame_o line). The connection relationship of the plurality of transistors constituting the register unit 21 is the same as that in FIG. 8 .

In addition, the width of the gate driver configuration area GA is limited. Therefore, a plurality of transistors are connected in parallel to form a transistor having one function. In this way, the size of the transistor is designed so that each transistor is accommodated in the gate driver arrangement area GA.

[1-2-2] Arrangement of output unit 22 and clearing unit 24 FIG. 11 is a layout diagram of the output unit 22 and the clearing unit 24. FIG. 11 shows 10 pixels PX connected to two scanning lines GL and a gate driver arrangement area GA for two columns.

The transistor M3 and the capacitor Cb constituting the output unit 22, and the transistors M8 and M9 constituting the clearing unit 24 are arranged in the gate driver arrangement area GA. In addition, the gate driver arrangement area GA is provided with an An line, a Vgl line, a line for supplying the clock ClkA (called a ClkA line), a line for supplying the clock ClkB (called a ClkB line), and a line for supplying the clear signal CLR. Wiring (called CLR line). The connection relationship between the plurality of elements constituting the output unit 22 and the clearing unit 24 is the same as that in FIG. 8 .

Capacitor Cb is formed by connecting a plurality of capacitors in parallel because of its large size. Although illustration is omitted, the output transistor M3 is configured by connecting a plurality of transistors in parallel because of its large size.

The clock ClkA and the clock ClkB are alternately supplied to a plurality of core circuits RG. In FIG. 11 , the output unit 22 that receives the supply of the clock ClkA and the output unit 22 that receives the supply of the clock ClkB are shown.

[1-2-3] Configuration of input unit 20 FIG. 12 is a layout diagram of the input unit 20. FIG. 12 shows six pixels PX connected to two scanning lines GL and a gate driver arrangement area GA for two columns.

The transistors M2 and M5 constituting the input unit 20 are arranged in the gate driver arrangement area GA. In addition, the gate driver arrangement area GA is provided with an An line, a Vgl line, a line for supplying the input signal VIN (called the VIN line), and a line for supplying the reset signal RST (called the RST line). The connection relationship between the plurality of transistors constituting the input unit 20 is the same as that in FIG. 8 .

Any scan line GL is connected to the transistor M2 included in the input unit 20 of the next stage using the VIN line. Any scan line GL is connected to the transistor M5 included in the input unit 20 in the previous stage using the RST line.

[1-2-4] Arrangement of pull-down part 23 FIG. 13 is a layout diagram of the pull-down part 23. FIG. 13 shows three pixels PX connected to one scanning line GL and a gate driver arrangement area GA for one column.

The transistor M4e constituting the pull-down portion 23 is arranged in the gate driver arrangement area GA. In addition, the An line and the Vgl line are arranged in the gate driver configuration area GA. The transistor M4o constituting the pull-down portion 23 is arranged in the gate driver arrangement area GA like the transistor M4e. The connection relationship between the plurality of transistors constituting the pull-down portion 23 is the same as that in FIG. 8 .

[1-3] Wiring of multiple divided areas DI Next, the wiring of the plurality of divided areas DI will be described.

FIG. 14 is a diagram illustrating the wiring of a plurality of divided areas DI. Hereinafter, description will be given as an example of a case where the display area 4 is composed of 9 (=3×3) divided areas DI_(1,1) to DI_(3,3).

The wiring to the plurality of divided areas DI is performed as follows. ． The gate driver GD is configured for each divided area DI. ． The power supply wiring system only wires the Vgl line. ． The Frame_e line and the Frame_o line are wired as common signals for the entire screen. ． CLR lines are routed for each divided area DI. ． The ST line (the wiring for supplying the start signal ST), the ClkA line, and the ClkB line are wired for each divided area DI in the scanning line direction (X direction).

The start signal ST is composed of three start signals ST1 to ST3. The start signals ST1 to ST3 are supplied respectively using three lines ST1 to ST3.

The clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. The clock signals ClkA1 to ClkA3 are supplied respectively using three ClkA1 lines to ClkA3 lines.

The clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. The clock signals ClkB1 to ClkB3 are supplied respectively using three ClkB1 lines to ClkB3 lines.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. The clear signals CLR11 to CLR33 are supplied using 9 CLR11 lines to CLR33 lines.

The start signal ST1 is input to the divided areas DI_(1,1), DI_(1,2), and DI_(1,3) of the first column. The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) of the second column. The start signal ST3 is input to the divided areas DI_(3,1), DI_(3,2), and DI_(3,3) of the third column. The nine divided areas DI_(1,1) to DI_(3,3) can be started in column units.

The clock signals ClkA1 and ClkB1 are input to the divided areas DI_(1,1), DI_(1,2) and DI_(1,3) of the first column. The clock signals ClkA2 and ClkB2 are input to the divided areas DI_(2,1), DI_(2,2) and DI_(2,3) of the second column. The clock signals ClkA3 and ClkB3 are input to the divided areas DI_(3,1), DI_(3,2) and DI_(3,3) of the third column. The nine divided areas DI_(1,1) to DI_(3,3) can be clocked in column units.

The nine clear signals CLR11 to CLR33 are respectively input to the nine divided areas DI_(1,1) to DI_(3,3). The 9 divided areas DI_(1,1) to DI_(3,3) can use the 9 clear signals CLR11 to CLR33 to individually stop scanning and prevent data from being rewritten (the display will be maintained).

The frame signal Frame_e is input to all divided areas DI. The frame signal Frame_o is input to all divided areas DI. The Vgl line is routed to all divided areas DI.

[1-4] Example of display area 4 Next, an example of the display area 4 will be described. FIG. 15 is a schematic diagram illustrating an embodiment of the display area 4. Assume that the column number m of the divided area DI, the row number n of the divided area DI, and the scanning line number i within the divided area DI are assumed.

The display area 4 has, for example, (480×640) pixels. The display area 4 has nine divided areas DI_(1,1) to DI_(3,3).

The number of scanning lines in each divided area DI is 160. The number of rows of the divided area DI in the first row is 213. The number of rows of the divided area DI in the second row is 214. The number of rows of the divided area DI in the third row is 213. The number of rows in the divided area DI corresponds to the number of signal lines SL.

[1-5] Action The operation of the liquid crystal display device 1 configured as above will be described.

[1-5-1] Scanning operation of display area 4 First, the scanning operation of one divided area DI will be described. FIG. 16 is a timing chart illustrating the scanning operation of the divided area DI.

The control circuit 15 receives the signal Vsync from the outside. The period from when the signal Vsync once reaches the low level until it reaches the low level again (or the period during which the signal Vsync is at the high level) is one frame. One frame refers to the period during which all the scanning lines included in the subarray SA are scanned once, and also refers to the period during which one image is displayed up to the divided area DI.

In any divided area DI_(m,n), clock signals ClkAm, ClkBm, start signal STm, and clear signal CLRmn are input.

The control circuit 15 responds to the low level of the signal Vsync and inputs the start signal STm to the divided area DI_(m,n). The gate driver GD_(m,n) responds to the start signal STm and starts the scanning operation.

The control circuit 15 inputs the clock signals ClkAm and ClkBm to the divided areas DI_(m,n). The clock signal ClkAm and the clock signal ClkBm have a complementary phase relationship. The gate driver GD_(m,n) responds to the clock signals ClkAm and ClkBm to perform a scanning operation, that is, to set a plurality of scanning lines GL to a high level in sequence.

After the last scan line GLi becomes a high level, the control circuit 15 sets the clear signal CLRmn to a high level. Thereby, the shift register SR of the gate driver GD_(m,n) is cleared, that is, the output of the shift register SR becomes a low level. In this way, the data of the divided area DI_(m,n) is rewritten.

Next, the scan stop operation of one divided area DI will be described. FIG. 17 is a timing chart explaining the scanning stop operation of the divided area DI. FIG. 17 shows the operation of a divided area in which data is not rewritten among the divided areas in the same column to which the start signal STm is input.

The control circuit 15 responds to the low level of the signal Vsync and inputs the start signal STm to the divided area DI_(m,n). Next, the control circuit 15 inputs the clear signal CLRmn to the divided area DI_(m,n) immediately after the start signal STm. Thereby, the start signal STm can be substantially disabled. Then, no pulse wave is input to the scanning line GL. At this time, the divided area DI_(m,n) is not scanned and remains displayed.

[1-5-2] Drive mode Next, the driving mode of the liquid crystal display device 1 will be described. Hereinafter, as an example, the operation of m=3, n=3, that is, nine divided areas DI_(1,1) to DI_(3,3) will be described.

FIG. 18 is a schematic diagram illustrating drive mode 1 of the liquid crystal display device 1 . In the first frame, the control circuit 15 sets the start signal ST1 to enable (high level). The control circuit 15 sets the clear signals CLR11, CLR12, and CLR13 to enable (high level) at the end of the first frame. Thereby, the scanning operation of the divided areas DI_(1,1) to DI_(1,3) of the first column is performed.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21, CLR22, and CLR23 at the end of the second frame. Thereby, the scanning operation of the divided areas DI_(2,1) to DI_(2,3) of the second column is performed.

The control circuit 15 enables the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31, CLR32, and CLR33 at the end of the third frame. Thereby, the scanning operation of the divided areas DI_(3,1) to DI_(3,3) of the third column is executed.

FIG. 19 is a schematic diagram illustrating drive mode 2 of the liquid crystal display device 1 . The control circuit 15 is in the first frame and enables the start signal ST1. The control circuit 15 enables the clear signals CLR12 and CLR13 immediately after the start signal ST1. Thereby, scanning of the divided areas DI_(1,2) and DI_(1,3) is stopped. The control circuit 15 enables the clear signal CLR11 at the end of the first frame. In this way, the scanning operation of the divided area DI_(1,1) is performed, and the data of the divided area DI_(1,1) is rewritten. In addition, the divided areas DI_(1,2) and DI_(1,3) will remain displayed.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR22 and CLR23 immediately after the start signal ST2. Thereby, scanning of the divided areas DI_(2,2) and DI_(2,3) is stopped. The control circuit 15 enables the clear signal CLR21 at the end of the second frame. In this way, the scanning operation of the divided area DI_(2,1) is performed, and the data of the divided area DI_(2,1) is rewritten. In addition, the divided areas DI_(2,2) and DI_(2,3) will remain displayed.

Subsequently, similarly, the start signal STm is enabled, and any divided area DI included in the m column performs a scanning operation. In addition, the clear signal CLR corresponding to the remaining divided areas DI included in the m column is set to enable, and the scanning of the remaining divided areas DI is stopped.

Thereby, the first to ninth frames are sequentially driven, and the data in the divided areas DI_(1,1) to DI_(3,3) are rewritten.

In addition, FIG. 18 and FIG. 19 illustrate an example in which the data of all the divided areas DI is rewritten. It is also possible to display an image in the display area 4 by controlling the start signal ST and the clear signal CLR to skip scanning of any divided area DI.

[1-5-3] Operation of shift register SR Next, the operation of the shift register SR will be described. FIG. 20 is a timing diagram illustrating the operation of the shift register SR. As shown in FIG. 7 , frame signals Frame_o and Frame_e are input to the shift register SR.

The frame signals Frame_o and Frame_e adopt a minimum unit of 1 frame, and are set to enable (high level) alternately for each arbitrary frame. The two inverter circuits 21o and 21e operate alternately in response to the frame signals Frame_o and Frame_e. The control circuit 15 switches the states of the frame signals Frame_o and Frame_e while the signal Vsync is at a low level.

For example, assume that the frame signal Frame_o is set to enabled (high level). The frame signal Frame_e is low level. When the frame signal Frame_o becomes a high level, the transistor M1o of the inverter circuit 21o is turned on, and the inverter circuit 21o is set to be enabled. The transistor M1e of the inverter circuit 21e is turned off, and the inverter circuit 21e is disabled.

After the frame signal Frame_o becomes a high level, the enable signal ST is set to a high level. As a result, the input signal VIN of the core circuit RG1 of the first stage becomes a high level. As a result, the transistor M2 of the input unit 20 is turned on, and the node An becomes a high level.

When the node An becomes a high level, the transistor M7o of the inverter circuit 21o is turned on, and the node Bno becomes a low level. That is, the inverter circuit 21o holds the inversion data of the node An at the node Bno. Thereby, the transistor M4o of the pull-down part 23 is turned off, and the pull-down operation of the node Qn is stopped.

In addition, when the node An reaches a high level, the transistor M3 of the output part 22 is turned on. Then, the clock signal ClkA becomes high level. In this way, the scan line GL1 becomes a high level.

The core circuit RG2 of the second stage receives the output signal as the input signal VIN from the core circuit RG1 of the previous stage. Then, the clock signal ClkB becomes high level. In this way, the core circuit RG2 sets the scan line GL2 to a high level.

The core circuit RG1 of the first stage receives the output signal of the core circuit RG2 of the second stage as the reset signal RST. The reset signal RST is input to the gate of the transistor M5 of the input part 20 . As a result, transistor M5 is turned on, and node An becomes a low level.

When the node An becomes a low level, the transistor M7o of the inverter circuit 21o is turned off, and the node Bno becomes a high level. That is, the inverter circuit 21o holds the inversion data of the node An at the node Bno. When the node Bno becomes a high level, the transistor M6o is turned on, and the node An remains at a low level. Thereby, the transistor M4o of the pull-down part 23 is turned on, and the node Qn becomes a low level.

In addition, when the node An becomes a low level, the transistor M3 of the output part 22 is turned off. Thereby, the scanning line GL1 becomes a low level.

In addition, in terms of detailed design, it is designed to avoid simultaneous operation of adjacent core circuits RG. Therefore, a gap is provided between the edges of each other so that the pulse wave of the clock signal ClkA and the pulse wave of the clock signal ClkB do not overlap.

Subsequently, similarly, the core circuits RG3 to RGi output pulse signals sequentially.

After the last core circuit RGi outputs the pulse signal, the clear signal CLR is set to a high level. When the clear signal CLR reaches a high level, the transistors M8 and M9 of the clear part 24 are turned on. As a result, node Qn and node An become low level. Thereby, the core circuit RGi sets the scanning line GLi to a low level.

Then, the frame signal Frame_e is set to a high level, and the frame signal Frame_o is set to a low level. In this way, the inverter circuit 21e of the core circuit RG is enabled. Then, the scanning operation by the shift register SR is repeated.

Through the above-mentioned operation, the transistor that continuously applies the forward bias voltage (bias) can be removed in the core circuit RG. Thereby, it is possible to suppress deterioration in the characteristics of the transistors constituting the core circuit RG. Specifically, in the case of using a TFT for a transistor, when a forward bias voltage is continuously applied, the threshold voltage Vth shifts. However, in this embodiment, it is possible to suppress deterioration in the characteristics of the TFT.

[1-5-4] Operation of core circuit RG Next, the operation of the core circuit RG included in the shift register SR will be described. The selection period is a period during which the scanning line is selected and the scanning line outputs a pulse signal. The non-selection period is a period other than the selection period, and the scanning line does not output a pulse signal.

FIG. 21 is a schematic diagram illustrating the operation of the inverter of the core circuit RG during the selection period. For example, assume that the frame signal Frame_o is set to enable (high level ("Hi" in FIG. 21)), and the inverter circuit 21o performs an inverter operation. The frame signal Frame_e is at a low level ("Lo" in Figure 21).

The gate of the transistor M2 receives a high-level ("ON" in Figure 21) input signal VIN from the core circuit RG in the previous stage. Thereby, the transistor M2 is turned on, and the node An becomes a high level ("Hi" in Figure 21).

A high-level frame signal Frame_o is input to the gate of the transistor M1o. Therefore, the transistor M1o is turned on, and the inverter circuit 21o is set to be enabled.

Since the node An is at a high level, the transistor M7o is turned on and the node Bno is pulled down. The arrows in Figure 21 indicate current flow.

In addition, the inverter operation during the selection period can also cause the transistor M7e of the inverter circuit 21e to operate. That is, since the node An is at a high level, the transistors M1b and M7e are turned on. Therefore, the node Bno is also pulled down by the path of the transistor M1b, the node Bne, and the transistor M7e. Thereby, the node Bno can be reliably set to a low level.

The drive capability of transistor M6o is set to be greater than the drive capability of transistor M7o. During the non-selection period, the node An can be reliably set to a low level by pulling down the node An through the transistor M6o.

Regarding the conditions for realizing the above-mentioned inverter operation, the transistors M6 and M7 are set so as to satisfy the following conditions. Among them, transistor M6 refers to each of transistors M6o and M6e, and transistor M7 refers to each of transistors M7o and M7e. Mark the channel widths of transistors M6 and M7 as W6 and W7 respectively. The channel width is also called the gate width.

W7≦W6≦2×W7

By setting "W6≦2×W7", the combined driving capability of the transistors M7o and M7e is greater than the driving capability of the transistor M6o (or the transistor M6e). Thereby, node Bno can be reliably set to a low level during the selection period.

By setting "W7≦W6", the driving ability of the transistor M6 becomes greater than the driving ability of the transistor M7. Thereby, the node An can be reliably set to a low level during the non-selection period.

Move your attention to the inverter circuit included in the core circuit RG near the last section. Among the inverter circuits 21o and 21e, the potential of the node Bne of the inverter circuit set to be disabled (for example, the inverter circuit 21e) is continuously reduced due to the leakage current of the transistor M1e. Therefore, during the selection period of the core circuit RG near the final stage, the transistor M1b is turned on, thereby connecting the node Bno and the node Bne on the enabled side, thereby forming a system that can be set to a low level more robustly. accurate architecture.

[1-6] Effects of the first embodiment In the first embodiment, the display area 4 is divided into a plurality of divided areas DI arranged in a matrix. The sub-array SA and the gate driver GD are arranged in each of the plurality of divided areas DI. Thereby, a liquid crystal display device 1 capable of narrowing the frame can be realized. In addition, the display area 4 can be divided and driven for each divided area DI. In addition, scanning can be performed freely for each divided area DI.

In addition, by scanning for each divided area DI, the frame frequency can be reduced compared to the case where the entire screen is scanned as one frame. Thereby, the power consumption caused by charging and discharging based on the clock signal is reduced. In addition, the writing time for writing data (driving voltage) into the pixel can be extended, so that the current for driving the TFT included in the pixel can be reduced, and the size of the TFT can also be reduced. As a result, since the current supplied to the scanning line GL and the signal line SL can also be reduced, power consumption can be reduced.

In addition, the clock signals ClkA and ClkB can be driven in a time-divided manner for each divided area DI. This makes it possible to reduce power consumption compared to the case where the clock signal is supplied to the entire screen.

In addition, each core circuit RG is provided with two inverter circuits 21o and 21e, and the inverter circuits 21o and 21e are alternately enabled in response to the frame signals Frame_o and Frame_e. Therefore, it is possible to prevent the voltage from being continuously applied to the transistor (for example, TFT) constituting the shift register SR. Thereby, a gate driver GD with high withstand voltage can be realized.

[2] Second embodiment The second embodiment is another example regarding the wiring of the display area 4 . The second embodiment is configured to wire different clock signals for each row of a plurality of divided areas DI.

[2-1] Wiring of multiple divided areas DI FIG. 22 is a diagram illustrating the wiring of a plurality of divided areas DI in the second embodiment. Hereinafter, description will be given as an example of a case where the display area 4 is composed of 9 (=3×3) divided areas DI_(1,1) to DI_(3,3).

The wiring to the plurality of divided areas DI is performed as follows. ． The gate driver GD is configured for each divided area DI. ． The power supply wiring system only wires the Vgl line. ． The Frame_e line and the Frame_o line are wired as common signals for the entire screen. ． CLR lines are routed for each divided area DI. ． The ST lines are wired for each divided area DI in the scanning line direction (X direction). ． The ClkA line and the ClkB line are wired for each divided area DI in the signal line direction (Y direction).

The start signal ST is composed of three start signals ST1 to ST3. The start signals ST1 to ST3 are supplied respectively using three lines ST1 to ST3.

The clock signal ClkA is composed of three clock signals ClkA1 to ClkA3. The clock signals ClkA1 to ClkA3 are supplied respectively using three ClkA1 lines to ClkA3 lines.

The clock signal ClkB is composed of three clock signals ClkB1 to ClkB3. The clock signals ClkB1 to ClkB3 are supplied respectively using three ClkB1 lines to ClkB3 lines.

The clear signal CLR is composed of nine clear signals CLR11 to CLR33. The clear signals CLR11 to CLR33 are supplied using 9 CLR11 lines to CLR33 lines.

The start signal ST1 is input to the divided areas DI_(1,1), DI_(1,2), and DI_(1,3) of the first column. The start signal ST2 is input to the divided areas DI_(2,1), DI_(2,2), and DI_(2,3) of the second column. The start signal ST3 is input to the divided areas DI_(3,1), DI_(3,2), and DI_(3,3) of the third column. The nine divided areas DI_(1,1) to DI_(3,3) can be started in column units.

The clock signals ClkA1 and ClkB1 are input to the divided areas DI_(1,1), DI_(2,1) and DI_(3,1) of the first row. The clock signals ClkA2 and ClkB2 are input to the divided areas DI_(1,2), DI_(2,2) and DI_(3,2) of the second row. The clock signals ClkA3 and ClkB3 are input to the divided areas DI_(1,3), DI_(2,3) and DI_(3,3) of the third row. The nine divided areas DI_(1,1) to DI_(3,3) can perform clock control in row units.

The nine clear signals CLR11 to CLR33 are respectively input to the nine divided areas DI_(1,1) to DI_(3,3). The nine divided areas DI_(1,1) to DI_(3,3) can each use nine clear signals CLR11 to CLR33 to stop scanning and prevent data from being rewritten (maintaining display).

The frame signal Frame_e is input to all divided areas DI. The frame signal Frame_o is input to all divided areas DI. The Vgl line is routed to all divided areas DI.

[2-2] Scanning operation of display area 4 Next, the scanning operation of one divided area DI will be described. FIG. 23 is a timing chart explaining the scanning operation of the divided area DI.

The control circuit 15 receives the signal Vsync from the outside. Clock signals ClkAm, ClkBm, start signal STm, and clear signal CLRmn are input to any divided area DI_(m,n). The scanning operation of the divided area DI is the same as that in FIG. 16 of the first embodiment.

Next, the scan stop operation of one divided area DI will be described. FIG. 24 is a timing chart explaining the scanning stop operation of the divided area DI. FIG. 24 shows the operation of a divided area in which data is not rewritten among the divided areas in the same column to which the start signal STm is input.

The control circuit 15 responds to the low level of the signal Vsync and inputs the start signal STm to the divided area DI_(m,n). Next, the control circuit 15 inputs the clear signal CLRmn to the divided area DI_(m,n) immediately after the start signal STm. Thereby, the start signal STm can be substantially disabled. Then, no pulse wave is input to the scanning line GL. At this time, the divided area DI_(m,n) is not scanned and remains displayed.

The divided areas DI adjacent in the column direction operate with different clock signals ClkA (and different clock signals ClkB). As shown in FIG. 24 , among the divided areas adjacent in the column direction, a clock signal is not input to a divided area in which data is not rewritten.

The liquid crystal display device 1 of the second embodiment can similarly execute the drive mode described in the first embodiment. The effects of the second embodiment are also the same as those of the first embodiment.

[3] Third embodiment The third embodiment is configured such that a part of the plurality of divided areas formed by dividing the display area 4 is configured as a non-display area in which an image is not displayed.

FIG. 25 is a schematic diagram of the display area 4 of the third embodiment. FIG. 25 shows a case where the display area 4 includes nine divided areas as an example.

The display area 4 has one or a plurality of non-display areas ND. In FIG. 25 , a case where the display area 4 includes three non-display areas ND is shown as an example. In the non-display area ND, no pixels or gate drivers are provided.

The display area 4 system has 6 divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) . The sub-array SA and the gate driver GD are arranged in the divided area DI.

FIG. 26 is a schematic diagram illustrating drive mode 1 of the liquid crystal display device 1. In FIG. 26 , for example, wiring having the display area 4 of the first embodiment is provided. There are no wiring signal lines in the ND system in the non-display area.

In the first frame, the control circuit 15 sets the start signal ST1 to enable (high level). The control circuit 15 sets the clear signals CLR12 and CLR13 to enable (high level) at the end of the first frame. Thereby, the scanning operation of the divided areas DI_(1,2) and DI_(1,3) of the first column is executed.

The control circuit 15 enables the start signal ST2 in the second frame following the first frame. The control circuit 15 enables the clear signals CLR21 and CLR23 at the end of the second frame. Thereby, the scanning operation of the divided areas DI_(2,1) and DI_(2,3) of the second column is executed.

The control circuit 15 enables the start signal ST3 in the third frame following the second frame. The control circuit 15 enables the clear signals CLR31 and CLR32 at the end of the third frame. Thereby, the scanning operation of the divided areas DI_(3,1) and DI_(3,2) of the third column is executed.

FIG. 27 is a schematic diagram illustrating drive mode 2 of the liquid crystal display device 1. In FIG. 27 , for example, wiring having the display area 4 of the second embodiment is provided. There are no wiring signal lines in the ND system in the non-display area.

The control circuit 15 is in the first frame and enables the start signal ST2. The control circuit 15 sets the clear signal CLR23 to enable immediately after the start signal ST2. Thereby, scanning of the divided area DI_(2,3) is stopped. The control circuit 15 enables the clear signal CLR21 at the end of the first frame. In this way, the scanning operation of the divided area DI_(2,1) is performed, and the data of the divided area DI_(2,1) is rewritten. In addition, the divided area DI_(2,3) will remain displayed.

The control circuit 15 enables the start signal ST3 in the second frame following the first frame. The control circuit 15 enables the clear signal CLR32 immediately after the start signal ST3. Thereby, scanning of the divided area DI_(3,2) is stopped. The control circuit 15 enables the clear signal CLR31 at the end of the second frame. In this way, the scanning operation of the divided area DI_(3,1) is performed, and the data of the divided area DI_(3,1) is rewritten. In addition, the divided area DI_(3,2) will remain displayed.

Subsequently, similarly, the start signal STm is enabled, and any divided area DI included in the m column performs a scanning operation. In addition, the clear signal CLR corresponding to the remaining divided areas DI included in the m column is enabled, and the scanning of the remaining divided areas DI is stopped.

In this way, the six divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3) are sequentially driven ), rewrite the data of the divided areas DI_(2,1), DI_(3,1), DI_(1,2), DI_(3,2), DI_(1,3), DI_(2,3).

The non-display area ND is, for example, always black. In addition, a color filter of a desired color can also be disposed in the non-display area ND, thereby causing the non-display area ND to display in a color other than black.

In the third embodiment, the gate driver GD is arranged for each divided area DI. Therefore, even when the non-display area ND is provided between the divided areas DI in the row direction, the gate driver GD can still be used to scan all the divided areas DI.

Furthermore, in the third embodiment, a non-tetragonal special-shaped display can be realized. In addition, odd-shaped displays can be driven optimally.

In addition, in each of the above-described embodiments, description is given for the case where all transistors are composed of N-type transistors. However, it is not limited to this. By inverting the polarity of the power supply voltage and the pulse signal, all the transistors can also be composed of P-type transistors.

In addition, the shift register SR included in the gate driver GD is not limited to the structure described in each of the above embodiments. Other types of shift registers that can sequentially output pulse waves to a plurality of scan lines GL can also be used.

In addition, in each of the above embodiments, the display device is explained taking a liquid crystal display device as an example. However, the present invention is not limited to this, and can also be applied to other display devices such as organic EL display devices.

The present invention is not limited to the above-described embodiments, and various modifications can be made during the implementation stage within the scope that does not deviate from the gist of the present invention. In addition, each embodiment may be appropriately combined and implemented, and in this case, the combined effect can be obtained. In addition, the above-mentioned embodiment includes various inventions, and various inventions can be extracted by selecting and combining the plurality of disclosed constituent elements. For example, even if some components are deleted from all the components shown in the embodiments, as long as the problem can be solved and the effects can be obtained, the configuration with the deleted components can be extracted as an invention.

1: Liquid crystal display device 2:TFT substrate 3:Integrated circuit 4:Display area 10: Pixel array 11: Gate driver group 12: Source driver 13: Common electrode driver 14: Voltage generation circuit 15:Control circuit 16:Switching element 20:Input part 21:Register Department 21e,21o:Inverter circuit 22:Output department 23: Drop-down part 24: Clearance Department SR: shift register RG: core circuit

FIG. 1 is a schematic layout diagram of a liquid crystal display device according to the first embodiment of the present invention. FIG. 2 is a block diagram of a liquid crystal display device. Figure 3 is a schematic diagram of the display area. FIG. 4 is a schematic diagram of the pixel array shown in FIG. 2 . FIG. 5 is a schematic diagram of the gate driver group shown in FIG. 2 . FIG. 6 is a circuit diagram of the subarray shown in FIG. 4 . Figure 7 is a block diagram of the shift register included in the gate driver. FIG. 8 is a circuit diagram of the core circuit shown in FIG. 7 . FIG. 9 is a schematic diagram illustrating the configuration area of the gate driver. Figure 10 is a layout diagram of the register section. Figure 11 is a layout diagram of the output section and the clearing section. Fig. 12 is a layout diagram of the input unit. Figure 13 is a layout diagram of the pull down portion. FIG. 14 is a diagram illustrating the wiring of a plurality of divided areas. FIG. 15 is a schematic diagram illustrating an embodiment of a display area. FIG. 16 is a timing diagram illustrating the scanning operation of divided areas. FIG. 17 is a timing chart illustrating the scanning stop operation of divided areas. FIG. 18 is a schematic diagram illustrating the driving mode (pattern 1) of the liquid crystal display device. FIG. 19 is a schematic diagram illustrating drive mode 2 of the liquid crystal display device. Figure 20 is a timing diagram illustrating the operation of the shift register. FIG. 21 is a schematic diagram illustrating the operation of the inverter of the core circuit during the selection period. FIG. 22 is a diagram illustrating the wiring of a plurality of divided areas in the second embodiment. FIG. 23 is a timing chart illustrating the scanning operation of divided areas. FIG. 24 is a timing chart illustrating the scanning stop operation of divided areas. FIG. 25 is a schematic diagram of the display area of the third embodiment. FIG. 26 is a schematic diagram illustrating drive mode 1 of the liquid crystal display device. FIG. 27 is a schematic diagram illustrating drive mode 2 of the liquid crystal display device.

1: Liquid crystal display device

10: Pixel array

11: Gate driver group

12: Source driver

13: Common electrode driver

14: Voltage generation circuit

15:Control circuit

CNT: control signal

DT: image data

Claims (12)

A display device comprising: a display area having a plurality of divided areas arranged in rows and columns; a pixel array having a plurality of sub-arrays respectively arranged in the plurality of divided areas, each of the plurality of sub-arrays having a plurality of pixels; A plurality of scan lines are individually provided in each of the plurality of sub-arrays and extend along the first direction; a plurality of signal lines are configured in a manner that is jointly connected to the sub-array groups of each row and are provided in the aforementioned pixel array, along with the aforementioned The first direction intersects and extends in a second direction; a plurality of gate drivers are respectively arranged in the plurality of divided areas, each of which is connected to the plurality of scan lines; a source driver is connected to the plurality of signal lines; and control The circuit controls the plurality of gate drivers and the aforementioned source driver, and can individually drive the plurality of sub-arrays. A display device includes: a display area including a plurality of divided areas arranged in rows and columns; a non-display area provided in at least one divided area among the plurality of divided areas and in which no pixels are arranged; and a pixel array having a plurality of divided areas arranged respectively. In the plurality of sub-arrays in the remaining divided areas, each of the aforementioned plurality of sub-arrays has a plurality of pixels; a plurality of scan lines are individually provided in each of the aforementioned plurality of sub-arrays and extend along the first direction; A plurality of signal lines are configured to be commonly connected to the sub-array groups of each row and are provided in the aforementioned pixel array, extending in a second direction that intersects the aforementioned first direction; a plurality of gate drivers are respectively arranged in the remaining divisions. regions, each of which is connected to the plurality of scan lines; a source driver, connected to the plurality of signal lines; and a control circuit, which controls the plurality of gate drivers and the aforementioned source driver to individually drive the plurality of sub-arrays. The display device of claim 1 or 2, wherein the control circuit sequentially drives the sub-array groups arranged along the row direction. The display device of claim 1 or 2, wherein the control circuit simultaneously drives the sub-array groups arranged along the column direction. The display device of Claim 1 or 2, wherein the start signal used to start scanning is input to the gate driver groups of each column together. For example, the display device of claim 1 or 2, wherein the clock signal is input to the gate driver group of each column together. For example, the display device of claim 1 or 2, wherein the clock signal is input to the gate driver group of each row together. The display device of claim 5, wherein the clear signal used to stop scanning is input to each of the plurality of gate drivers. The display device of claim 8, wherein the control circuit inputs the clear signal immediately after the start signal is input to the first gate driver to stop rewriting the data of the sub-array connected to the first gate driver. . The display device of claim 1 or 2, wherein each of the plurality of gate drivers includes a shift register having a plurality of core circuits connected in series; each of the aforementioned plurality of core circuits includes: an input The input signal corresponding to the output signal of the core circuit in the previous section is transferred to the first node; the first inverter circuit is enabled by the first frame signal and maintains the aforementioned first inverter circuit at the second node. the inversion signal of the node; and the second inverter circuit is enabled by the second frame signal that is complementary to the first frame signal, and maintains the inversion signal of the first node at the third node . The display device of claim 10, wherein the core circuit includes an output part; the output part includes an output transistor and a capacitor; the output transistor has: a gate connected to the first node, and a gate for receiving a clock signal. a first terminal and a second terminal connected to the scanning line; the capacitor has a first electrode connected to the first node and a second electrode connected to the scanning line. Such as the display device of claim 11, wherein the odd-numbered core circuits receive a first clock signal; the even-numbered core circuits receive a second clock signal that is complementary to the first clock signal.