KR102416886B1 - Gate driving circuit and Flat panel display device using the same - Google Patents

Abstract

The n-th stage of the gate driving circuit of the present invention includes: a first node control unit for controlling the first node by a carry pulse output from the previous stage and a carry pulse output from the subsequent stage; a second node controller for controlling a second node according to the voltage of the first node; an inverter unit for inverting the voltage of the second node and applying it to a third node; a scan pulse output unit receiving one of a plurality of scan pulse output clock signals and outputting a scan pulse according to voltages of the first node and the third node; In addition, a carry pulse output unit for receiving one of a plurality of clock signals for outputting carry pulses and outputting carry pulses according to voltages of the first and third nodes is provided.

Description

Gate driving circuit and flat panel display device using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a gate driving circuit for improving a breakdown voltage and a flat panel display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display (LCD) using liquid crystal and an organic light emitting diode (Organic Light Emitting Diode; hereinafter) Various display devices such as an OLED display using OLED) are being used.

Such display devices include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

The driving circuit includes a gate driving circuit driving the plurality of gate lines, a data driving circuit driving the plurality of data lines, and timing for supplying image data and various control signals to the gate driving circuit and the data driving circuit. controller, etc.

Among the display devices, the display panel of the liquid crystal display includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed on the glass substrate, and the thin film transistor A liquid crystal layer filled between the array substrate and the color filter array substrate is provided.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line and one sub-pixel area Pixel (P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel region P.

In the display panel of the liquid crystal display, a voltage is applied to an electric field generating electrode (a pixel electrode and a common electrode) to generate an electric field in the liquid crystal layer, and the arrangement state of liquid crystal molecules of the liquid crystal layer is adjusted by the electric field to control incident light. Display an image by controlling the polarization.

In addition, in the display panel of the OLED display among the display devices, the plurality of gate lines and the plurality of data lines intersect to define sub-pixels, and each sub-pixel includes an anode and a cathode and the anode and the cathode An OLED composed of an organic light emitting layer therebetween, and a pixel circuit independently driving the OLED are provided.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

The display panel for the display device is defined as an active area (AA) providing an image to a user and a non-active area (NA) surrounding the display area (AA).

In addition, a gate driving circuit and a data driving circuit are provided outside the non-display area or the display panel to provide a scan pulse and a data signal for driving each pixel of the plurality of gate lines and the plurality of data lines of the display panel. provided

The gate driving circuit may include at least one gate driver IC, but the display panel is not displayed in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel. may be formed simultaneously on the region. As a result, the gate driving circuit is included in the display panel. This is called a Gate-In-Panel (hereinafter also referred to as “GIP”).

The gate driving circuit as described above includes a plurality of stages greater than the number of gate lines in order to sequentially supply scan pulses to each gate line, and uses oxide semiconductor thin film transistors to improve driving characteristics.

1 is a block diagram of an n-th stage ST(n) of a conventional gate driving circuit, FIG. 2 is a circuit diagram of the inverter unit 13 of FIG. 1, and FIG. 3 is a conventional n-th stage (ST(n)). It is a waveform diagram of ST(n)).

As shown in FIG. 1, the n-th stage ST(n) of the conventional gate driving circuit includes a carry pulse CR(n-3) output from the previous stage and a carry pulse CR output from the subsequent stage. (n+3)), the Q node control unit 12 for controlling the first node Q, and the inverter unit 13 for inverting the voltage of the first node Q and applying it to the second node Qb ) and one of the plurality of scan pulse output clock signals SCCLK(n) are received and the scan pulse SC(n) is obtained according to the voltages of the first node Q and the second node Qb. The scan pulse output unit 15 that outputs A carry pulse output unit 16 for outputting a carry pulse CR(n) according to the ripple of the first node Q, the scan pulse output unit 15 and the carry pulse output unit 16 It is constituted by including a stabilization unit 14 for preventing occurrence and the like, and a first node reset unit 11 for resetting the first node Q by a start signal VST.

A detailed circuit configuration of the inverter unit 13 is shown in FIG. 2 .

The inverter unit 13 uses an oxide semiconductor thin film transistor (Oxide TFT)-based two-stage inverter (four TFTs) composed of an N-type TFT in a GIP circuit.

That is, the inverter unit 13 includes a first transistor ( ) in which a source electrode is connected to a first constant voltage terminal (GVDD), a gate electrode is connected to a common node (N), and a drain electrode is connected to the second node (Qb). T1), a second transistor T2 having a gate electrode and a source electrode commonly connected to the first constant voltage terminal GVDD and a drain electrode connected to the common node N, and the first node Q a third transistor T3 connected to a gate electrode, a source electrode connected to the common node N, and a drain electrode connected to a second constant voltage terminal GVSS2, and a gate electrode connected to the first node Q and a fourth transistor T4 connected to the second node Qb, a source electrode connected to the second node Qb, and a drain electrode connected to the second constant voltage terminal GVSS2.

Here, the first to fourth transistors T1 , T2 , T3 , and T4 are all N-type transistors and oxide TFTs.

In the inverter unit 13 configured as described above, when a high voltage is applied to the first node Q, the third and fourth transistors T3 and T4 are turned on, and the second transistor T2 and A current flows from the first constant voltage terminal GVDD to the second constant voltage terminal GVSS2 through a third transistor T3, and a second voltage from the second constant voltage terminal GVSS2 to the second node Qb A constant voltage GVSS2 is applied.

Accordingly, the inverter unit 13 inverts the second node Qb to the low logic state when the first node Q is in the high logic state.

The operation of the n-th stage ST(n) of the conventional gate driving circuit configured as described above is as follows.

That is, as shown in FIG. 3 , the first node Q is in a high state by the carry pulse CR(n-3) output from the (n-3)-th previous stage, and the first node ( When Q) is in a high state, the third and fourth transistors T3 and T4 of the inverter unit 13 are turned on to invert the second node Qb to a low state.

At this time, a clock signal SCCLK(n) for outputting a scan pulse and a clock signal CRCLK(n) for outputting a carry pulse are applied to the scan pulse output unit 15 and the carry pulse output unit 16 . Also, although not shown in the drawing, since a bootstrapping capacitor is built in the scan pulse output unit 15, when the scan pulse output clock signal SCCLK(n) is applied high, the first node (Q) is bootstrapped (or coupled) to have a higher potential.

In the state in which the first node Q is bootstrapped in this way, the scan pulse output unit 15 and the carry pulse output unit 16 receive the input clock signal SCCLK(n) for outputting the scan pulse and the carry pulse. The output clock signal CRCLK(n) is output as a scan pulse SC(n) and a carry pulse CR(n), respectively.

In addition, the first node Q is in a low state by the carry pulse CR(n+3) output from the (n+3)-th post stage, and the third and third of the inverter unit 13 are 4 transistors T3 and T4 are turned off to invert the second node Qb to a high state.

In the above, when the inverter unit 13 inverts the second node Qb to the low state, the third and fourth transistors T3 and T4 are subjected to bootstrapping ( Alternatively, a coupled (Coupling) high voltage is applied.

And, when the display panel has a large area and high resolution, under-driving is required for the gate driving circuit formed of the oxide semiconductor TFT due to a short data storage (write) period and an increase in the load of lines.

That is, in the general gate driving circuit, 24V is used as the first constant voltage GVDD and -6V is used as the second constant voltage GVSS2 to swing from 24V to -6V, but in the under-driving, the second constant voltage GVSS2 is used. ), -12V is used.

Therefore, since the swing width of the clock pulse increases to 24V to -12V for the under driving, the bootstrapfill (or coupling) level of the first node Q increases, and eventually the inverter unit ( 13), since a higher voltage is applied to the third and fourth transistors T3 and T4 during under-driving, there is a risk of black-down.

SUMMARY OF THE INVENTION The present invention is to solve the problems of the related art, and an object of the present invention is to provide a gate driving circuit capable of improving a breakdown voltage and a flat panel display using the same.

The n-th stage of the gate driving circuit according to the present invention for achieving the above object includes a first node control unit for controlling the first node by a carry pulse output from a previous stage and a carry pulse output from a subsequent stage; A second node control unit for controlling a second node according to the voltage of the first node, an inverter unit for inverting the voltage of the second node to apply to the third node, and receiving one of a plurality of clock signals for outputting scan pulses a scan pulse output unit for outputting a scan pulse according to voltages of the first node and the third node; It is characterized by having a carry pulse output unit that outputs .

Here, the second node controller may include a transistor that is turned on/off according to the voltage of the first node and supplies a first constant voltage to the second node.

The gate driving circuit includes a storage unit for selectively storing a carry pulse output from the previous stage according to a line selection signal LSP, and a first node Q according to a real-time compensation signal VRT for a blank section of the corresponding stage. ) and charging the first node (Q) according to the start signal (VST) signal characterized in that it further comprises a blank section first node control unit.

The gate driving circuit includes a storage unit for selectively storing a carry pulse output from the previous stage according to a line selection signal LSP, and a first node Q according to a real-time compensation signal VRT for a blank section of the corresponding stage. ) and a blank section first node controller for charging the second node and discharging the first node (Q) according to a start signal (VST) signal.

The blank section first node controller includes a first transistor that is turned on/off according to the real-time compensation signal VRT to charge the first node Q to a first constant voltage, and the real-time compensation signal and a second transistor that is turned on/off according to (VRT) to charge the second node Qh with a first constant voltage.

In addition, a flat panel display device according to the present invention for achieving the above object includes a plurality of sub-pixels in a matrix form in which a plurality of gates and data lines are disposed, in response to a scan pulse supplied to each gate line. a display panel for displaying an image by applying a data voltage to the plurality of data lines; a gate driving circuit for sequentially supplying scan pulses to each of the gate lines; and a data voltage for supplying the data voltage to the plurality of data lines. a data driving circuit that aligns image data input from the outside to suit the size and resolution of the display panel, supplies it to the data driver, and supplies synchronization signals input from the outside to a plurality of gate control signals and a plurality of data control signals and a timing controller for supplying them to the gate driver and the data driver, respectively, and the nth stage of the gate driving circuit controls the first node by a carry pulse output from a previous stage and a carry pulse output from a subsequent stage a first node control unit, a second node control unit for controlling a second node according to the voltage of the first node, an inverter unit for inverting the voltage of the second node and applying it to a third node, a plurality of scan pulses a scan pulse output unit for receiving one of the output clock signals and outputting a scan pulse according to voltages of the first and third nodes; It is characterized in that it has a carry pulse output unit that outputs a carry pulse according to the voltage of the node.

The gate driving circuit and the flat panel display using the same according to an embodiment of the present invention having the above characteristics have the following effects.

First, the first node's boot? Since no voltage is applied to the inverter, the black-down voltage can be improved.

Second, there is a possibility that the first node is discharged during the real-time compensation driving of the blank section, but the possibility of the first node being discharged by the real-time compensation signal is prevented, so that the black-down voltage can be improved more safely.

1 is a block diagram of an n-th stage ST(n) of a conventional gate driving circuit;
2 is a circuit configuration diagram of the inverter unit 13 of FIG. 1 .
3 is a waveform diagram of a conventional n-th stage ST(n).
4 is a block diagram schematically illustrating a flat panel display device according to the present invention;
5 is a block diagram of the (n)th stage ST(n) configuration of the gate driving circuit according to the first embodiment of the present invention.
6 is a waveform diagram of the (n)th stage ST(n) according to the first embodiment of the present invention.
7 is a block diagram of the (n)-th stage (ST(n)) configuration of the gate driving circuit according to the second embodiment of the present invention;
8 is a waveform diagram of the (n)th stage ST(n) according to the second embodiment of the present invention.
9 is a real-time compensation driving waveform diagram of the (n)-th stage ST(n) according to the first and second embodiments of the present invention;

A gate driving circuit and a flat panel display using the same according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

4 is a schematic block diagram of a flat panel display device according to the present invention, and FIG. 5 is a block diagram of the (n)-th stage ST(n) of the gate driving circuit according to the first embodiment of the present invention.

As shown in FIG. 4 , the flat panel display according to the present invention includes a display panel 10 , a gate driving circuit 20 , a data driving circuit 30 , and a timing controller 40 .

The display panel 10 includes a plurality of gate lines GL1 to CLn arranged in a first direction at regular intervals on a substrate, and a direction perpendicular to the plurality of gate lines GL at regular intervals. A plurality of data lines DL1 to DLm arranged in the second direction, and a plurality of sub-pixels arranged at intersections of the plurality of gate lines GL1 to CLn and the plurality of data lines DL1 to DLm It is configured by providing the (P). The plurality of sub-pixels P are configured according to an image signal (data voltage) supplied from the plurality of data lines DL1 to DLm in response to a scan pulse supplied from each of the gate lines GL1 to CLn. Display the image.

When the display panel 10 is a liquid crystal display panel, each sub-pixel P is supplied from the corresponding data lines DL1 to DLm in response to a scan pulse supplied from the corresponding gate lines GL1 to CLn. A thin film transistor for providing an image signal (data voltage) to each pixel electrode and a capacitor for storing an image signal (data voltage) supplied from the data lines DL1 to DLm for one frame are provided.

In addition, when the display panel 10 is an OLED display panel, each sub-pixel P includes an organic light emitting diode (OLED), a driving transistor, a capacitor, and at least one switching transistor.

That is, at least one switching transistor stores a data voltage supplied from the corresponding data lines DL1 to DLm in response to a scan pulse supplied from the corresponding gate lines GL1 to CLn in the capacitor, and the driving transistor is A current flowing through the organic light emitting diode is controlled according to the data voltage stored in the capacitor so that the organic light emitting diode emits light.

The gate driving circuit 20 sequentially supplies a scan pulse (a gate driving signal) to each of the gate lines GL1 to CLn according to a plurality of gate control signals GCS provided from the timing controller 40 . It consists of shift registers.

The gate driving circuit 20 includes a plurality of stages to sequentially supply a scan signal (gate driving signal, Vgout) to each of the plurality of gate lines GL1 to CLn.

When the gate driving circuit 20 is a gate in panel (GIP) type gate driving circuit, the gate driving circuit 20 is disposed in a non-display area of the display panel 10 .

The gate driving circuit 20 includes a plurality of stages, and the plurality of stages correspond one-to-one with the plurality of gate lines, so that one stage supplies a scan signal to one gate line. Of course, the gate driving circuit 20 may include a dummy stage to which a scan signal is not actually supplied to the gate line.

The data driving circuit 30 converts digital image data RGB input from the timing controller 40 into an analog data voltage using a reference gamma voltage, and converts the converted analog data voltage to the plurality of data lines DL1 . ~DLm). The data driving circuit 30 is controlled according to a plurality of data control signals DCS provided from the timing controller 40 .

The timing controller 40 aligns image data RGB input from the outside to suit the size and resolution of the display panel 10 , and supplies it to the data driving circuit 30 . In addition, the timing controller 40 receives externally input synchronization signals SYNC, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. is used to generate a plurality of gate control signals GCS and a plurality of data control signals DCS and respectively supply them to the gate driving circuit 20 and the data driving circuit 30 .

5 is a block diagram of the (n)-th stage ST(n) of the gate driving circuit according to the first embodiment of the present invention.

As shown in FIG. 5, the (n)-th stage ST(n) of the gate driving circuit according to the first embodiment of the present invention includes transistors Ta, Tb, Tc and a capacitor C1, a storage unit 21 configured to selectively store a set signal SET according to a line select pulse (LSP); Transistors T1b, T1c, T3nb, and T3nc are provided, and the first node Q is applied to the first constant voltage GVDD according to a real-time compensation signal (VRT) in a blank section of the corresponding stage. ) and the first node (Q) control unit 22 in the blank section for discharging the first node (Q) to the second constant voltage (GVSS2) according to the start signal (VST) signal; Transistors T1, T1a, T3n, and T3na are provided, and the first node Q is charged to the set voltage according to the set signal SET during the driving period of the corresponding stage, and a reset signal ( a first node (Q) controller 23 for discharging the first node (Q) to a second constant voltage (GVSS2) according to the RESET); a second node Qh control unit 24 including a transistor T3q to charge a second node Qh to the first constant voltage GVDD according to the voltage of the first node Q; Inverter unit ( 25); It includes a pull-up transistor T6c and a pull-down transistor T7c, and receives one clock signal CRCLK(n) from among a plurality of clock signals for outputting carry pulses to receive the first node Q and the third node Qb a carry pulse output unit 26 for outputting a carry pulse CR(n) according to the voltage of ); A pull-up transistor T6, a pull-down transistor T7, and a bootstrapping capacitor C2 for preventing output loss, and one clock signal SCCLK(n) among clock signals for outputting a plurality of scan pulses ) and a scan pulse output unit 27 for outputting a scan pulse SC(n) according to the voltages of the first node Q and the third node Qb; and transistors T3, T3a, T5, T5a, and T5b, the set signal SET, the vertical real time (VRT) signal, and the storage unit 21 in the blank section The first node Q, the third node Qb, the carry pulse output unit 26 and the scan pulse output unit 27 according to the signal M of It is configured with a stabilizing portion (28).

Here, the set signal SET is a carry pulse CR(n-3) output from a previous stage ((n-3)-th stage), and the reset signal RESET is a subsequent stage ((n+3) th stage) may be a carry pulse CR(n+3) output.

The transistor T3q of the second node Qh control unit 24 is turned on/off according to the voltage of the first node Q to apply a first constant voltage GVDD to the second node Qh. supply to

The operation of the (n)-th stage ST(n) of the gate driving circuit according to the first embodiment of the present invention configured as described above will be described below.

6 is a waveform diagram of the (n)-th stage ST(n) according to the first embodiment of the present invention.

The storage unit 21 converts the set signal SET according to the line select pulse (LSP) to the carry pulse CR(n-3) output from the (n-3)th previous stage to the capacitor C1. charge in

In the blank section, the first node Q control unit 22 converts the first node Q to a first constant voltage GVDD according to a real-time compensation signal (VRT) in the blank section. It charges and discharges the first node Q to the second constant voltage GVSS2 according to the start signal VST.

Timings of the line selection signal LSP, the real-time compensation signal VRT, and the start signal VST, and the operations of the storage unit 21 and the blank section first node Q control unit 22 are shown in FIG. 9 will be described later.

The first node Q control unit 23 charges the first node Q to the set voltage according to the set signal SET during the driving period of the corresponding stage, and according to the reset signal RESET The first node Q is discharged to a second constant voltage GVSS2.

Accordingly, when the set signal SET is high, the transistors T1 and T1a are turned on to apply the set voltage to the first node Q, so that the first node Q is high. become a state

A clock signal CRCLK(n) for outputting a carry pulse and a clock signal SCCLK(n) for outputting a scan pulse are respectively applied to the carry pulse output unit 26 and the scan pulse output unit 27, and the scan When the pulse output clock signal SCCLK(n) is applied high, the first node Q is bootstrapped (or coupled) by the bootstrapping capacitor C2 of the scan pulse output unit 27 . )) and has a higher potential.

In the state in which the first node Q is bootstrapped as described above, the carry pulse output unit 26 and the scan pulse output unit 27 each receive an input clock signal CRCLK(n) and The clock signal SCCLK(n) for outputting the scan pulse is output as the carry pulse CR(n) and the scan pulse SC(n).

When the set signal SET is input to a high state and the first node Q becomes a high state, the transistor T3q of the control unit 24 of the second node Qh is turned on to turn on the second node (Qh) is charged to the first constant voltage GVDD.

Accordingly, when the second node Qh is charged to the first constant voltage GVDD, the transistors T4q and T5q of the inverter unit 25 are turned on to invert the third node Qb to a low state. make it

Then, when the reset signal RESET is input to a high state, the transistors T3 and T3na of the first node Q control unit 23 are turned on to apply the first node Q to a second constant voltage ( discharge to GVSS2). Accordingly, the first node S and the second node Qh are in a low state, and the third node Qb is in a high state.

When driven in this way, the stabilizing unit 28 operates according to the set signal SET, the vertical real time (VRT) signal, and the third node (M) of the storage unit 21. Qb) is discharged to the second constant voltage GVSS2, and ripple generation of the first node Q, the scan pulse output unit 15, and the carry pulse output unit 16 is prevented.

5 and 6 , in the gate driving circuit according to the first embodiment of the present invention, a separate second node Qh is provided, and the second node Qh depends on the voltage of the first node Q. A first constant voltage GVDD is charged in the node Qh, and the transistors T4q and T5q of the inverter unit 25 are controlled by the voltage of the second node Qh.

Accordingly, since the transistors T4q and T5q of the inverter unit 25 are not affected by the bootstrapping (or coupling) voltage of the first node Q, the gate driving circuit performs under driving. Even if the swing width of the clock pulse is increased to 24V to -12V, there is no fear of being blacked down.

In the gate driving circuit according to the first embodiment of the present invention as described with reference to FIGS. 5 and 6 , it is possible to drive without the storage unit 21 and the first node (Q) control unit 22 of the blank section.

However, when real-time compensation driving is performed using the storage unit 21 and the blank section first node (Q) control unit 22, the gate according to the first embodiment of the present invention as described with reference to FIGS. 5 and 6 . In the driving circuit, the first node Q may be discharged because inverting is not performed between the first node Q and the third node Qb.

That is, in FIGS. 5 and 6 , when the first node Q and the second node Qh are in the high state and the third node Qb is inverted to the low state, the high level of the third node Qb is The transition time from the state to the low state is increased. At this time, since the transistors T3 and T3a of the stabilization unit 28 for preventing the ripple of the first node Q are not completely turned off, the first node Q and the second node Qh discharge may occur.

Accordingly, the gate driving circuit according to the second embodiment of the present invention can prevent the above-described phenomenon.

7 is a block diagram illustrating a configuration of an (n)-th stage ST(n) of the gate driving circuit according to the second embodiment of the present invention. In the configuration of the stage ST(n), the corresponding stage is transmitted to the first node Q control unit 22 in the blank period according to a vertical real time (VRT) signal for real-time compensation in the blank period. A transistor T1d that charges the node Qh to the first constant voltage GVDD may be further added.

That is, the first node (Q) control unit 22 of the blank section of the (n)-th stage ST(n) of the gate driving circuit according to the second embodiment of the present invention is stored in the storage unit 21 . The transistor T1b is turned on/off according to the set signal SET; the carry pulse CR(n-3) output from the (n-3)th previous stage, and the real-time compensation signal VRT. The transistor T1c is turned on/off to charge the first node Q to a first constant voltage through the transistor T1b, and the transistor T1c is turned on/off according to the real-time compensation signal VRT. a transistor T1d for charging the second node Q to a first constant voltage through the transistor T1b, and two transistors for discharging the first node Q according to a start signal VST signal ( T3nb, T3nc).

The remaining components are the same as those of the gate driving circuit according to the first embodiment of the present invention described with reference to FIG. 5 and thus will be omitted.

8 is a waveform diagram of the (n)-th stage ST(n) according to the second embodiment of the present invention.

During real-time compensation driving (VRT compensation section), since the second node Qh is initially charged to the first constant voltage GVDD by the real-time compensation signal VRT, in the high state of the third node Qb An increase in the transition time to the low state is prevented, and the transistors T3 and T3a of the stabilization unit 28 are completely turned on to discharge the first node Q and the second node Qh. phenomenon can be prevented.

9 is a real-time compensation driving waveform diagram of the (n)-th stage ST(n) according to the first and second embodiments of the present invention.

9 , the set signal SET is a carry pulse CR(n-3) output from a previous stage ((n-3)th stage), and the reset signal RESET is a subsequent stage ((n-3)th stage) The carry pulse CR(n+3) output from the +3)th stage) will be described as an example.

First, the basic driving period is as described with reference to FIGS. 6 and 8 .

First, before the basic driving period, since the start signal VST is supplied in a high state, the transistors T3n and T3na are turned on by the start signal VST to provide the first node Q with a second constant voltage. Discharge to (GVSS2). That is, the first node Q is initialized.

In the first section (a), the set signals SET, CR(n-3) and the line selection pulse LSP are simultaneously input to a high state, and the real-time compensation yaw signal VRT maintains a low state. .

Then, the storage unit 21 turns on the transistors Ta and Tb according to the line selection signal LSP to charge the set signals SET and CR(n-3) in the capacitor C1. Accordingly, the node M of the capacitor C1 maintains a high state.

In addition, since the real-time compensation signal VRT maintains a low state during the basic driving period, the first node Q control unit 22 charges the first node Q with the first constant voltage GVDD during the blank period. I never do that.

The first node (Q) control unit 23 turns on the transistors T1 and T1a according to the set signals SET, CR(n-3), and the set signals SET, CR(n-3)) Since a voltage is applied to the first node Q, the first node Q is in a high state.

When the first node Q is in the high state, the second node Qh control unit 24 turns on the transistor T3q to set the second node Qh to the first constant voltage GVDD. In the inverter unit 25, the transistors T4q and T5q of the inverter unit 25 are turned on according to the voltage of the second node Qh to put the third node Qb in a low state. invert

In the second section (b) of the basic driving period, the carry pulse output unit 26 and the scan pulse output unit 27 are provided with a carry pulse output clock signal CRCLK(n) and a scan pulse output clock signal SCCLK (n)) is applied in a high state, respectively, so that the first node Q is bootstrapped by the bootstrap capacitor C2 of the scan pulse output unit 27 to have a higher potential.

In the state in which the first node Q is bootstrapped as described above, the carry pulse output unit 26 and the scan pulse output unit 27 each receive an input clock signal CRCLK(n) and The clock signal SCCLK(n) for outputting the scan pulse is output as the carry pulse CR(n) and the scan pulse SC(n).

Then, in the third section c of the basic driving section, the reset signal RESET, CR(n+3) is input to a high state, and the transistor ( T3 and T3na are turned on to discharge the first node Q to a second constant voltage GVSS2. Accordingly, the first node S and the second node Qh are in a low state, and the third node Qb is in a high state.

The following describes the operation of the real-time compensation section.

In the first section d of the real-time compensation section, all of the set signals SET, CR(n-3) and the line selection pulse LSP maintain a low state, and only the real-time compensation signal VRT is in a high state. has

Accordingly, since the real-time compensation signal VRT is in a high state and the node M of the storage unit 21 is also in a high state, the transistors T1b and T1c of the first node Q control unit 22 of the blank period are in a high state. , T1d) are all turned on to charge the first node Q with a first constant voltage GVDD.

When the first node Q is in the high state, the second node Qh control unit 24 turns on the transistor T3q to set the second node Qh to the first constant voltage GVDD. In the inverter unit 25, the transistors T4q and T5q of the inverter unit 25 are turned on according to the voltage of the second node Qh to put the third node Qb in a low state. invert

And, in the second section (e) of the real-time compensation section, the carry pulse output unit 26 and the scan pulse output unit 27 have a carry pulse output clock signal CRCLK(n) and a scan pulse output clock signal ( SCCLK(n)) is applied in a high state, respectively, so that the first node Q is bootstrapped by the bootstrap capacitor C2 of the scan pulse output unit 27 to have a higher potential.

In the state in which the first node Q is bootstrapped as described above, the carry pulse output unit 26 and the scan pulse output unit 27 each receive an input clock signal CRCLK(n) and The clock signal SCCLK(n) for outputting the scan pulse is output as the carry pulse CR(n) and the scan pulse SC(n).

And, in the third section f of the real-time compensation section, since the start signal VST is supplied in a high state, the transistors T3nb and T3nc of the first node Q control section 22 of the blank section are all turned on. is turned on to discharge the first node Q to a second constant voltage GVDD. Accordingly, the first node S and the second node Qh are in a low state, and the third node Qb is in a high state.

As described in FIG. 9 , when real-time compensation is driven (VRT compensation section), the second node Qh is initially charged to the first constant voltage GVDD by the real-time compensation signal VRT, so that the third node The transition time from the high state to the low state of (Qb) is prevented from being increased, and the transistors T3 and T3a of the stabilization unit 28 are completely turned on so that the first node Q and the first A phenomenon in which the second node Qh is discharged can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

21: storage unit 22: blank section first node (Q) control unit
23: first node (Q) control unit 24: second node (Qh) control unit
25: inverter unit 27: carry pulse output unit
27: scan pulse output unit 28: stabilization unit

Claims (10)

a plurality of stages to sequentially supply a scan signal to each of the plurality of gate lines;
The nth stage is
a first node controller for controlling the first node according to the carry pulse output from the previous stage and the carry pulse output from the rear stage;
a second node controller for controlling a second node according to the voltage of the first node;
an inverter unit for inverting the voltage of the second node and applying it to a third node;
a scan pulse output unit receiving one of a plurality of scan pulse output clock signals and outputting a scan pulse according to voltages of the first node and the third node; and
A gate driving circuit comprising: a carry pulse output unit configured to receive one of a plurality of carry pulse output clock signals and output a carry pulse according to voltages of the first node and the third node. The method of claim 1,
and the second node control unit is turned on/off according to the voltage of the first node and includes a transistor configured to supply a first constant voltage to the second node. The method of claim 1,
a storage unit selectively storing a carry pulse output from the previous stage according to the line selection signal LSP; and
A gate driving circuit further comprising a blank section first node controller for charging the first node according to a real-time compensation signal (VRT) in the blank section of the corresponding stage and discharging the first node according to a start signal (VST) signal . The method of claim 1,
a storage unit selectively storing a carry pulse output from the previous stage according to the line selection signal LSP; and
A blank section first node controller for charging the first node and the second node according to a real-time compensation signal (VRT) in the blank section of the corresponding stage and discharging the first node according to a start signal (VST) signal The gate driving circuit further provided. 5. The method of claim 4,
The blank section first node control unit,
a first transistor turned on/off according to the real-time compensation signal (VRT) to charge the first node with a first constant voltage;
and a second transistor turned on/off according to the real-time compensation signal (VRT) to charge the second node with a first constant voltage. A display panel in which a plurality of gates and data lines are disposed to include a plurality of sub-pixels in a matrix form, and a data voltage is applied to the plurality of data lines in response to a scan pulse supplied to each gate line to display an image. ;
a gate driving circuit for sequentially supplying scan pulses to respective gate lines;
a data driving circuit supplying the data voltage to the plurality of data lines; and
Image data input from the outside is arranged to be suitable for the size and resolution of the display panel and supplied to the data driving circuit, and synchronization signals input from the outside are applied to a plurality of gate control signals and a plurality of data control signals to the gate driving circuit and a timing controller respectively supplying the data to the data driving circuit,
The gate driving circuit includes a plurality of stages to sequentially supply a scan signal to each of the plurality of gate lines,
The nth stage is
a plurality of stages to sequentially supply a scan signal to each of the plurality of gate lines;
The nth stage is
a first node controller for controlling the first node according to the carry pulse output from the previous stage and the carry pulse output from the rear stage;
a second node controller for controlling a second node according to the voltage of the first node;
an inverter unit for inverting the voltage of the second node and applying it to a third node;
a scan pulse output unit receiving one of a plurality of scan pulse output clock signals and outputting a scan pulse according to voltages of the first node and the third node; and
A flat panel display comprising: a carry pulse output unit that receives one of a plurality of carry pulse output clock signals and outputs a carry pulse according to voltages of the first node and the third node. 7. The method of claim 6,
and the second node controller is turned on/off according to the voltage of the first node to supply a first constant voltage to the second node. 7. The method of claim 6,
a storage unit selectively storing a carry pulse output from the previous stage according to the line selection signal LSP; and
A flat panel display device further comprising: a blank section first node controller for charging the first node in a blank section of the corresponding stage according to a real-time compensation signal (VRT) and discharging the first node according to a start signal (VST) signal . 7. The method of claim 6,
a storage unit selectively storing a carry pulse output from the previous stage according to the line selection signal LSP; and
A blank section first node controller for charging the first node and the second node according to a real-time compensation signal (VRT) in the blank section of the corresponding stage and discharging the first node according to a start signal (VST) signal A flat panel display device further comprising: 10. The method of claim 9,
The blank section first node control unit,
a first transistor turned on/off according to the real-time compensation signal (VRT) to charge the first node with a first constant voltage;
and a second transistor turned on/off according to the real-time compensation signal (VRT) to charge the second node with a first constant voltage.

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