KR20050047744A - Gate driver circuit and display device having the same - Google Patents

Abstract

Disclosed are a gate driving circuit capable of improving operating characteristics and a display device having the same. The display panel includes a plurality of gate lines and a plurality of data lines. The first gate driving circuit includes a plurality of first stages connected dependently with each other, and provides a first gate driving signal output from each of the first stages with a blank period to an odd-numbered gate line. The second gate driving circuit includes a plurality of second stages connected dependently to each other, and provides a second gate driving signal output from each of the second stages to the even-numbered gate lines corresponding to the blank period. Therefore, the operating characteristics of the display device can be improved.

Description

Gate driver circuit and display device having same {GATE DRIVER CIRCUIT AND DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a gate driving circuit and a display device having the same, and more particularly, to a gate driving circuit and a display device having the same can improve the operating characteristics.

A liquid crystal display device, which is one of display devices, includes a liquid crystal display panel including a first substrate, a second substrate provided to face the first substrate, and a liquid crystal layer formed between the first substrate and the first substrate.

The liquid crystal display panel includes a display area and a peripheral area adjacent to the display area. The display area includes a plurality of gate lines extending in a first direction and a plurality of data lines extending in a second direction perpendicular to the first direction. Thin film transistors (hereinafter referred to as TFTs) are connected to each of the gate lines and the data lines.

In the peripheral area, a gate driving circuit for sequentially outputting gate driving signals to a plurality of gate lines is formed, and a data driving chip for outputting image signals to a plurality of data lines is mounted.

In general, the gate driving circuit includes one shift register in which a plurality of stages are connected in a cascade manner.

Each stage includes a clock terminal, an output terminal, an input terminal, and a control terminal. The output terminal of each stage is electrically connected to the corresponding gate line among the gate lines, and is connected to the control terminal of the previous stage and the input terminal of the next stage, respectively. Accordingly, the gate driving signal output from the output terminal is not only applied to the corresponding gate line but also serves to control the operation of the previous stage and the next stage.

However, as the liquid crystal display panel becomes larger in size, the length of the plurality of gate lines also becomes longer, and the number of TFTs provided in the display area also increases. The increase in the length of the gate lines and the increase in the number of the TFTs cause a delay in the gate driving signal output from the gate driving circuit.

Nevertheless, the delayed gate driving signal is again provided to the input terminal of the next stage and the control terminal of the previous stage, respectively, to control the driving of each stage. As a result, a vicious cycle in which the gate drive signal output from each stage is further delayed is repeated.

Accordingly, it is an object of the present invention to provide a gate driving circuit for improving the operating characteristics.

Further, another object of the present invention is to provide a display device having the above gate driving circuit.

In the gate driving circuit according to an aspect of the present invention, a plurality of stages are connected and output a gate driving signal output from each stage.

Each stage includes an input terminal, a clock terminal, a control terminal, and first and second output terminals. The input terminal receives a stage driving signal output from any one of the previous stages, and the clock terminal receives a clock of any one of a plurality of clocks of different phases while keeping a low state longer than a high state. The control terminal receives a stage driving signal output from any one of the following stages.

The first output terminal outputs the clock received as the clock terminal as the gate driving signal, and the second output terminal outputs the clock received as the clock terminal as a stage driving signal.

According to another aspect of the present invention, a display device includes a display panel, a first gate driving circuit, a second gate driving circuit, and a data driving circuit. The display panel includes a plurality of gate lines and a plurality of data lines, and the data driver outputs data signals to the plurality of data lines.

The first gate driving circuit includes a plurality of first stages connected dependently to each other, and provides a first gate driving signal output from each of the first stages with a blank period to an odd-numbered gate line. The second gate driving circuit includes a plurality of second stages connected dependently to each other, and provides a second gate driving signal output from each of the second stages to an even-numbered gate line corresponding to the blank period.

According to still another aspect of the present invention, a display device includes a display panel, a first gate driving circuit, a second gate driving circuit, and a data driving circuit. The display panel includes a plurality of gate lines and a plurality of data lines.

The first gate driving circuit includes a plurality of first stages connected dependently to each other. Each of the first stages may provide a first gate driving signal having a first dummy period and a first active period adjacent to the first dummy period to an odd-numbered gate line.

The second gate driving circuit includes a plurality of second stages connected dependently to each other. Each second stage provides a second gate driving signal having a second dummy period corresponding to the first active period and a second active period adjacent to the second dummy period to an even-numbered gate line.

The data driving circuit outputs data signals to the plurality of data lines corresponding to the first and second active periods.

According to such a gate driving circuit and a display device having the same, a first gate driving circuit outputting a first gate driving signal to an odd gate line and a second gate driving circuit outputting a second gate driving signal to an even gate line are provided. By operating individually, the operating characteristics of the display device can be improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 500 according to an exemplary embodiment of the present invention may include a lower substrate 100, an upper substrate 200 facing the lower substrate 100, and the lower substrate 100. And a liquid crystal display panel 300 formed of a liquid crystal layer (not shown) interposed between the upper substrate 200 and the upper substrate 200.

The liquid crystal display panel 300 includes a display area DA for displaying an image and first to third peripheral areas SA1 and SA2 adjacent to the display area DA.

A plurality of pixels are provided in a matrix form in the display area DA, and each of the plurality of pixels includes a gate line GL extending in a first direction D1 and a second orthogonal to the first direction D1. The data line DL extends in the direction D2 and insulates and crosses the gate line GL. The TFT 110 is connected to the gate line GL and the data line DL, and the liquid crystal capacitor Clc is coupled to the drain electrode of the TFT 110. Therefore, 2n gate lines GL1 to GL2n and m data lines DL1 to DLm are respectively provided in the display area DA. Here, n and m are one or more natural numbers.

A first gate for outputting a first gate driving signal to odd-numbered gate lines GL1 to GL2n-1 in the first peripheral area PA1 adjacent to the first ends of the 2n gate lines GL1 to GL2n. The driving circuit 350 is formed. A second gate driving circuit for outputting a second gate driving signal to even-numbered gate lines GL2 to GL2n in the second peripheral area PA2 adjacent to the second ends of the 2n gate lines GL1 to GL2n. 360 is formed.

In addition, a driving chip 370 for outputting an image signal to the m data lines DL1 to DLm is mounted in the third peripheral area PA3 adjacent to one end of the m data lines DL1 to DLm. do.

A flexible printed circuit board (FPC) 400 is attached to one side of the third peripheral area PA3. The FPC 400 electrically connects an external device (not shown) for driving the liquid crystal display panel 300 and the driving chip 370. Therefore, the driving chip 370 outputs an image signal, first and second gate control signals in response to various signals provided from the external device.

The driving chip 370 outputs the image signals to the m data lines DL1 to DLm, provides the first gate control signal to the first gate driving circuit 350, and controls the second gate. The signal is provided to the second gate driving circuit 360. The first gate driving circuit 350 outputs a first gate driving signal to the odd-numbered gate lines GL1 to GL2n-1 in response to the first gate control signal, and the second gate driving circuit 360 The second gate driving signal is output to the even-numbered gate lines GL2 to GL2n in response to the second gate control signal.

FIG. 2 is a diagram illustrating in detail the first gate driving circuit illustrated in FIG. 1, and FIG. 3 is a diagram illustrating the second gate driving circuit illustrated in FIG. 1 in detail.

Referring to FIG. 2, the first gate driving circuit 350 includes one first shift register including n + 1 odd stages SRC_O1 to SRC_On + 1 connected to each other. The plurality of odd stages SRC_O1 to SRC_On + 1 includes n driving stages SRC_O1 to SRC_On and one dummy stage SRC_On + 1.

Each odd stage SRC_O1 to SRC_On + 1 includes an input terminal IN, a clock terminal CK, a control terminal CT, a first output terminal GOUT, and a second output terminal SOUT.

The clock terminal CK is provided with a first clock CK_O or a second clock CKB_O. That is, the first clock CK_O is provided to odd-numbered odd stages SRC_O1, SRC_O3, ... SRC_On + 1 among the plurality of odd stages SRC_O1 to SRC_On + 1, and the second clock CKB_O. Is provided to the even-numbered odd stages SRC2, SRC4, ... SRC_On.

The first output terminal GOUT of the odd-numbered odd stages SRC_O1, SRC_O3, ... outputs the first clock CK_O as a first gate driving signal, and the even-numbered odd stages SRC_O2, SRC_O4, .. The first output terminal GOUT of SRC_On outputs the second clock CKB_O as a first gate driving signal.

The first output terminal GOUT of the n odd stages SRC_O1 to SRC_On may have a one-to-one correspondence to the n odd-numbered gate lines GL1, GL3,... GL2n-1 provided in the display area DA. Connected. Accordingly, the first gate driving signals output from the first output terminals GOUT of the n odd stages SRC_O1 to SRC_On are sequentially applied to the odd-numbered gate lines GL1, GL3,..., GL2n-1. . Here, the first output terminal GOUT of the dummy stage SRC_On + 1 is maintained in a floating state because there is no corresponding gate line.

The second output terminal SOUT of the odd-numbered odd stages SRC_O1, SRC_O3, ... SRC_On + 1 outputs the first clock CK_O as a stage driving signal, and the even-numbered odd stages SRC2, SRC4,. The second output terminal SOUT of SRC_On outputs the second clock CKB_O as a stage driving signal.

The input terminal IN receives a stage driving signal output from the second output terminal SOUT of the previous stage, and the control terminal CT is a stage output from the second output terminal SOUT of the next stage. Receive a drive signal.

Here, since there is no previous stage of the first order stage SRC_O1, the first start signal ST_O is provided to the input terminal IN of the first order stage SRC_O1. In addition, since the next stage of the dummy stage SRC_On + 1 does not exist, the first start signal ST_O is provided to the control terminal CT of the dummy stage SRC_On + 1.

Each of the odd stages SRC_O1 to SRC_On + 1 further includes a ground voltage terminal VSS provided with a ground voltage and a driving voltage terminal VDD provided with a driving voltage.

Referring to FIG. 3, the second gate driving circuit 360 includes one second shift register including n + 1 even stages SRC_E1 to SRC_En + 1 connected dependently to each other. The plurality of even stages SRC_E1 to SRC_En + 1 include n driving stages SRC_E1 to SRC_En and one dummy stage SRC_En + 1.

Each even stage SRC_E1 to SRC_En + 1 includes an input terminal IN, a clock terminal CK, a control terminal CT, a first output terminal GOUT, and a second output terminal SOUT.

The clock terminal CK is provided with a third clock CK_E or a fourth clock CKB_E. That is, the third clock CK_E is provided to odd even stages SRC_E1, SRC_E3, ... SRC_En + 1 of the plurality of stages SRC_E1 to SRC_En + 1, and the fourth clock CKB_E is provided. The even numbered even stages SRC_E2, SRC_E4, ... SRC_En are provided.

The first output terminal GOUT of the odd-numbered even stages SRC_E1, SRC_E3, ... outputs the third clock CK_E as a second gate driving signal, and the even-numbered even stages SRC_E2, SRC_E4, .. The first output terminal GOUT of SRC_En outputs the fourth clock CKB_E as a second gate driving signal.

The first output terminal GOUT of the n even stages SRC_E1 to SRC_En is connected in a one-to-one correspondence to the n even-numbered gate lines GL2, GL4,... GL2n provided in the display area DA. . Accordingly, the second gate driving signals output from the first output terminals GOUT of the n even stages SRC_E1 to SRC_En are sequentially applied to the even-numbered gate lines GL2, GL4,..., GL2n.

The second output terminal SOUT of the odd-numbered even stages SRC_E1, SRC_E3, ... outputs the third clock CK_E as a stage driving signal, and the even-numbered stages SRC_E2, SRC_E4, ... SRC_En The second output terminal SOUT of the outputs the fourth clock CKB_E as a stage driving signal.

The input terminal IN receives a stage driving signal output from the second output terminal SOUT of the previous stage, and the control terminal CT is a stage output from the second output terminal SOUT of the next stage. Receive a drive signal.

Here, since there is no previous stage of the first even stage SRC_E1, the second start signal ST_E is provided to the input terminal IN of the first odd stage SRC_E1. In addition, since the next stage of the dummy stage SRC_En + 1 does not exist, the second start signal ST_E is provided to the control terminal CT of the dummy stage SRC_En + 1.

4 is an input / output waveform diagram of the first and second gate driving circuits shown in FIGS. 2 and 3.

2 to 4, each of the first to fourth clocks CK_O, CKB_O, CK_E, and CKB_E having different phases maintains the low state longer than the high state for one period T. That is, each of the first to fourth clocks CK_O, CKB_O, CK_E, and CKB_E maintains a high state for a quarter period (1 / 4T), and maintains a low state for the third quarter period (3 / 4T). Keep it.

The second clock CKB_O has the same period T as the first clock CK_O and is delayed by a half cycle (1 / 2T) than the first clock CK_O, and the third clock ( CK_E is delayed by 1/4 period (1 / 4T) than the first clock CK_O while having the same period T as the first clock CK_O. In addition, the fourth clock CKB_E is delayed by 3/4 period (3 / 4T) than the first clock CK_O while having the same period T as the first clock CK_O. It is delayed by a half cycle (1 / 2T) from the clock CK_E.

The first start signal ST_O is output in the high state just before the first clock CK_O is raised to the high state. In response to the first start signal ST_O, the first order stage SRC_O1 outputs the first clock CK_O in a high state as a first gate driving signal. The output first gate driving signal is provided to the first gate line GL1 of 2n gate lines GL1 to GL2n.

Thereafter, the second start signal ST_E is output in the high state just before the third clock CK_E rises to the high state. In response to the second start signal ST_E, the first even stage SRC_E1 outputs a third clock CK_E in a high state as a second gate driving signal. The output second gate driving signal is provided to a second gate line GL2. Therefore, the time point at which the second gate driving signal is output from the first even stage SRC_E1 is after the output of the first odd stage SRC_O1 is switched to the low state.

Next, when the second clock CKB_O is generated in the high state after the first clock CK_O is switched to the low state, the second order stage is responded to in response to the stage driving signal output from the first order stage SRC_O1. SRC_O2 outputs a high second clock CKB_O as a first gate driving signal. The output first gate driving signal is provided to a third gate line GL3.

Here, the time when the second odd stage SRC_O2 outputs the first gate driving signal is after the output of the first even stage SRC_E1 is switched to the low state. Accordingly, a first blank period BL1 is formed between the first gate driving signal output from the first odd stage SRC_O1 and the first gate driving signal output from the second odd stage SRC_O2. As shown in FIG. 4, the first even stage SRC_E1 outputs a second gate driving signal corresponding to the first blank period BL1.

Thereafter, when the fourth clock CKB_E is generated in the high state after the third clock CK_E is switched to the low state, the second even stage is responded to in response to the stage driving signal output from the first even stage SRC_E1. SRC_E2 outputs the high fourth clock CKB_E as the second gate driving signal. The output second gate driving signal is provided to a fourth gate line GL4.

The second even stage SRC_E2 outputs the second gate driving signal after the output of the second odd stage SRC_O2 is turned low. Accordingly, a second blank period BL2 is formed between the second gate driving signal output from the first even stage SRC_E1 and the second gate driving signal output from the second even stage SEC_E2. As shown in FIG. 4, the second odd stage SRC_O2 outputs a second gate driving signal corresponding to the second blank period BL2.

As a result, the n odd stages SRC_O1 to SRC_On and the n even stages SRC_E1 to SRC_En operate alternately, so that the first and the second gate lines GL1 to GL2n are divided into odd and even numbers. The two gate drive signal is applied alternately.

FIG. 5 is an input / output waveform diagram of the first and second gate driving circuits shown in FIGS. 2 and 3.

2, 3, and 5, the first clock CK_O remains high for 1/2 cycle (1 / 2T) and low for the other half cycle (1 / 2T). Keep it. The second clock CKB_O is delayed by 1/2 cycle (1 / 2T) of the first clock CK_O and has a phase inverted with the first clock CK_O.

The third clock CK_E maintains a high state for one half period (1 / 2T) and a low state for the other half period (1 / 2T). The fourth clock CKB_E is delayed by 1/2 cycle (1 / 2T) of the third clock CK_E and has a phase inverted with the third clock CK_E.

In addition, the third clock CK_E is delayed by a quarter period (1 / 4T) than the first clock CK_O, and the fourth clock CKB_E is 1/4 of the second clock CKB_O. Delay by a period (1 / 4T).

The first start signal ST_O is output in the high state just before the first clock CK_O is raised to the high state. In response to the first start signal ST_O, the first order stage SRC_O1 outputs the first clock CK_O in a high state as a first gate driving signal. The output first gate driving signal is provided to the first gate line GL1 of 2n gate lines GL1 to GL2n.

Thereafter, when the second clock CKB_O is generated in the high state after the first clock CK_O is switched to the low state, the second order stage is responded to in response to the stage driving signal output from the first order stage SRC_O1. SRC_O2 outputs a high second clock CKB_O as a first gate driving signal. The output first gate driving signal is provided to a third gate line GL3.

The second start signal ST_E is output in the high state just before the third clock CK_E rises to the high state. In response to the second start signal ST_E, the first even stage SRC_E1 outputs a third clock CK_E in a high state as a second gate driving signal. The output second gate driving signal is provided to a second gate line GL2.

Thereafter, when the fourth clock CKB_E is generated in the high state after the third clock CK_E is switched to the low state, the second even stage is responded to in response to the stage driving signal output from the first even stage SRC_E1. SRC_E2 outputs the high fourth clock CKB_E as the second gate driving signal. The output second gate driving signal is provided to a fourth gate line GL4.

As illustrated in FIG. 5, the first gate driving signal has a first dummy section D1 and a first active section A1 adjacent to the first dummy section D1, and the second gate driving signal includes the first dummy section D1. A second dummy section D2 corresponding to the first active section A1 and a second active section A2 adjacent to the second dummy section D2 are included.

The first quarter period (1 / 4T) is the first dummy period (D1) and the remaining quarter period (1 / 4T) of the half period (1 / 2T) of the first gate driving signal is generated. Is defined as the first active period A1. The first quarter period (1 / 4T) is the second dummy period (D2) of the 1/2 period (1 / 2T) in which the second gate driving signal is generated, and the remaining 1/4 period (1 / T). 4T) is defined as the second active period A2.

Here, the second gate driving signal applied to the second gate line GL2 is delayed by a quarter period (1 / 4T) than the first gate driving signal applied to the first gate line GL1. The first gate driving signal applied to the first gate line GL3 is delayed by a quarter period (1 / 4T) than the second gate driving signal applied to the second gate line GL2.

Accordingly, the second dummy period of the first active period A1 of the first gate driving signal A1 applied to the first gate line GL1 and the second gate driving signal applied to the second gate line GL2. D2) overlap each other. In addition, the first dummy period of the second active period A2 of the second gate driving signal A2 applied to the second gate line GL2 and the first gate driving signal applied to the third gate line GL3. A1) overlap each other.

In this case, the driving chip 370 (shown in FIG. 1) outputs a first data driving signal DATA1 in the first active period A1, and a second data driving signal in the second active period A2. DATA2) is output. This process is repeated, and the first and second gate driving signals are alternately applied to the 2n gate lines GL1 to GL2n divided into odd and even numbers.

FIG. 6 is an internal circuit diagram of the first and second gate driving circuits shown in FIGS. 2 and 3.

Referring to FIG. 6, each of the odd and even stages includes a first pull-up unit 351, a second pull-up unit 352, a first pull-down unit 353, a second pull-down unit 354, a pull-up driving unit 355, and And a pull-down driver 356.

The first pull-up unit 351 outputs one of the first to fourth clocks CK_O, CKB_O, CK_E, and CKB_E provided to the clock terminal CK to the first output terminal GOUT as a gate driving signal. . The second pull-up unit 352 outputs one of the first to fourth clocks CK_O, CKB_O, CK_E, and CKB_E provided to the clock terminal CK to the second output terminal SOUT as a stage driving signal. do.

In the first pull-up unit 351, a gate electrode is connected to the first node N1, a source electrode is connected to the clock terminal CK, and a drain electrode is connected to the first output terminal GOUT. It consists of transistor NT1. When the gate electrode is connected to the first node N1 and the source electrode is connected to the clock terminal CK, the second pull-up unit 352 has a second electrode connected to the second output terminal SOUT. It consists of a transistor NT2.

The first pull-down unit 353 is turned on after the first pull-up unit 351 is turned off to discharge the gate driving signal output from the first output terminal GOUT, and the second pull-down unit 354 is turned on after the second pull-up unit 352 is turned off to discharge the stage driving signal output from the second output terminal SOUT.

The first pull-down unit 353 has a third gate electrode connected to the second node N2, a drain electrode connected to the first output terminal GOUT, and a source electrode connected to the ground voltage terminal VSS. It consists of transistor NT3. The second pull-down unit 354 has a source electrode connected to the ground voltage terminal VSS when a gate electrode is connected to the second node N2 and a drain electrode is connected to the second output terminal SOUT. 4th transistor NT4.

The pull-up driving unit 355 includes fifth to seventh transistors NT5, NT6, and NT7 to turn on the first and second pull-up units 351 and 352.

In the fifth transistor NT5, a gate electrode is connected to the input terminal IN, a drain electrode is connected to a driving voltage terminal VDD, and a source electrode is connected to the first node N1. In the sixth transistor NT6, the gate electrode and the drain electrode are connected to the driving voltage terminal VDD, and a source electrode is connected to the third node N3. In the seventh transistor NT7, a gate electrode is connected to the first node N1, a drain electrode is connected to a third node N3, and a source electrode is connected to the ground voltage terminal VSS.

The pull-down driver 356 includes eighth and twelfth transistors NT8, NT9, NT10, NT11, and NT12, and turns off the first and second pull-up parts 351 and 352 while the first and second pull-up drivers 356 are turned off. The pull-down parts 353 and 354 are turned on.

In the eighth transistor NT8, a gate electrode is connected to the third node N3, a drain electrode is connected to the driving voltage terminal VDD, and a source electrode is connected to the second node N2. In the ninth transistor NT9, a gate electrode is connected to the first node N1, a drain electrode is connected to the second node N2, and a source electrode is connected to the ground voltage terminal VSS. In the tenth transistor NT10, a gate electrode is connected to the input terminal IN, a drain electrode is connected to the second node N2, and a source electrode is connected to the ground voltage terminal VSS.

In the eleventh transistor NT11, a gate electrode is connected to the second node N2, a drain electrode is connected to the first node N1, and a source electrode is connected to the ground voltage terminal VSS. In the twelfth transistor NT12, a gate electrode is connected to the control terminal CT, a drain electrode is connected to the first node N1, and a source electrode is connected to the ground voltage terminal VSS.

When the stage driving signal output from the second output terminal SOUT of the previous stage is provided to the input terminal IN, the fifth transistor NT5 is turned on so that the potential of the first node N1 gradually increases. Is raised. As the potential of the first node N1 is increased, the first and second transistors NT1 and NT2 are turned on, and gate driving signals and stage driving are applied to the first and second output terminals GOUT and SOUT. The signals are output respectively.

Meanwhile, when the sixth transistor NT7 is turned on as the potential of the first node N1 is increased while the sixth transistor NT6 is always maintained in the turned-on state, the sixth transistor NT6 is turned on. The potential of the three nodes N3 drops.

As the potential of the third node N3 falls, the eighth transistor NT8 maintains a turn-off state. Therefore, the driving voltage VDD is not provided to the second node N2. In addition, the ninth transistor NT9 is turned on when the potential of the first node N1 increases to maintain the potential of the second node N2 at the ground voltage VSS. And turn off the fourth transistors NT3 and NT4.

Subsequently, when a stage driving signal output from the second output terminal SOUT of the next stage is provided through the control terminal CT, the twelfth transistor NT12 is turned on and the first node N1 is turned on. Is discharged to the ground voltage VSS. As the potential of the first node N1 falls, the seventh and ninth transistors NT7 and NT9 are turned off.

Accordingly, the potential of the second node N2 gradually rises, and accordingly, the third and fourth transistors NT3 and NT4 are turned on to be output from the first and second output terminals GOUT and SOUT. Discharges the gate driving signal to the ground voltage VSS.

In this case, the tenth and eleventh transistors NT10 and NT11 are turned on as the potential of the second node N2 rises, thereby rapidly discharging the potential of the first node N1. While repeating this process, each stage outputs a gate driving signal and a stage driving signal that maintain a high state for a predetermined period.

7 is a diagram illustrating a dual liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 7, a dual liquid crystal display device 700 according to another exemplary embodiment of the present invention may include a main liquid crystal display panel 300, a sub liquid crystal display panel 600, a driving chip 370, and first and second flexible devices. Circuit boards 400 and 450 are included.

The main liquid crystal display panel 300 includes a main display area DA1 displaying a main image and first to fourth peripheral areas PA1, PA2, PA3, and PA4 adjacent to the main display area DA1. 2n main gate lines GL1-1 to GL1-2n and m main data lines DL1-1 to orthogonal to the main gate lines GL1-1 to GL1-2n in the main display area DA1. DL1-m) is provided.

The first main gate driving circuit 350 is formed in the first peripheral area PA1, and the second main gate driving circuit 360 is formed in the second peripheral area PA2. The first main gate driving circuit 350 outputs a gate driving signal to odd-numbered main gate lines GL1-1 to GL1-2n-1, and the second main gate driving circuit 360 is an even-numbered main gate. The gate driving signal is output to the lines GL1-2 to GL1-2n.

The driving chip 370 is mounted on the third peripheral area PA3, and the first flexible circuit board 400 is attached. The first flexible circuit board 400 is electrically connected to the driving chip 370 to apply various signals provided from the outside to the driving chip 370.

The driving chip 370 outputs a main image signal to the main data lines DL1-1 to DL1-m, and controls the first and second gates to the first and second main gate driving circuits 350 and 360. Output the signal. In addition, the driving chip 370 outputs a sub image signal and a third gate control signal. The sub image signal is applied to the sub data lines DL2-1 to DL2-j to be described later, and the third gate control signal is applied to the sub gate driving circuit 610 to be described later.

The second liquid crystal display panel 600 includes a sub display area DA2 for displaying a sub image and fifth and sixth peripheral areas PA5 and PA6 adjacent to the sub display area DA2. I sub-gate lines GL2-1 to GL2-i and j data lines DL2-1 to DL2 orthogonal to the sub-gate lines GL2-1 to GL2-i in the sub display area DA2. -j) is provided. Where i and n are two or more natural numbers and i is a number less than or equal to n. J and m are two or more natural numbers, and j is a number less than or equal to m.

The main and sub liquid crystal display panels 300 and 600 are electrically connected to each other by the second flexible printed circuit board 450. The first end of the second flexible printed circuit board 450 is attached to the fourth peripheral area PA4 of the main liquid crystal display panel 300, and the second end of the second flexible printed circuit board 450 is connected to the fifth peripheral area of the sub liquid crystal display panel 600. Is attached to area PA5. Therefore, even when the driving chip 400 is mounted in the first peripheral area PA1, the driving chip 400 is electrically connected to the second liquid crystal display panel 600 by the second flexible printed circuit board 450. Is connected.

That is, some of the main data lines DL1-1 to DL1-j are connected to the sub data lines through the first connection line groups CL1-1 to CL1-j provided on the second flexible printed circuit board 450. Is electrically connected to DL2-1 to DL2-j). Accordingly, the sub image signal output from the driving chip 370 passes through the part DL1-1 to DL1-j and the first connection line CL1-1 to CL1-j of the main data line. (DL2-1 to DL2-j).

The sub gate driving circuit 610 is formed in the sixth peripheral area PA6. The sub-gate driving circuit 610 sequentially outputs gate driving signals to the sub gate lines GL2-1 to GL2-i in response to the third gate control signal received from the driving chip 370.

According to such a gate driving circuit and a display device having the same, a first gate driving circuit which outputs a gate driving signal to an odd gate line and a second gate driving circuit which outputs a gate driving signal to an even gate line are operated separately. do.

Accordingly, by not connecting the first and second gate driving circuits dependently through the gate lines, it is possible to prevent the gate driving signals from being distorted by the line resistances generated in the gate lines, thereby, Operation characteristics can be improved.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating the first gate driving circuit illustrated in FIG. 1 in detail.

3 is a view illustrating the second gate driving circuit illustrated in FIG. 1 in detail.

4 is an input / output waveform diagram of the first and second gate driving circuits shown in FIGS. 2 and 3.

FIG. 5 is an internal circuit diagram of the first and second gate driving circuits shown in FIGS. 2 and 3.

6 is a diagram illustrating a dual liquid crystal display according to another exemplary embodiment of the present invention.

7 is a diagram illustrating a dual liquid crystal display according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 200: upper substrate

300: liquid crystal display panel 350: first gate driving circuit

360: second gate driving circuit 370: driving chip

400: flexible circuit board 500: liquid crystal display device

Claims (15)

In the gate driving circuit which is connected to a plurality of stages and outputs a gate driving signal output from each stage, Each stage, An input terminal for receiving a stage driving signal output from one of the previous stages; A clock terminal for keeping a low state longer than a high state and receiving one of a plurality of clocks having different phases; A control terminal for receiving a stage driving signal output from any one of the following stages; A first output terminal configured to output the clock received through the clock terminal as the gate driving signal; And And a second output terminal configured to output the clock received as the clock terminal as a stage driving signal. The method of claim 1, wherein the plurality of clocks, A first clock for maintaining a high state for one quarter of a period and a low state for three quarters of the period; And A first cycle having the same period as the first clock, delayed by one half of the first clock, held high for one quarter of the period, and held low for three quarters of the period; A gate drive circuit comprising two clocks. The gate driving circuit of claim 2, wherein the first clock is provided to an odd numbered stage of the plurality of stages, and the second clock is provided to an even numbered stage of the plurality of stages. 3. The gate driving circuit according to claim 2, wherein each stage outputs a gate driving signal delayed for one quarter of the period than the gate driving signal output from the previous stage. A display panel having a plurality of gate lines and a plurality of data lines; A first gate driving circuit including a plurality of first stages connected to each other and providing a first gate driving signal output from each of the first stages to an odd-numbered gate line with a blank section; A second gate driving circuit including a plurality of second stages connected to each other and providing a second gate driving signal output from each of the second stages to an even-numbered gate line corresponding to the blank period; And And a data driving circuit for outputting data signals to the plurality of data lines. The method of claim 5, wherein each of the first stage, An input terminal for receiving a stage driving signal output from one of the previous stages; A first clock that is held high for 1/4 hour of the period and low for 3/4 hours of the period, or 1/2 of the first clock while having the same period as the first clock. A clock terminal for receiving a clock of any one of a second clock which is delayed and is kept high for 1/4 hour of the period and kept low for 3/4 hours of the period; A control terminal for receiving a stage driving signal output from any one of the following stages; A first output terminal configured to output the clock received through the clock terminal as the gate driving signal; And And a second output terminal configured to output the clock received as the clock terminal as a stage driving signal. The display apparatus of claim 6, wherein the first clock is provided to an odd numbered stage of the plurality of first stages, and the second clock is provided to an even numbered stage of the plurality of first stages. 7. The display device according to claim 6, wherein each stage outputs a gate driving signal delayed for one quarter of the period than the gate driving signal output from the previous stage. The method of claim 6, wherein each of the second stage, An input terminal for receiving a stage driving signal output from one of the previous stages; A third clock that is held high for one quarter of a period and the same state as the third clock or the third clock that remains low for three quarters of the period, and is one half of the third clock. A clock terminal which is delayed and receives a clock of any one of a fourth clock which is held high for 1/4 hour of the period and kept low for 3/4 hour of the period; A control terminal for receiving a stage driving signal output from any one of the following stages; A first output terminal configured to output the clock received through the clock terminal as the gate driving signal; And And a second output terminal configured to output the clock received as the clock terminal as a stage driving signal. The display device of claim 9, wherein the third clock is delayed by a quarter period from the first clock and the fourth clock is delayed by a quarter period than the second clock. A display panel having a plurality of gate lines and a plurality of data lines; An odd-numbered gate line having a first gate driving signal output from each of the first stages having a first dummy section and a first active section adjacent to the first dummy section, the first gate section being composed of a plurality of first stages connected to each other independently A first gate driving circuit provided by; A second stage including a plurality of second stages connected to each other and having a second dummy section corresponding to the first active section and a second active section adjacent to the second dummy section and outputting from each of the second stages; A second gate driving circuit providing a gate driving signal to an even gate line; And And a data driving circuit configured to output data signals to the plurality of data lines corresponding to the first and second active periods. The method of claim 11, wherein each of the first stage, An input terminal for receiving a stage driving signal output from one of the previous stages; A clock terminal configured to receive a clock of any one of a first clock or a second clock having a phase inverted from the first clock; A control terminal for receiving a stage driving signal output from any one of the following stages; A first output terminal configured to output the clock received through the clock terminal as the gate driving signal; And And a second output terminal configured to output the clock received as the clock terminal as a stage driving signal. The display device of claim 12, wherein the first clock is provided to an odd numbered stage of the plurality of first stages, and the second clock is provided to an even numbered stage of the plurality of first stages. The method of claim 12, wherein each of the second stage, An input terminal for receiving a stage driving signal output from one of the previous stages; A clock terminal configured to receive a clock of any one of a third clock delayed by a quarter period from the first clock or a fourth clock having a phase inverted from the third clock; A control terminal for receiving a stage driving signal output from any one of the following stages; A first output terminal configured to output the clock received through the clock terminal as the gate driving signal; And And a second output terminal configured to output the clock received as the clock terminal as a stage driving signal. The display device of claim 14, wherein the third clock is provided to an odd numbered stage of the plurality of second stages, and the fourth clock is provided to an even numbered stage of the plurality of second stages.