KR20050113777A - Gate driver and display apparatus having the same - Google Patents

Abstract

In the gate driving circuit which consists of a plurality of stages and outputs a gate signal to a corresponding gate line, the buffer portion of each stage operates in response to the start signal or the output signal of the previous stage, and the charging portion charges the signal output from the buffer portion . The first driver outputs a clock signal as a gate signal in response to a signal charged in the charging unit, and the discharge unit discharges the charging unit in response to an output signal of the next stage. The second driver applies a ground voltage to the gate line in response to the output signal of the next stage. Here, the start signal provided to the buffer unit is kept high for a longer time period than the clock signal period. Therefore, distortion of the signal output from the gate driving circuit can be prevented.

Description

GATE DRIVER AND DISPLAY APPARATUS HAVING THE SAME

The present invention relates to a gate driving circuit and a display device having the same, and more particularly, to a gate driving circuit capable of preventing signal distortion and a display device having the same.

In general, a liquid crystal display device includes a liquid crystal display panel for displaying an image. The liquid crystal display panel includes a display area for displaying an image and a peripheral area adjacent to the display area. The display area includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel consists of a thin film transistor and a liquid crystal capacitor. The peripheral area includes a gate driver for outputting a gate signal to gate lines and a data driver for outputting a data signal to data lines.

The gate driver is simultaneously formed in the peripheral area of the liquid crystal display panel through the same process as the thin film transistor, and the data driver is formed in a chip shape and mounted on the peripheral area. The gate driver includes one shift register including a plurality of stages connected dependently to each other, and each stage is connected to a corresponding gate line to output a gate signal.

The stages are connected to each other in order to sequentially output gate signals to the gate lines. That is, the input terminal of the current stage is connected to the output terminal of the previous stage, and the output terminal of the next stage is connected to the control terminal of the current stage. At this time, since the previous stage does not exist in the input terminal of the first stage of the plurality of stages, a start signal for driving the first stage is provided.

As described above, since the signal output from the first stage is provided as an input signal of the next stage, if the signal output from the first stage is delayed for a predetermined time, the signal delay affects the signal output from the next stage. As a result, the signal distortion generated in the first stage continues until the last stage, whereby the signal output from the gate driver is totally distorted. In addition, the signal distortion may increase from the first stage to the last stage to cause a malfunction of the gate driving circuit.

Accordingly, it is an object of the present invention to provide a gate driving circuit for preventing signal distortion.

Further, another object of the present invention is to provide a display device having the above gate driving circuit.

The gate driving circuit according to an aspect of the present invention consists of a plurality of stages and outputs a gate signal to a corresponding gate line. Each of the stages includes a buffer unit, a charging unit, a first driver, a discharge unit, and a second driver.

The buffer unit operates in response to a start signal or an output signal of a previous stage, and the charging unit charges a signal output from the buffer unit. The first driver outputs a clock signal as the gate signal in response to a signal charged in the charging unit, and the discharge unit discharges the charging unit in response to an output signal of a next stage. The second driver applies a ground voltage to the gate line in response to an output signal of the next stage. Here, the start signal provided to the buffer unit is kept high for a period longer than the period of the clock signal.

According to another aspect of the present invention, a display device includes a display panel, a first gate driver, a second gate driver, and a data driver. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels to display an image. The first gate driver outputs a first gate signal to odd-numbered gate lines among the plurality of gate lines. The first gate driver outputs a first clock signal as the first gate signal in response to a first start signal or the second gate signal. The second gate driver outputs a second gate signal to even-numbered gate lines of the plurality of gate lines. The data driver outputs data signals to the plurality of data lines.

Here, the first gate driver outputs a first clock signal as the first gate signal in response to a start signal or the second gate signal, and the second gate driver outputs a second clock in response to the first gate signal. The signal is output as the second gate signal. The start signal provided to the first gate driver is held high for a period longer than a period of the first clock signal.

According to such a gate driving circuit and a display device having the same, a malfunction of the gate driving circuit is prevented by keeping the high period of the start signal provided to the first stage of the gate driving circuit longer than the period of the clock signal provided to the gate driving circuit. can do.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating the display area illustrated in FIG. 1 in detail.

Referring to FIG. 1, the display device 600 according to an exemplary embodiment may include a display area DA for displaying an image and first to third peripheral areas PA1 adjacent to the display area DA. And a display panel 100 having PA2 and PA3. The display area DA includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are perpendicular to each other.

In FIG. 2, only the first to fourth gate lines GL1, GL2, GL3, and GL4 of the plurality of gate lines are shown, and only the first and second data lines DL1 and DL2 of the plurality of data lines are shown. As illustrated in FIG. 2, a first pixel P1 and a third pixel P3 are connected to the first gate line GL1, and a second pixel P2 and a second gate line GL2. The fourth pixel P4 is connected. The first and second pixels P1 and P2 are commonly connected to the first data line DL1, and the third and fourth pixels P3 and P4 are common to the second data line DL2. Is connected.

The first pixel P1 includes a first transistor T1 and a first liquid crystal capacitor Clc1. The gate electrode of the first transistor Tr1 is connected to the first gate line GL1, the source electrode is connected to the first data line DL1, and the drain electrode is connected to the first liquid crystal capacitor Clc1. Connected. The second pixel P2 includes a second transistor Tr2 and a second liquid crystal capacitor Clc2. The gate electrode of the second transistor Tr2 is connected to the second gate line GL2, the source electrode is connected to the first data line DL1, and the drain electrode is connected to the second liquid crystal capacitor Clc2. Connected. That is, the first and second pixels P1 and P2 are commonly connected to the first data line DL1.

The third pixel P3 includes a third transistor Tr3 and a third liquid crystal capacitor Clc3. The gate electrode of the third transistor Tr3 is connected to the first gate line GL1, the source electrode is connected to the second data line DL2, and the drain electrode is connected to the third liquid crystal capacitor Clc3. Connected. The fourth pixel P4 includes a fourth transistor Tr4 and a fourth liquid crystal capacitor Clc4. The gate electrode of the fourth transistor Tr4 is connected to the second gate line GL2, the source electrode is connected to the second data line DL2, and the drain electrode is connected to the fourth liquid crystal capacitor Clc4. Connected. That is, the third and fourth pixels P3 and P4 are commonly connected to the second data line DL2.

Since the above structures are repeated in the third and fourth gate lines GL3 and GL4, the repeated description is omitted.

Referring back to FIG. 1, the first gate driver 200 is disposed in the first peripheral area PA1 to form an odd-numbered gate line GL1, GL3 ... among the plurality of gate lines formed in the display area DA. ) Is electrically connected. The second gate driver 300 is provided in the second peripheral area PA2 to be electrically connected to even-numbered gate lines GL2, GL4... Among the plurality of gate lines. The first and second gate drivers 200 and 300 are formed in the display panel 100 when a plurality of pixels are formed in the display area DA.

Meanwhile, the data driver 400 having a chip shape is mounted in the third peripheral area PA3. The data driver 400 is electrically connected to the data lines DL1, DL2..., Formed in the display area.

A flexible printed circuit board (FPC) 500 is attached to the third peripheral area PA3 of the display panel 100, and the flexible circuit board 500 is external to the display panel 100. Various signals are input from the device provided to the data driver 400 and provided to the data driver 400 and the first and second gate drivers 200 and 300. The various signals may include first and second control signals GC1 and GC2 for controlling driving of the first and second gate drivers 200 and 300, and third control signals for controlling operations of the data driver 400. Outputs (not shown).

The first gate driver 200 is driven by the first control signal GC1 to output a first gate signal to odd-numbered gate lines GL1, GL3..., In the display area DA. The second gate driver 300 is driven by the second control signal GC2 to output a second gate signal to even-numbered gate lines GL2, GL4..., In the display area DA. In addition, the data driver 400 outputs a data signal to the data lines DL1, DL2... In the display area DA in response to the third control signal.

Hereinafter, the first and second gate drivers will be described in detail with reference to FIG. 3.

3 is a diagram illustrating an internal configuration of the first and second gate drivers illustrated in FIG. 1.

Referring to FIG. 3, the first gate driver 200 is connected to odd-numbered gate lines GL1, GL3, GL5, and GL7 of a plurality of gate lines provided in the display area DA to receive a first gate signal. to provide. The second gate driver 300 is connected to second ends of even-numbered gate lines GL2, GL4, GL6, and GL8 of the plurality of gate lines to provide a second gate signal.

The first gate driver 200 includes a first shift register including a plurality of odd stages SRCO1, SRC02, SRC03, SRCO4... Each of the odd stages SRCO1 to SRCO4 includes an input terminal IN, an output terminal OUT, a control terminal CT, a first clock signal terminal CK1, and a ground voltage terminal VSS.

The second gate driver 300 includes a second shift register including a plurality of even stages SRCE1, SRCE2, SRCE3, SRCE4... Each of the even stages SRCE1 to SRCE4 includes an input terminal IN, an output terminal OUT, a control terminal CT, a second clock signal terminal CK2, and a ground voltage terminal VSS.

The output terminal OUT of each of the odd stages SRCO1 to SRCO4 is connected to a first end of the odd-numbered gate lines GL1, GL3, GL5, and GL7, so that the odd-numbered gate lines GL1, GL3, The first gate signal is sequentially output to GL5 and GL7. The output terminal OUT of each of the even stages SRCE1 to SRCE4 is connected to a second end of the even-numbered gate lines GL2, GL4, and GL6, and the even-numbered gate lines GL2, GL4, and GL6. ) Sequentially outputs the second gate signal.

Here, the first gate driver 200 and the second gate driver 300 are electrically connected to each other through gate lines. That is, the output signal of the first gate driver 200 is provided as an input signal of the second gate driver 300, and the output signal of the second gate driver 300 is of the first gate driver 200. It is provided as an input signal. For example, the output terminal OUT of the first odd stage SRCO1 is connected to the input terminal IN of the first even stage SRCE1, and the output terminal OUT of the first even stage SRCE1 is It is connected to the control terminal CT of the first order stage SRCO1 and the input terminal IN of the second order stage SRCO2. Therefore, the odd stages SRCO1 to SRCO4 of the first gate driver 200 and the even stages SRCE1 to SRCE4 of the second gate driver 300 are dependently connected to each other.

On the other hand, the start signal STV is provided to the input terminal IN of the first order stage SRCO1 among the plurality of order stages. In addition, a first clock signal CK is provided to the first clock signal terminal CK1 of each of the odd stages SRCO1 to SRCO4, and a ground voltage is provided to the ground voltage terminal VSS. The second clock signal terminal CK2 of each of the even stages SRCE1 to SRCE4 is provided with a second clock signal CKB having a phase inverted with the first clock signal CK.

4 is an internal circuit diagram of the first order stage shown in FIG. However, by explaining the internal configuration of the first odd stage, the description of the internal configuration of each stage of the first and second shift registers having a similar configuration is omitted.

Referring to FIG. 4, the first order stage SRCO1 includes a first driver 10, a second driver 20, a buffer unit 30, a charging unit 40, and a discharge unit 50.

The first driver 10 includes the first transistor T1, and the charger 40 includes one capacitor C1. A drain electrode of the first transistor T1 is connected to the first clock signal terminal CK1, a gate electrode is connected to one end of the capacitor C1 via a first node N1, and a source electrode is connected to the first electrode T1. It is connected to the other end of the capacitor C1 and the output terminal OUT. A first clock signal CK (shown in FIG. 3) is provided to the first clock signal terminal CK1.

The second driver 20 includes a second transistor T2, and the buffer unit 30 includes a third transistor T3. The drain electrode of the second transistor T2 is connected to the source electrode of the first transistor T1 and the other end of the capacitor C1, the gate electrode is connected to the control terminal CT, and the source electrode is the ground voltage. It is connected to the terminal VSS. The drain electrode and the gate electrode of the third transistor T3 are commonly connected to the input terminal IN, and the source electrode is connected to one end of the capacitor C1. The start signal STV is provided to the input terminal IN.

In the discharge unit 50, a drain electrode is connected to one end of the capacitor C1, a gate electrode is common to the gate electrode of the second transistor T2, and is connected to the control terminal CT. The fourth transistor T4 is connected to the ground voltage terminal VSS.

Hereinafter, the operation of the first odd stage SRCO1 will be described.

When the start signal STV is provided to the input terminal IN of the first stage stage SRCO1, the third transistor T3 is turned on to gradually increase the potential of the first node N1. As the potential of the first node N1 increases, charge is charged in the capacitor C1. When the charge charged in the capacitor C1 becomes equal to or greater than the threshold voltage of the first transistor T1, the first transistor T1 is turned on, and the output terminal OUT has the high state of the first clock signal ( CK) is output as the first gate signal.

Thereafter, the second gate signal output from the first even stage SRCE1 (shown in FIG. 3) is applied through the control terminal CT of the first odd stage SRCO1. The second transistor T2 is turned on by the second gate signal to apply a ground voltage to the output terminal OUT. In addition, the fourth transistor T4 is turned on by the second gate signal to discharge the charge charged in the capacitor C1 to turn off the first transistor T1. Thus, the ground voltage may be output to the output terminal OUT of the first odd stage SRCO1.

FIG. 5 is an input / output waveform diagram of the first and second shift registers shown in FIG. 2.

Referring to FIG. 5, the first clock signal CK, which is provided to the odd stages SRCO1 and SRCO2 (shown in FIG. 3), remains low for 1/2 of one period H, and the remaining 1 It remains high for a period of / 2. The second clock signal CKBO, which is provided to the even stages SRCE1 and SRCE2 (shown in FIG. 3), is delayed by a half cycle from the first clock signal CKO, so that the first clock signal CKO is delayed. It has an inverted phase.

The start signal STV provided to the input terminal IN (shown in FIG. 3) of the first order stage SRCO1 among the order stages is about 1.5 times one period 1H of the first clock signal CK. The state remains high for 1.5 h. The first odd stage SRCO1 outputs the first clock signal CK in a high state to the first gate line GL1 in response to the start signal STV.

At this time, the capacitor C1 of the first odd stage SRCO1 (shown in FIG. 4) is charged in response to the high period of the start signal STV. By increasing the high period of the start signal STV to 1.5H, the charging time of the capacitor C1 is sufficiently secured. That is, the start signal may sufficiently charge the capacitor C1 until the first gate signal is output from the first order stage SRCO1. As a result, delay of the first gate signal output from the first order stage SRCO1 may be prevented.

In FIG. 5, only the start signal STV is kept high for 1.5H. Although not shown in the figure, the start signal STV may be kept high for a time between 1H and 1.5H, and may be kept high for a time longer than 1.5H.

Next, a first gate signal output from the first odd stage SRCO1 is input to an input terminal IN of the first even stage SRCE1 among the even stages. The first even stage SRCE1 outputs the second clock signal CKB in a high state to the second gate line GL2 in response to the first gate signal from the first odd stage SRCO1.

Thereafter, the second gate signal output from the first even stay SRCE1 is input to the input terminal IN of the second odd stage SRCO2. The second odd stage SRCO2 outputs the first clock signal CK in a high state to the third gate line GL3 in response to the second gate signal from the first even stage SRCE1.

Next, the first gate signal output from the second odd stage SRCO2 is input to the input terminal IN of the second even stage SRCE2. The second even stage SRCE2 outputs the second clock signal CKB in a high state to the fourth gate line GL4 in response to the first gate signal from the second odd stage SRCO2.

As illustrated in FIG. 5, when the first and second gate signals are sequentially applied to the first and second gate lines G1 and GL2, the data driver 400 (shown in FIG. 1) may be multiple. The first and second data signals D1 and D2 are sequentially output to the data line. For example, the first and second pixels P1 and P2 (shown in FIG. 2) connected to the first and second gate lines GL1 and GL2 are commonly connected to the first data line DL1. The first data signal D1 applied to the first data line DL1 is provided to the first pixel P1 when the first gate signal is applied to the first gate line GL1. In addition, the second data signal D2 applied to the first data line DL1 is provided to the second pixel P2 when the second gate signal is applied to the second gate line GL2. .

Meanwhile, since each of the odd and even stages is dependently connected to each other, the delay of the first gate signal output from the first odd stage SRCO1 may affect the output of the subsequent stage. As described above, by increasing the high period of the start signal STV to 1.5H, the delay of the first gate signal output from the first odd stage SRCO1 is prevented, and further, the first and the first The distortion of the first and second gate signals output from each of the two gate drivers 200 and 300 (refer to FIG. 3) may be reduced as a whole.

According to the gate driving circuit and the display device having the same, the high period of the start signal provided to the first stage of the gate driving circuit is kept longer than the period of the clock signal provided to the gate driving circuit.

Therefore, by preventing the delay of the gate signal output from the first stage, it is possible to reduce the delay of the gate signal output from the later stage. As a result, malfunction of the gate driving circuit can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating the display area illustrated in FIG. 1 in detail.

3 is a diagram illustrating an internal configuration of the first and second gate drivers illustrated in FIG. 1.

4 is an internal circuit diagram of the first order stage shown in FIG.

FIG. 5 is an input / output waveform diagram of the first and second shift registers shown in FIG. 2.

* Description of the symbols for the main parts of the drawings *

100: display panel 200: first gate driver

300: second gate driver 400: data driver

500: flexible circuit board 600: display device

Claims (8)

A gate driving circuit comprising a plurality of stages and outputting a gate signal to a corresponding gate line, A buffer unit operable in response to a start signal or an output signal of a previous stage; A charging unit for charging a signal output from the buffer unit; A first driver outputting a clock signal as the gate signal in response to a signal charged in the charging unit; A discharge unit for discharging the charging unit in response to an output signal of a next stage; And A second driver configured to apply a ground voltage to the gate line in response to an output signal of the next stage, And the start signal maintains a high state for a time longer than a period of the clock signal. The gate driving circuit of claim 1, wherein the start signal is provided to a first stage of the plurality of stages to reduce a delay time of the gate signal output from the first stage. A display panel configured to display an image including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; A first gate driver configured to output a first gate signal to odd-numbered gate lines among the plurality of gate lines; A second gate driver configured to output a second gate signal to even-numbered gate lines of the plurality of gate lines; And A data driver for outputting data signals to the plurality of data lines; The first gate driver outputs a first clock signal as the first gate signal in response to a start signal or the second gate signal, and the second gate driver outputs a second clock signal in response to the first gate signal. Output as a second gate signal, wherein the start signal is held high for a period longer than a period of the first clock signal. The display panel of claim 3, wherein the display panel includes a plurality of pixel groups including first and second pixels. The first pixel is connected to a first gate line of a plurality of gate lines, and is connected to a first data line of a plurality of data lines, And the second pixel is connected to a second gate line adjacent to the first gate line and to the first data line. The display device of claim 4, wherein the data signal provided to the first data line is applied to the first pixel when the first gate driver outputs the first gate signal to the first gate line. And when the second gate driver outputs the second gate signal to the second gate line, the data signal provided to the first data line is applied to the second pixel. 4. The gate driving circuit of claim 3, wherein the first gate driver includes a plurality of odd stages, the second gate driver includes a plurality of even stages, and the odd stages and the even stages are connected to each other through the plurality of gate lines. Display device characterized in that connected in cascade. The method of claim 6, wherein each of the aod stage, A first buffer unit operating in response to the first start signal or the second gate signal output from the previous even stage; A first charging unit which charges a signal output from the first buffer unit; A first driver outputting the first clock signal as the first gate signal in response to a signal charged in the first charging unit; A first discharge unit configured to discharge the first charging unit in response to the second gate signal output from a next even stage; And And a second driver configured to apply a ground voltage to the odd-numbered gate lines in response to the second gate signal output from the next even stage. The method of claim 6, wherein each even stage, A second buffer unit operating in response to the first gate signal output from a previous odd stage; A second charger for charging a signal output from the second buffer unit; A third driver outputting the second clock signal as the second gate signal in response to a signal charged in the second charging unit; A second discharge unit configured to discharge the second charging unit in response to the first gate signal output from a next odd stage; And And a fourth driver configured to apply a ground voltage to the first gate line in response to the first gate signal output from the next stage.