JP4991775B2 - Gate drive circuit - Google Patents

Description

  The present invention relates to a drive circuit for an active matrix drive display device and an active matrix drive display device having the same, and more particularly to a drive circuit capable of improving display characteristics of the display device.

  The polycrystalline liquid crystal display device has the advantages that the device operation can be speeded up and the device can be driven at low power, but the manufacturing process is complicated. Accordingly, the polycrystalline liquid crystal display device is mainly applied to a small display device, and the amorphous liquid crystal display device is mainly applied to a large screen display device such as a notebook PC, an LCD monitor, and an HDTV.

  Recently, a technology for reducing the number of assembly steps by forming a gate driving circuit on the glass substrate of the liquid crystal display panel as in the case of the polycrystalline liquid crystal display device in the amorphous liquid crystal display device. We are striving to

  In general, the gate driving circuit includes a shift register and a wiring unit for providing various signals to the shift register. The wiring portion is composed of a plurality of wirings, and the layout of the wiring affects an output signal output from the gate driving circuit. That is, the current state is generated in which the output signals of the gate driving circuit are distorted due to the crossing of the wirings and the generated capacitance.

  Accordingly, the display characteristics of the liquid crystal display device are deteriorated.

  Further, as the amorphous liquid crystal display device is gradually increased in size or developed in a direction having a high resolution, the screen is driven by the conventional gate driving circuit integrated on the TFT substrate as follows. Problems occur.

  First, as the screen is enlarged or the resolution is increased, the number of gate lines formed on the TFT substrate of the amorphous liquid crystal display device and the number of pixels connected to the gate lines are increased accordingly. As the number of gate lines and pixels increases, the RC delay of the gate line increases as the distance from the gate driver increases, and the delay of the clock generated with a high level interval from the first gate line to the last gate line. Time will increase. For this reason, the gate output signal is distorted, which deteriorates the display characteristics of the liquid crystal display device.

  Further, a capacitance is formed between the wirings having the largest wiring width and arranged at the outermost contour. This further increases the RC delay of the liquid crystal display device. Therefore, there is a need for a structure that can transmit the gate drive signal to the gate line with a minimum delay.

  Accordingly, one feature of the present invention is to provide a driving circuit for an active matrix driving display device capable of improving display characteristics. Another feature of the present invention provides a liquid crystal display device having the driving circuit.

  A driving circuit of an active matrix driving display device according to one aspect of the present invention described above is as follows. Invention 1 is a gate driving circuit formed in a peripheral region of a liquid crystal display panel having a plurality of gate lines, and a plurality of stages are subordinate. And a shift register that sequentially supplies a drive signal for controlling the switching element output from each stage to the gate line through an output terminal, and a signal that is formed around the shift register and is sent to the shift register. And a wiring section composed of wiring for supply.

  The wiring unit includes a first clock wiring for providing a first clock signal to odd-numbered stages of the shift register, and a second clock signal having a phase inverted from that of the first clock signal for even-numbered stages of the shift register. A second clock wiring to be provided; a third clock wiring formed in a seal line region where no liquid crystal is present; and coupled to an end of the first clock wiring to provide the first clock signal to the odd-numbered stage; and a liquid crystal And a fourth clock wiring that is formed in the seal line region that is not present and is coupled to an end of the second clock wiring to provide the second clock signal to the even-numbered stage.

A second aspect of the present invention is the first aspect of the present invention, wherein one end located opposite to the input terminal of the first clock wiring is coupled to one end located opposite to the input terminal of the third clock wiring, and the input terminal of the second clock wiring One end of the fourth clock line is coupled to one end of the fourth clock line.
A third aspect of the present invention is the second aspect of the present invention, wherein the first clock wiring is arranged so as to be coupled with the third clock wiring in a second region where the last stage of the shift register is arranged, and the second clock wiring is The second region is arranged to be coupled to the fourth clock line.

A fourth aspect of the present invention is the first aspect, wherein the wiring section includes a first power supply voltage wiring for providing a first power supply voltage to each stage of the shift register, a second power supply voltage wiring for providing a second power supply voltage, and The apparatus further includes a start signal wiring for providing a start signal to the first stage.
The invention 5 is the invention 4, wherein the start signal wiring, the first power supply voltage wiring, the second clock wiring, the first clock wiring, the second power supply voltage wiring, the third clock wiring, and the fourth clock wiring. In this order, the shift registers are arranged close to each other.

According to a sixth aspect of the present invention, in the fourth aspect, the power supply voltage connection line is disposed between the second power supply voltage line and the shift register and connects the second power supply voltage line and the respective stages. Has a first width in a first region that does not cross the power supply voltage connection line, has a second width in a second region that crosses the power supply voltage connection line, and the second clock wiring is connected to the power supply voltage. The third region not crossing the connection line has a third width, the fourth region crossing the power supply voltage connection line has a fourth width, the second width is smaller than the first width, and the fourth width The width is smaller than the third width.
A seventh aspect of the present invention is the power supply voltage connection line according to the fourth aspect, further comprising a power supply voltage connection line disposed between the second power supply voltage line and the shift register and connecting the second power supply voltage line and the respective stages. Has a first width in a first region that does not cross the first clock wiring and the second clock wiring, and has a second width in a second region that crosses the first clock wiring and the second clock wiring, The second width is smaller than the first width.

1 is a diagram illustrating a liquid crystal display panel according to a first embodiment of the present invention. 2 is a diagram specifically illustrating a shift register constituting the gate driving circuit illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating a configuration of a drive stage illustrated in FIG. 2. FIG. 4 is a layout diagram of the drive stage illustrated in FIG. 3. FIG. 3 is a circuit diagram illustrating a configuration of a dummy stage illustrated in FIG. 2. 6 is a layout drawing of the dummy stage shown in FIG. When a dummy stage has the same structure as a drive stage, it is an output waveform diagram of the dummy stage. FIG. 6 is an output waveform diagram when a dummy stage is configured by the circuit shown in FIG. 5. FIG. 6 is a circuit diagram illustrating a configuration of a drive stage and a dummy stage according to a second embodiment of the present invention. 5 is a diagram illustrating a gate driving circuit according to a third embodiment of the present invention. FIG. 11 is an output waveform diagram of the gate driving circuit illustrated in FIG. 10. FIG. 11 is a layout diagram of a gate driving circuit specifically illustrating positions of third and fourth clock lines illustrated in FIG. 10. 6 is a layout diagram illustrating a connection relationship between first and third clock lines and a connection relationship between second and fourth clock lines. 6 is a diagram illustrating a wiring structure of a shift register according to a fourth embodiment of the present invention. FIG. 15 is a layout diagram illustrating a shift register having the wiring structure illustrated in FIG. 14. 7 is a layout diagram illustrating a wiring structure of a shift register according to a fifth embodiment of the present invention;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a view showing a liquid crystal display panel according to a first embodiment of the present invention, and FIG. 2 is a view specifically showing a shift register constituting the gate driving circuit shown in FIG.

  Referring to FIG. 1, a liquid crystal display panel 200 according to an embodiment of the present invention includes a TFT substrate 100, a color filter substrate (not shown), and a liquid crystal layer (between the TFT substrate 100 and the color filter substrate). (Not shown).

  The TFT substrate 100 is divided into a display area (DA) for displaying an image and a peripheral area (PA) adjacent to the display area (DA). The display area (DA) includes a plurality of pixels in a matrix form. It is equipped with. Specifically, each of the plurality of pixels includes a TFT 110 connected to a data line (DL) extended in a first direction and a gate line (GL) extended in a second direction orthogonal to the first direction, A pixel electrode 120 coupled to the TFT 110 is included.

  The resolution of the liquid crystal display device 200 is determined by the number of the plurality of pixels. If the plurality of pixels are mxn, the resolution is mxn. At this time, m data lines DL1 to DLm are provided on the TFT substrate 100, and n gate lines GL1 to GLn are provided.

  Meanwhile, a data driving circuit 140 is attached in a chip form to the first peripheral area PA where one end of the data lines DL1 to DLm is disposed, and one end of the gate lines GL1 to GLn is disposed. A gate driving circuit is integrated in the second peripheral area (PA). The gate driving circuit 130 is formed on the same process as the process of forming the plurality of pixels in the display area (DA).

The gate driving circuit 130 is composed of one shift register.
As shown in FIG. 2, the shift register 131 includes a plurality of stages (SRC1 to SRCn + 1) that are connected in a dependent manner. Specifically, the shift register 131 includes n driving stages (SRC1 to SRCn) and a dummy stage (SRCn + 1). Here, n is an even number.

  The n driving stages (SCR1 to SRCn) sequentially output gate driving signals to the n gate lines (GL1 to GLn). At this time, the output terminals (OUT) of the n driving stages (SRC1 to SRCn) are connected to the control terminal (CT) of the previous driving stage, respectively. The carry terminals (CR) of the n drive stages (SCR1 to SRCn) are connected to the input terminal (IN) of the next drive stage.

  As an exception, the input signal (IN) of the first driving stage (SCR1) is provided with a start signal (ST) instead of an output signal.

  Meanwhile, the input terminal (IN) of the dummy stage (SRCn + 1) is connected to the carry terminal (CR) of the nth driving stage (SRCn), and the output terminal (OUT) of the dummy stage (SRCn + 1) is connected to the nth driving stage (SRCn + 1). SRCn) is connected to the control terminal (CT). Therefore, the dummy stage (SCRn + 1) is controlled so that the nth driving stage (SRCn) can operate properly. The output terminal (OUT) of the dummy stage (SRCn + 1) is also coupled to the control terminal (CT) of the dummy stage (SRCn + 1). Therefore, the dummy stage (SRCn + 1) is controlled by the output signal of the dummy stage (SRCn + 1) itself.

  A wiring unit 132 for supplying various signals to the shift register 131 is provided around the shift register 131. Specifically, the wiring unit 132 includes a start signal wiring (STL), a first voltage wiring (VDDL), a first clock wiring (CKL), a second clock wiring (CKBL), and a second voltage wiring (VSSL). .

  The start signal line (STL) provides a start signal (ST) to the input terminal (IN) of the first drive stage (SRC1). Here, the start signal (ST) is a pulse motivated by a vertical motivation signal provided from an external graphic controller (not shown). The first voltage line VDDL is connected to the n driving stages SRC1 to SRCn and the dummy stage SRCn + 1 to supply a first voltage VDD, and the second voltage line VSSL is connected to the first voltage line VDDL. The n driving stages SRC1 to SRCn and the dummy stage SRCn + 1 are connected to supply a second voltage VSS.

  Meanwhile, the first clock line CK is connected to the odd-numbered driving stages SRC1 and SRC3 and the dummy stage SRCn + 1 among the n driving stages SRC1 to SRCn. The second clock wiring (CKBL) is inverted from the first clock signal (CK) to the even-numbered driving stages (SRC2, SRCn) among the n driving stages (SCR1 to SRCn). A second clock signal (CKB) having a phase is provided.

  Accordingly, since the output signals (OUT1 to OUTn) of the respective stages are sequentially generated with an active period (high state), the gate lines (GL to) corresponding to the active period of the output signals (OUT1 to OUTn) are generated. GL1) are selected sequentially.

  FIG. 3 is a circuit diagram showing the configuration of the drive stage shown in FIG. 2, and FIG. 4 is a layout drawing of the drive stage shown in FIG. However, in FIGS. 3 and 4, the configuration of the nth drive stage (SRCn) is representatively shown, and the other drive stages (SRC1 to SRCn−1) are the same as the nth drive stage (SRCn). Since it has a configuration, the description of the remaining drive stages (SRC1 to SRCn-1) is omitted.

  3 and 4, the nth driving stage (SRCn) of the shift register 131 includes a pull-up unit 113a, a pull-down unit 131b, a pull-up driving unit 131c, a pull-down driving unit 131d, and a carry output unit 131e. The nth driving stage (SRCn) includes an input terminal (IN), an output terminal (OUT), a control terminal (CT), a clock signal terminal (CKT), a second voltage terminal (VSST), and a first voltage terminal. (VDDT) and a carry output terminal (CR).

  The pull-up unit 131a includes a drain that receives an input of a clock signal (CK), a gate connected to a first node (N1), and a source connected to the output terminal (OUT). ).

  The pull-down unit 131b is a second NMOS transistor (NT2) having a drain connected to the output terminal (OUT), a gate connected to the second node (N2), and a source connected to the second terminal (VSST). Composed.

  The pull-up driver 131c includes a capacitor (C) and third to ninth NMOS transistors (NT3, NT4, NT5, NT6, NT7, NT8, NT9). The capacitor (C) is connected between the first node (N1) and the output terminal (OUT). The third NMOS transistor (NT3) has a drain connected to the first voltage terminal (VDDT), a gate connected to the input terminal (IN), and a source connected to the first node (N1). Have. The 4NMOS transistor NT4 has a drain and gate commonly connected to the first voltage terminal VDDT and a source connected to the gate of the fifth NMOS transistor NT5. Meanwhile, the fifth NMOS transistor NT5 has a drain connected to the first voltage terminal VDDT, a gate connected to the source of the fourth NMOS transistor NT4, and a source connected to the second node N2. It has the structure made.

  The sixth NMOS transistor NT6 has a drain connected to the source of the third NMOS transistor NT3, a gate connected to the second node, and a source connected to the second voltage terminal VSSVS. Have. The seventh NMOS transistor (NT7) has a gate connected to the second node (N2), a drain connected to the input terminal (IN), and a source connected to the second voltage terminal (VSST). It has a configuration. The eighth NMOS transistor (NT8) has a drain connected to the second node (N2), a gate connected to the input terminal (IN), and a source connected to the second voltage terminal (VSST). Have.

  Although not shown in the drawing, the source of the eighth NMOS transistor NT8 is connected to a third power supply voltage terminal to which a third power supply voltage having a voltage level lower than the second voltage VSS is provided. Can do. Meanwhile, the ninth NMOS transistor NT9 has a drain connected to the input terminal (IN), a gate connected to the control terminal (CT), and a source connected to the second voltage terminal (VSST). Have.

  The pull-down driver 131d includes tenth to thirteenth NMOS transistors (NT10, NT11, NT12, NT13). Specifically, the tenth NMOS transistor NT10 has a drain connected to the second node N2, a gate connected to the first node N1, and a source connected to the second voltage terminal VSSST. It has a connected configuration. The eleventh NMOS transistor NT11 has a drain connected to the source of the fourth NMOS transistor NT4, a gate connected to the first node N1, and a source connected to the second voltage terminal VSSST. Have a configuration. The twelfth NMOS transistor (NT12) has a drain connected to the first node (N1), a gate connected to the control terminal (CT), and a source connected to the second voltage terminal (VSST). It has a configuration. The thirteenth NMOS transistor NT13 has a drain connected to the output terminal OUT, a gate connected to the control terminal CT, and a source connected to the second voltage terminal VSSST. .

  Meanwhile, the carry output unit 131e has a drain connected to the clock signal terminal (CKT), a gate connected to the first node (N1), and a source connected to the carry output terminal (CR). A transistor (NT14) is included. Accordingly, the carry output unit 131e controls transmission of the corresponding clock signal among the first and second clock signals (CK / CKB) to the input terminal (IN) of the next driving stage.

  In the nth driving stage (SRCn), the third NMOS transistor NT3 is turned on by a carry signal (CR) of the previous stage provided to the input terminal (IN), so that the first node (N1) ) Is increased from the second voltage (VSS) to the first voltage (VDD). Thereafter, the tenth NMOS transistor NT10 is turned on by increasing the potentials of the fourth and fifth NMOS transistors NT4 and NT5 and the first node N1. As described above, the tenth NMOS transistor NT10 is operated, so that the potential of the second node N2 is lowered to the second voltage VSS. Accordingly, the second NMOS transistor NT2 is turned off.

  When the potential of the first node (N1) is increased, the first NMOS transistor (NT1) is turned on, so that the clock signal (CK) having an on voltage level is output to the output terminal (OUT). When the operation starts, the output voltage is bootstrapped to the capacitor C, and the gate voltage of the first NMOS transistor NT1 is increased to the first voltage VDD or higher. Accordingly, the first NMOS transistor NT1 is maintained in a complete (FULL) conduction state.

  Thereafter, when the output signal of the dummy stage raised to the ON voltage level is provided through the control terminal (CT) of the nth driving stage (SRCn), the twelfth and thirteenth NMOS transistors (NT12 and NT13) are turned on. Is done.

  When the twelfth NMOS transistor NT12 is turned on, the potential of the first node N1 is lowered from the first voltage VDD to the second voltage VSS. Accordingly, the tenth NMOS transistor NT10 is turned off. Accordingly, the second node N2 is raised from the second voltage VSS to the first voltage VDD through the fourth and fifth NMOS transistors NT4 and NT5.

  The dummy stage output signal provided from the control terminal CT turns on the 13 NMOS transistor NT13, and the 13th NMOS transistor NT13 turned on together with the second NMOS transistor NT2. The second voltage (VSS) is output to the output terminal (OUT).

  Meanwhile, the seventh to eighth NMOS transistors NT7 and NT8 are n−1th transistors provided to the input terminal (IN) in a state where the first voltage (VDD) is output to the output terminal (OUT). It is turned on when the output signal of the driving stage is changed to the ON voltage level.

  Specifically, when an output signal of the (n−1) th driving stage having an ON voltage level is provided to the input terminal (IN) in a state where the voltage (VSS) is output to the output terminal (OUT), While the eighth NMOS transistor NT8 is turned on, the output signal of the (n-1) th driving stage provided to the input terminal (IN) is discharged to the second voltage terminal (VSST).

  In addition, the ninth NMOS transistor NT9 is turned on by the output signal of the dummy stage provided through the control terminal CT, and is changed to an on-voltage level provided to the input terminal IN. The output signal of the first drive stage is discharged. Accordingly, the first NMOS transistor NT1 is prevented from being turned on.

  Meanwhile, even if the output signal of the dummy stage (SRCn + 1) applied through the control terminal (CT) is lowered to the off voltage level and the twelfth MNOS transistor (NT12) is turned off, the second node (N2) A state of being biased to the first voltage (VDD) is maintained through the fourth and fifth NMOS transistors NT4 and NT5. Accordingly, the second NMOS transistor NT2 maintains a turn-on state, and the second voltage VSS is continuously output to the output terminal OUT.

  FIG. 5 is a circuit diagram showing a configuration of the dummy stage shown in FIG. 2, and FIG. 6 is a layout drawing of the drive stage shown in FIG. However, in the description of FIGS. 5 and 6, the same reference numerals are assigned to the same components as those of the nth drive stage (SRCn) illustrated in FIGS. 3 and 4, and the corresponding descriptions are given. Is omitted.

  Referring to FIGS. 5 and 6, the dummy stage (SRCn + 1) includes a pull-up unit 131a, a pull-down unit 131b, a pull-up driving unit 131c, a pull-down driving unit 131f, and a carry output like the n-th driving stage (SRCn). Part 131e. Here, the dummy stage (SRCn + 1) has the same structure as the nth driving stage, but the control terminal (CT) of the dummy stage (SRCn + 1) has an output terminal (OUT) of the dummy stage (SRCn + 1). Are concatenated. Therefore, the dummy stage (SRCn + 1) is controlled by its own output signal.

  At this time, in order to maintain the output signal of the dummy stage (SRCn + 1) for a predetermined time, the size (NT12 ') of the transistor directly connected to the control terminal (CT) is changed.

  Specifically, the size of the twelfth NMOS transistor (NT12 ') is about 10 times smaller than the size of the twelfth transistor (NT12) of the nth driving stage in the dummy stir (SRCn + 1).

  The size of the transistor is the ratio (W / L) of its width (W) to the length (L) of the transistor channel. In general, since the length (L) is determined, the size of the transistor is determined by the channel width (W). Accordingly, the width (W) of the twelfth NMOS transistor (NT12 ′) used for the dummy stage (SRCn + 1) is greater than the width (W) of the twelfth NMOS transistor (NT12) used for the nth driving stage. About 10 times smaller. 4 and 6, the channel width of the twelfth NMOS transistor NT12 'shown in FIG. 6 is about 10 times smaller than the channel width of the twelfth MNOS transistor NT12 shown in FIG.

  That is, even if the output signal of the dummy stage (SRCn + 1) raised to the ON voltage level is fed back to the control terminal (CT) of the dummy stage (SRCn + 1), the size of the twelfth NMOS transistor (NT12 ′) A predetermined time is required until the twelfth NMOS transistor (NT12 ′) is turned on. Accordingly, since the tenth NMOS transistor NT10 is not immediately turned off, the second node N2 maintains the second voltage VSS for a predetermined time. As a result, the output terminal of the dummy stage (SRCn + 1) can maintain the on-voltage level for a predetermined time.

  When the twelfth NMOS transistor NT12 ′ is turned on after a predetermined time has elapsed, the tenth NMOS transistor N10 is turned off correspondingly, and the second node N2 is connected to the second voltage. The voltage is raised from (VSS) to the first voltage (VDD). When the potential of the second node (N2) is raised to the first voltage (VDD), the second NMOS transistor (NT2) is turned on and the output terminal (OUT) of the dummy stage (SRCn + 1) is connected to the output terminal (OUT). A second voltage (VSS) is output.

  The dummy stage (SRCn + 1) is configured by removing the thirteenth NMOS transistor (NT13) connected to the control terminal (CT) from the nth driving stage (SRCn). Referring to FIG. 6, it can be seen that the thirteenth NMOS transistor NT13 illustrated in FIG. 4 is removed. Accordingly, only the second NMOS transistor NT2 that is turned on outputs the second voltage VSS to the output terminal OUT, so that the second voltage VSS is applied to the output terminal OUT. The output time can be extended.

  FIG. 7 is an output waveform diagram of a dummy stage configured with the same structure as the drive stage. FIG. 8 is an output waveform diagram when the dummy stage is configured with the circuit diagram shown in FIG. However, in FIGS. 7 and 8, the X-axis is time (μs) and the Y-axis is voltage (V).

  Referring to FIG. 7, after the driving stage sequentially outputs the output signals (OUTn−1, OUTn) having the high period, the dummy stage (SRCn + 1) is operated to output the output signal (OUTn + 1). In FIG. 7, the dummy stage (SRCn + 1) has the same circuit diagram as the drive stage, and the output terminal of the dummy stage (SRCn + 1) is connected to the control terminal of the dummy stage (SRCn + 1). At this time, the output signal (OUTn + 1 ′) output from the output terminal of the dummy stage is changed to the on voltage level by the output signal (OUTn) of the nth driving stage, and at the same time, the output signal (OUTn + 1 ′) changed to the on voltage level. The output signal (OUTn + 1 ′) is provided to the control terminal of the nth driving stage and the control terminal of the dummy stage (SRCn + 1) itself.

  Thereafter, the output signal (OUTn + 1 ′) output from the output terminal of the dummy stage (SRCn + 1) according to its own output signal (OUTn + 1 ′) fed back through the control terminal of the dummy stage (SRCn + 1) Down to level. As a result, the output signal (OUTn + 1 ') of the dummy stage is lowered to the off voltage level immediately after the on voltage level cannot be maintained for a predetermined period. That is, the maximum voltage level of the dummy stage output signal (OUTn + 1 ') has a value far below the maximum voltage level of the driving stage output signal (OUTn).

  On the other hand, as shown in FIG. 8, when the dummy stage is configured with the circuit diagram shown in FIG. 5, the output signal (OUTn + 1 ') of the dummy stage appears stably.

  After the driving stage sequentially outputs output signals (OUTn-1, OUTn) having a high period, the dummy stage is operated. That is, the output signal (OUTn + 1) output from the output terminal of the dummy stage is changed to the on voltage level (or high level) by the output signal (OUTn) of the nth driving stage, and at the same time, the output voltage (OUTn + 1) is changed to the on voltage level. The changed output signal (OUTn + 1) is provided to the control terminal of the nth driving stage (SRCn) and the control terminal of the dummy stage (SRCn + 1) itself.

  Thereafter, even if the output signal (OUTn + 1) is provided through the control terminal of the dummy stage (SRCn + 1), since the size of the transistor connected to the dummy control terminal is small, the output signal is output from the output terminal of the dummy stage. A predetermined time was required until the output signal (OUTn + 1) was lowered to the off voltage level. Accordingly, the output signal (OUTn + 1) of the dummy stage can maintain the on-voltage level for a predetermined period.

  At this time, the output signal (OUTn) of the driving stage having the high period and the output signal (OUTn + 1) of the dummy stage having the ON voltage level are generated with substantially the same voltage. Accordingly, the nth driving stage (SRCn) can be stably driven by the output signal (OUTn + 1) of the dummy stage (SRCn + 1).

  FIG. 9 is a circuit diagram showing the configuration of the drive stage and dummy stage of the shift register according to the second embodiment of the present invention.

  Referring to FIG. 9, the shift register 133 according to the second embodiment of the present invention includes n driving stages (SRC1 to SRCn) and a dummy stage (SRCn + 1). Among the n driving stages (SRC1 to SRCn), the nth driving stage (SRCn) includes a pull-up unit 133a, a pull-down unit 133b, a pull driving unit 133c, and a pull-down driving unit 133d.

  The pull-up unit 133a is a first NMOS transistor (NT1a) that receives a clock signal (CK) through a drain, has a gate connected to the first node (N1a), and a source connected to an output terminal (OUTn). Composed.

  The pull-down unit 133b includes a second NMOS transistor (NT2a) having a drain connected to the output terminal (OUTn), a gate connected to the second node (N2a), and a source connected to the second voltage terminal (VSST). Is done.

  The pull-up driver 133c includes a capacitor (C) and third to fifth NMOS transistors (NT3a, NT4a, NT5a). The capacitor (C) is connected between the first node (N1a) and an output terminal (OUT). The third NMOS transistor NT3a has a drain connected to the first voltage terminal VDDT, a gate connected to the input terminal IN, and a source connected to the first node N1a. The fourth NMOS transistor NT4a has a drain connected to the first node N1a, a gate connected to the control terminal CT, and a source connected to the second voltage terminal VSSST. . The fifth NMOS transistor (NT5a) has a drain connected to the first node (N1a), a gate connected to the second node (N2a), and a source connected to the second voltage terminal (VSST). Have. The size of the third NMOS transistor NT3a is about twice as large as the size of the fifth NMOS transistor NT5a.

  The pull-down driver 133d includes sixth and seventh NMOS transistors (NT6a and NT7a). The sixth NMOS transistor NT6a has a drain and gate commonly connected to the first voltage terminal VDDT and a source connected to the second node N2a. The seventh NMOS transistor (NT7a) has a drain connected to the second node (N2a), a gate connected to the first node (N1a), and a source connected to the second voltage terminal (VSST). Have The size of the sixth NMOS transistor NT6a is about 16 times larger than the size of the seventh NMOS transistor NT7a.

  When the output signal of the (n-1) th driving stage is provided to the input terminal of the nth driving stage (SRCn), the seventh NMOS transistor (NT7a) is turned on. By operating the seventh NMOS transistor, the potential of the second node (N2a) is lowered from the first voltage (VDD) to the second voltage (VSS), thereby causing the second NMOS transistor (NT2a) to move. Turned off. Thereafter, even if the seventh NMOS transistor N7a is turned on, the size of the sixth NMOS transistor NT6a is about 16 times larger than the size of the seventh NMOS transistor NT7a. Is subsequently maintained at the second voltage (VSS).

  When the output signal (OUTn + 1) of the dummy stage (SRCn + 1) raised to the ON voltage level is provided through the control terminal (CT) of the nth driving stage (SRCn), the seventh NMOS transistor (NT7a) is turned off. Is done. Accordingly, the second node N2a is raised from the second voltage VSS to the first voltage VDD through the sixth NMOS transistor NT6a.

  Thereafter, the output signal (OUTn + 1) of the dummy stage (SRCn) applied through the control terminal (CT) of the nth driving stage (SRCn) is lowered to the off voltage level, and the fourth NMOS transistor (NT4a) is turned off. Even so, the second node N2a is biased to the first voltage VDD through the sixth NMOS transistor NT6a. Accordingly, the second NMOS transistor NT2a maintains a turn-on state, and the second voltage VSS is continuously output to the output terminal OUTn.

  Meanwhile, as shown in FIG. 9, the dummy stage (SRCn + 1) has a pull-up unit 133a, a pull-down unit 133b, a pull-up driving unit 133c ′, and a pull-down driving unit, like the n-th driving stage (SRCn). 133d is included. Here, the dummy stage (SRCn + 1) has the same structure as the nth driving stage (SRCn), but the control terminal (CT) of the dummy stage (SRCn + 1) has an output terminal of the dummy stage (SRCn + 1). (OUTn + 1) are connected. Therefore, the dummy stage (SRCn + 1) is controlled by the output signal of the dummy stage (SRCn + 1). At this time, in order to maintain the output signal of the dummy stage (SRCn + 1) having the ON voltage level for a predetermined time, the size of the transistor directly connected to the control terminal (CT) is changed.

  Specifically, the size of the fourth transistor (NT4a ') in the dummy stage (SRCn + 1) is about 10 times smaller than the size of the fourth NMOS transistor (NT4a) in the nth driving stage (SRCn). Therefore, after the high level output signal of the dummy stage (SRCn + 1) is fed back to the control signal (CT) of the dummy stage (SRCn + 1), the fourth NMOS transistor (NT4a ′) is not immediately turned off, and thus the seventh NMOS transistor (NT7a). ) Is not turned on immediately. The fourth NMOS transistor (NT4a ') is maintained at the second voltage (VSS) for a predetermined period. Therefore, the output terminal of the dummy stage (SRCn + 1) is maintained at a high voltage level for a predetermined period.

  That is, even if the output signal of the dummy stage (SRCn + 1) raised to the ON voltage level is provided through the control terminal (CT) of the dummy stage (SRCn + 1), the fourth NMOS transistor (NT4a ′) is turned on. Therefore, the seventh NMOS transistor NT7a is not immediately turned off. Therefore, the fourth node (N4) maintains the second voltage (VSS) for a predetermined time. Accordingly, the dummy stage (SRCn + 1) can maintain the on-voltage level for a predetermined time.

  When the fourth NMOS transistor NT4a ′ is turned on after a predetermined time has elapsed, the seventh NMOS transistor NT7a is turned off in response to the fourth NMOS transistor NT4a ′. The voltage is raised from two voltages (VSS) to the first voltage (VDD). When the potential of the fourth node (N4) is raised to the first voltage (VDD), the second NMOS transistor (NT2a) is turned on, and the output terminal (OUT) of the dummy stage (SRCn + 1) is connected to the first terminal (OUT). Two voltages (VSS) are output.

  Thus, the dummy stage (SRCn + 1) can be stably operated by connecting the control terminal (CT) of the dummy stage (SRCn + 1) to the output terminal (OUT + 1) of the dummy stage (SRCn + 1). . In addition, the gate driving circuit does not need a separate wiring provided from the outside in order to provide a control signal to the control terminal (CT) of the dummy stage (SRCn + 1), and thus may not be added.

  Accordingly, the addition of the additional wiring (not shown) prevents a situation in which various signals provided to the gate driving circuit are delayed due to the capacitance generated between the other wiring and the additional wiring. be able to.

  FIG. 10 is a diagram illustrating a gate driving circuit according to a third embodiment of the present invention, and FIG. 11 is an output waveform diagram of the gate driving circuit illustrated in FIG. Here, i is an even number smaller than n.

  Referring to FIG. 10, the gate driving circuit 150 according to the third embodiment of the present invention includes one shift register 151. The shift register 151 is divided into first and second groups (G1 and G2) including a plurality of driving stages. A wiring unit 152 for supplying various signals to the shift register 151 is provided around the shift register 151.

  Specifically, the wiring unit 152 includes a start signal line (STL), a first voltage line (VDDL), a first clock line (CKL1), a second clock line (CKBL1), a second voltage line (VSSL), 3 clock lines (CKL2) and a fourth clock line (CKBL2) are included.

  The first clock line (CKL1) is configured to supply a first clock signal to odd-numbered drive stages (SRC1, SRC3,..., SRCi-1) among the drive stages (SRC1 to SRCi-1) of the first group. (CK) is provided, and the third clock line (CKL2) is connected to the first clock signal (SRCi + 1) among the driving stages (SRCi to SRCn) of the second group (G2). CK). Meanwhile, the second clock line (CKBL1) is connected to the first clock signal (CK1) in the even-numbered drive stages (SRC2...) Among the drive stages (SRC1 to SRCi-1) of the first group (G1). ) And a second clock signal (CKB) having an inverted phase, and the fourth clock line (CKBL2) is an even-numbered one of the driving stages (SRCi to SRCn) of the second group (G2). The second clock signal CKB is provided to driving stages SRCi to SRCn.

  Accordingly, some of the n driving stages (SRC1 to SRCn) are provided by the first and second clock signals (CK, CKB) provided through the first and second clock lines (CKL1, CKBL1), respectively. Be operated. The other part is operated by the first and second clock signals (CK, CKB) provided through the third and fourth clock lines (CKL2, CKBL2), respectively. As a result, the delay time of the first and second clock signals (CK, CKB) generated with the ON voltage level section sequentially from the first gate line to the nth gate line is minimized, and each stage is set. It is possible to prevent the current output signal from being distorted.

  Meanwhile, the third and fourth clock wirings (CKL2, CKBL2) do not cross other wirings (VSSL, VDDL, STL, etc.) so as to be connected to the n driving stages (SRC1 to SRCn). One end of the third and fourth clock lines (CKL2, CKBL2) is coupled to one end of the first and second clock lines (CKL1, CKBL1) and connected to each of the n driving stages (SRC1 to SRCn). The

  Specifically, the first end of the third clock line (CKL2) to which the first clock signal (CK) is input and the first clock line (CKL1) to which the first clock signal (CK) is input. The first end is disposed at a close position. The first end of the second clock line (CKBL1) to which the second clock signal (CKB) is input and the first end of the fourth clock line (CKBL2) to which the second clock signal (CKB) is input. The ends are arranged at close positions. That is, the input terminals of the first to fourth clock signal lines (CKL1, CKBL1, CKL2, CKBL2) are positioned adjacent to the first driving stage (SRC1) of the n driving stages (SRC1 to SRCn). Be placed.

  At this time, the other second end of the first clock line (CKL1) is coupled to the other second end of the third clock line (CKL2), and the position to be coupled to the dummy stage (SRCn + 1). Adjacent position.

Therefore, the third and fourth clock lines (CKL2, CKBL2) are not directly connected to the shift register 151, and there is no portion that is crossed with other lines. Accordingly, the moving speed of the first and second clock signals (CK, CKB) through the third and fourth clock lines (CKL2, CKBL2) is changed through the first and second clock lines (CKL1, CKBL1). The moving speed of the first and second clock signals (CK, CKB) is faster.
In addition, the wiring portion 152 is disposed adjacent to the shift register 151 as the wiring width is narrower.

  Specifically, the start signal line (STL) is disposed at a position closest to the shift register 151, and then the first voltage line (VDDL) is adjacent to the start signal line (STL). Arranged. Second and first clock lines CK1 and CKBL1 are sequentially positioned outside the first voltage line VDDL. The second voltage line (VSSL) is formed in connection with the first clock line (CKL1). Meanwhile, the third clock line (CKL2) is disposed adjacent to the second voltage line (VSSL), and then the fourth clock line (CKBL2) is adjacent to the third clock line (CKL2). Be placed.

  The wiring part 152 is composed of various wirings arranged in this order, so that the display characteristics of the liquid crystal display device can be improved. That is, the closer to the shift register 151, the larger the total contact area between the wirings, and the larger the contact capacitance. Therefore, the wiring that is not greatly affected by the contact capacitance is disposed adjacent to the shift register 151. Thereby, the display characteristics of the liquid crystal display device can be improved.

  Referring to FIG. 11, the first and second clock signals (CK, CKB) are provided to the first group (G1) of the shift register 151 through the first and second wirings (CKL1, CKBL1). When a start signal (ST) is provided to the first driving stage (SRC1) of the first group (G1), the first driving stage (SRC1) of the first group (G1) receives the start signal (STC1). In response to the leading end of (ST), a high level interval of the first clock signal (CK) is generated in the first output signal (OUT1). Thereafter, in the second driving stage (SRC2), in response to the first output signal (OUT1) of the first driving stage (SRC1), the high-level section of the second clock signal (CKB) is the first level. Two output signals (OUT2) are generated.

  Meanwhile, when the first and second clock signals (CK, CKB) are provided to the second group (G2) of the shift register 151 through the third and fourth clock signal lines (CKL2, CKBL2), the first and second clock signals are provided. In the i-th drive stage (SRCi) that is the first drive stage of the second group (G2), the i-1th drive stage (SRCi-1) that is the last drive stage of the first group (G1). ) In response to the (i-1) th output signal (OUTi-1), a high level interval of the second clock signal (CKB) is generated in the ith output signal (OUTi). In the (i + 1) th driving stage (SRCi + 1), in response to the i-th output signal (OUTi), a high level interval of the first clock signal (CK) is generated in the i + 1-th output signal (OUTi + 1).

As described above, the first to nth output signals (OUT1 to OUTn) are sequentially generated at the output terminals (OUT) of the respective stages while having the high level section.
FIG. 12 is a design diagram of the gate driving circuit specifically showing the positions of the third and fourth clock lines shown in FIG. 10, and FIG. 13 shows the connection relationship between the first and third clock lines and the third clock line. FIG. 6 is a design diagram illustrating a connection relationship between second and fourth clock wirings.

  Referring to FIG. 12, on the outside of the shift register 151, a start signal line (STL), a first voltage line (VDDL), first and second clock lines (CKL1, CKBL1), a second voltage line (VSSL), Third and fourth clock lines (CKL2, CKBL2) are sequentially arranged. Each wiring is arranged adjacent to the shift register 151 as the wiring width is narrower. That is, the wiring width far from the shift register is set to be at least larger than or equal to the wiring width adjacent to the shift register. The closer to the shift register 151, the larger the total contact area between the wirings and the larger the contact capacitance. Therefore, the wirings that are not greatly affected by the capacitance are arranged adjacent to the shift register 151. .

  Specifically, the start signal line (STL) is disposed at a position closest to the shift register 151, and then the first voltage line (VDDL) is adjacent to the start signal line (STL). Be placed. The second and first clock lines (CKBL, CKBL1) are located outside the first voltage line (VDDL). Here, the second clock line (CKBL1) is disposed closer to the shift register 151 than the first clock line (CKL1). The second voltage line (VSSL) is formed adjacent to the first clock line (CKL1). Such a structure reduces a delay due to contact capacitance generated between the wiring and the connection line connecting the corresponding wiring to each stage (SRC1 to SRCn + 1).

  On the other hand, the third and fourth clock lines (CKL2, CKBL2) do not pass through other lines so as to be connected to the shift register 151. One end of the third and fourth clock lines (CKL2, CKBL2) is coupled to one end of the first and second clock lines (CKL1, CKBL1) and connected to the shift register 151. The four clock wirings (CKL2, CKBL2) are disposed at a position farther from the shift register 151 than the second voltage wiring (VSSL). In other words, it is arranged outside the second voltage wiring (VSSL).

  As shown in FIG. 12, the third and fourth clock lines (CKL 2 and CKBL 2) are formed in the seal line area (SA) of the TFT substrate 300. Specifically, the TFT substrate 300 includes a display area (DA) in which gate lines (not shown), data lines (not shown), and pixels (not shown) are formed, and the periphery of the display area (DA). Are divided into peripheral areas (PA).

  The peripheral area PA includes a gate driving area GA on which the shift register 151 and various wirings are formed, and a coupling member for connecting the TFT substrate to a color filter substrate (not shown), such as a sealant. (Not shown) is divided into the seal line area (SA) formed. The gate driving area (GA) and the seal line area (SA) are partially overlapped. That is, the seal line area (SA) is divided into a first area in which liquid crystal is present and a second area in which no liquid crystal is present, based on the center of the seal line area (SA). Here, the gate drive region (GA) includes the first region.

  Here, a part of the third and fourth clock wirings (CKL2, CKBL2) and the second voltage wiring (VSSL) are formed in the seal line region (SA), and the remainder of the second voltage wiring (VSSL). In part, the first clock line (CKL1), the second clock line (CKBL1), and the start signal line (STL) are formed in the gate driving region (GA).

  A part of the second voltage line (VSSL), the first and second clock lines (CKL1, CKBL1), the first voltage line (VDDL), and the start signal line (STL) have a portion in contact with the connection line. . Therefore, a part of the second voltage wiring (VSSL), the first and second clock wirings (CKL1, CKBL1), the first voltage wiring (VDDL), and the start signal wiring (STL) are in the seal line region (SA). When it is formed, a contact failure occurs due to a process of applying pressure at a high temperature to bond the TFT substrate 300 and the color filter substrate.

  A wiring having a portion in contact with the connection line is formed in the gate driving region (GA), and a wiring having no portion in contact with the connection line is formed in the seal line region (SA). Therefore, it is possible to prevent the overall size of the liquid crystal display device from being increased. Specifically, the remainder of the second voltage wiring (VSSL) and the third and fourth clock wirings (CKL2, CKBL2) do not have a portion to be coupled to the connection line, so that the seal line area (SA) May be formed.

  Therefore, the third and fourth clock lines (CKL2, CKBL2) are additionally formed in the peripheral area (PA), so that the phenomenon of increasing the size of the liquid crystal display device does not occur. In addition, since the third and fourth clock lines (SKL2, CKBL2) are formed in the seal line area (SA) where no liquid crystal exists, the capacitance of the third and fourth clock lines (CKL2, CKBL2) is increased. not exist. Therefore, the delay time of the first and second clock signals (CK, CKB) is much reduced compared to the first and second clock lines (CKL1, CKBL1).

  Referring to FIG. 13, one end of the first clock signal line (CKL1) is coupled to one end of the third clock line (CKL2), and one end of the second clock line (CKBL1) is connected to the fourth clock line (CKL1). Is coupled to one end of CKBL2). Accordingly, the third clock wiring (CKL2) provides the first clock signal (CK) to each stage of the shift register, and the fourth clock wiring (CKBL2) provides the second clock signal (CKBL2) to each stage. CKB).

  As shown in FIGS. 12 and 13, the third and fourth clock lines CKL2 and CKBL2 are not directly connected to the shift register 151, but are crossed with other lines. There is no part to be. Accordingly, the moving speed of the first and second clock signals (CK, CKB) through the third and fourth clock lines (CKL2, CKBL2) is the moving speed of the first and second clock lines (CKL1, CKBL1). Faster.

  Accordingly, a part of each stage (SRC1 to SRCn + 1) of the shift register 151 is operated by the first and second clock signals (CK, CKB) provided through the first and second clock lines (CKL1, CKBL1). A part of the remainder is operated by the first and second clock signals (CK, CKB) provided through the third and fourth clock lines (CKL2, CKBL2).

  As a result, the shift register 151 is minimized by minimizing the delay time of the first and second clock signals (CK, CKB) generated with a high level section sequentially from the first gate line to the last gate line. The delay distortion of the output signal output from can be removed.

  FIG. 14 is a diagram showing a wiring structure according to a fourth embodiment of the present invention, and FIG. 15 is a layout diagram specifically showing the wiring structure shown in FIG.

  Referring to FIGS. 14 and 15, a first voltage connection line (VSSLc) connecting the second voltage line (VSSL) and each stage is provided between a second voltage line (VSSL) and a shift register (not shown). ) Is arranged. Between the second voltage line (VSSL) and the shift register, first and second clock lines (CKL1, CKBL1) are disposed in parallel with the second voltage line (VSSL).

  The first voltage connection line (VSSLc) and the first and second clock lines (CKL1, CKBL1) are crossed. In addition, the first and second clock lines (CKL1, CKBL1) have a first width (W1) in a region that does not cross the first voltage connection line (VSSLc), and the first voltage connection line (VSSLc). ) Has a second width (W2) smaller than the first width (W1).

  Specifically, the first clock line (CKL1) has a first recess (C1) recessed inward from one side wall corresponding to a region crossing the second voltage connection line (VSSLc). A second recess (C2) is formed in the second clock line (CKBL1) corresponding to a region crossing the first voltage connection line (VSSLc).

  The first clock line (CKL1) includes first and second sidewalls 1401 and 1402 extending in a length direction, and the second clock line (CKBL1) extends in a length direction. And fourth side walls 1403 and 1404. The first and second clock lines (CKL1, CKBL1) are disposed such that the second sidewall 1402 and the third sidewall 1403 face each other. At this time, the first recess (C1) is formed in the first side wall 1401, and the second recess (C2) is formed in the fourth side wall 1404.

  14 and 15, a first clock signal connection line (CKLc) for providing a first clock signal to each stage is disposed between the first clock line (CKL1) and the shift register 151. A second clock signal connection line (CKBLc) for providing a second clock signal to each stage is disposed between the second clock line (CKBL1) and the shift register 151. The first clock signal connection line (CKLc) is in contact with the first clock line (CKL1) in the vicinity of the second side wall 1402 of the first clock line (CKL1), and the second clock signal connection line (CKBLc) is The second clock line (CKBL1) is in contact with the second clock line (CKBL1) in the vicinity of the third side wall 1403. The first and second recesses (C1, C2) may be formed at positions that do not overlap the contact portions of the first and second clock signal connection lines (CKLc, CKBLc).

  Accordingly, a capacitance generated in a section intersecting the first and second clock lines (CK1, CKB1) and the first voltage connection line (VSSLc) can be reduced. Accordingly, the delay time of the first and second clock signals (CK, CKB) applied to the shift register through the first and second clock lines (CKL1, CKBL1) can be shortened. Further, the delay time of the second voltage VSS applied through the second voltage connection line (VSSLc) can be shortened.

  Since the first and second clock lines (CKL1, CKBL1) are partially formed with a narrow width (W2), the first voltage connection line (VSSLc) and the first and second clock lines (CK1, CKB1) are formed. In the portion where) overlaps, resistance occurs. However, since the delay of the signal has a greater influence on the capacitance component than the resistance component, the delay time can ultimately be reduced.

Hereinafter, the RC delay that is changed by the capacitance component and the resistance component is presented through the experimental example and the comparative example presented in Table 1. In the experimental example, the first width (W1) of the first and second clock wirings (CKL1, CKBL1) is 70 μm, and the second width (W2) is 45 μm. In the comparative example, the first and second clock lines (CKL1, CKBL1) have a uniform thickness of 70 μm as a whole.

  As shown in Table 1, the first capacitance generated between the first and second clock lines (CKL1, CKBL1) and the first voltage connection line (VSSLc) in the comparative example is 385 pF. In the experimental example, the second capacitance generated between the first and second clock lines (CKL1, CKBL1) and the first voltage connection line (VSSLc) is 344.5 pF. That is, the second capacitance in the experimental example is reduced by about 10.5% from the first capacitance in the comparative example.

  On the other hand, in the comparative example, the first resistance in the first and second clock lines (CKL1, CKBL1) is 457Ω, and in the experimental example, the second resistance in the first and second clock lines (CKL1, CKBL1). Is 489Ω, and the second resistance in the experimental example is increased by about 7% from the first resistance. However, since the rate at which the second capacitance is reduced is larger than the rate at which the second resistance is increased in the experimental example, the RC delay is ultimately reduced.

FIG. 16 shows a wiring structure according to a fifth embodiment of the present invention.
Referring to FIG. 16, a first voltage connection line (VSSLc) for connecting the second voltage line (VSSL) and each stage is disposed between the second voltage line (VSSL) and a shift register (not shown). The Between the second voltage line (VSSL) and the shift register, first and second clock lines (CKL1, CKBL1) are arranged alongside the second voltage line (VSSL).

  Here, the first voltage connection line (VSSLc) is crossed with the first and second clock lines (CKL1, CKBL1). The first voltage connection line (VSSLc) includes a third recess (C3) that is recessed inward from one side wall corresponding to a region crossing the first clock line (CKL1). Corresponding to a region crossing the second clock wiring (CKBL1), there is a fourth recess (C4) recessed inward from one side wall. Accordingly, the second voltage connection line (VSSLc) has a third width (W3) in a region that does not cross the first and second clock lines (CKL1, CKBL1), and the first and second clock lines ( The region crossing CKL1 and CKBL1) has a fourth width (W4) smaller than the three widths (W3).

  As described above, the first voltage connection line (VSSLc) is formed to be narrow in a region crossing the first and second clock lines (CKL1, CKBL1), thereby the first and second clock lines. The capacitance formed between (CKL1, CKBL1) and the first voltage connection line (VSSLc) can be reduced. Accordingly, a delay time of the first and second clock signals applied through the first and second clock lines (CKL1, CKBL1) and a delay of the first power supply voltage applied through the first voltage connection line (VSSLc). Time can be reduced.

  In such a gate driving circuit, the output terminal of the dummy stage (SRCn + 1) is connected to the control terminal of the last driving stage (SRCn), and simultaneously connected to the control terminal of the dummy stage (SRCn + 1) itself, It is possible to prevent a phenomenon in which various signals provided to the gate driving circuit are delayed. Also, by changing the structure of the transistor connected to the control terminal from the dummy stage (SRCn + 1), the output signal of the dummy stage (SRCn + 1) is normally output, thereby improving the display characteristics of the liquid crystal display device. Can be made.

  In addition to the first and second clock wirings, the wiring unit additionally includes third and fourth clock wirings to which the first and second clocks (CK and CKB) are provided, respectively. It is possible to minimize the delay time of the first and second clocks generated with the high level section sequentially from the gate line to the last gate line, and further improve the display characteristics of the liquid crystal display device. .

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to the embodiments, and as long as it has ordinary knowledge in the technical field to which the present invention belongs, without departing from the spirit and spirit of the present invention, The present invention can be modified or changed.

100, 300 TFT substrate 110 TFT
120 pixel electrode 130 gate drive circuit 131, 133, 151 shift register 132, 152 wiring part 140 data drive circuit 150 gate drive circuit 200 liquid crystal display device 1401 first side wall 1402 second side wall 1403 third side wall 1404 fourth side wall

Claims (8)

In a gate driving circuit formed in a peripheral region of a liquid crystal display panel having a large number of gate lines,
A shift register that sequentially connects a plurality of driving stages to the gate line via an output terminal to control the switching element output from each driving stage, and a shift register;
A wiring portion formed around the shift register and configured by wiring for supplying a signal to the shift register,
The wiring part is
A first clock signal is disposed from one end to the other end along the plurality of drive stages of the shift register and is connected to the odd-numbered drive stage of the shift register, and provides a first clock signal to the odd-numbered drive stage. Clock wiring,
A plurality of drive stages of the shift register are arranged from one end to the other end and connected to the even-numbered drive stage of the shift register, and the even-numbered drive stage has a phase different from that of the first clock signal. A second clock wiring for providing a second clock signal;
It is formed in a seal line area where no liquid crystal exists, and is arranged from one end to the other end along a plurality of drive stages of the shift register and is not connected to the drive stage, and the other end is the first stage. A third clock line coupled to the other end of the one clock line for providing the first clock signal to the odd-numbered drive stage;
It is formed in the seal line region, is arranged from one end to the other end along a plurality of drive stages of the shift register, is not connected to the drive stage, and the other end is the second clock wiring A fourth clock line coupled to the other end of the first clock line and providing the second clock signal to the even-numbered drive stage;
The odd number connected to the first clock line by inputting the first clock signal from one end of the first clock line and inputting the first clock signal from one end of the third clock line. A part of the second driving stage is driven by the first clock signal input from one end of the first clock wiring, and the remainder of the odd numbered driving stage connected to the first clock wiring is the third clock stage. Driven by the first clock signal input from one end of the clock wiring and input from the other end of the first clock wiring connected to the other end of the third clock wiring;
The even number connected to the second clock line when the second clock signal is input from one end of the second clock line and the second clock signal is input from one end of the fourth clock line. A part of the second driving stage is driven by the second clock signal inputted from one end of the second clock wiring, and the remainder of the even-numbered driving stage connected to the second clock wiring is the fourth clock stage. A gate driving circuit, wherein the gate driving circuit is driven by the second clock signal inputted from one end of the clock wiring and inputted from the other end of the second clock wiring connected to the other end of the fourth clock wiring.   2. The gate driving circuit according to claim 1, wherein the second clock signal provided by the second clock wiring has a phase opposite to that of the first clock signal provided by the first clock wiring.   The first clock line is disposed to be coupled to the third clock line in a second region where the last driving stage of the shift register is disposed, and the second clock line is disposed in the second region. The gate driving circuit according to claim 1, wherein the gate driving circuit is arranged so as to be coupled to the fourth clock wiring. The wiring unit starts with a first power supply voltage line for providing a first power supply voltage to each drive stage of the shift register, a second power supply voltage line for providing a second power supply voltage, and a first drive stage. 2. The gate driving circuit according to claim 1, further comprising a start signal wiring for providing a signal.   Proximity to the shift register in the order of the start signal wiring, the first power supply voltage wiring, the second clock wiring, the first clock wiring, the second power supply voltage wiring, the third clock wiring, and the fourth clock wiring The gate driving circuit according to claim 4, wherein the gate driving circuit is arranged as described above. A power supply voltage connection line disposed between the second power supply voltage line and the shift register and connecting the second power supply voltage line and the driving stages;
The first clock wiring has a first width in a first region that does not cross the power supply voltage connection line, and a second width in a second region that crosses the power supply voltage connection line;
The second clock line has a third width in a third region that does not cross the power supply voltage connection line, a fourth width in a fourth region that crosses the power supply voltage connection line, and the second width is The gate drive circuit according to claim 4, wherein the gate width is smaller than the first width, and the fourth width is smaller than the third width. A power supply voltage connection line disposed between the second power supply voltage line and the shift register and connecting the second power supply voltage line and the driving stages;
The power supply voltage connection line has a first width in a first region that does not cross the first clock wiring and the second clock wiring, and a second width in a second region that crosses the first clock wiring and the second clock wiring. 5. The gate driving circuit according to claim 4, wherein the second width is smaller than the first width. The plurality of drive stages of the shift register are:
The output terminal of the previous stage drive stage is connected to the control terminal of the next stage drive stage next to the previous stage drive stage, so that they are connected to each other and formed on the respective pixels arranged in a matrix form. A drive signal for driving the plurality of switching elements to a plurality of drive signal lines connected to the switching elements is sequentially output through the output terminals of the respective drive stages,
The shift register is
A dummy output terminal for outputting a dummy output signal and a dummy control terminal are provided, and the dummy output terminal is connected to the control terminal of the final drive stage among the plurality of drive stages to turn on the final drive stage. And further comprising a dummy stage that is connected to the dummy output terminal and is turned on / off by the dummy output signal.
Each of the drive stages is
A pull-up unit that provides a drive signal of an on-voltage level capable of turning on the switching element to the output terminal;
A pull-down unit that provides a drive signal of an off-voltage level capable of turning off the switching element to the output terminal;
A driving unit that is driven by the driving signal of the on-voltage level to turn on the pull-down unit and turn off the pull-up unit and maintain the driving signal of the on-voltage level for a first predetermined time. ,
The dummy stage is
A dummy pull-up unit for providing a dummy output terminal with a dummy output signal of an on-voltage level capable of turning on the switching element;
A dummy pull-down unit for providing a dummy output terminal with a dummy output signal of an off-voltage level capable of turning off the switching element;
Dummy driving driven by the on-voltage level dummy output signal to turn on the dummy pull-down unit and turn off the dummy pull-up unit to maintain the on-voltage level dummy output signal for a second predetermined time. And comprising
The dummy driving unit of the dummy stage includes a first transistor connected to the dummy control terminal and for maintaining the dummy output signal at the on-voltage level for the second predetermined time period.
The driving unit of the final driving stage is connected to the control terminal that receives a dummy output signal from the dummy output terminal, and maintains a driving signal at the on-voltage level for a first predetermined time. Has two transistors,
Since the size of the first transistor is smaller than the size of the second transistor, the dummy output signal of the on-voltage level of the dummy stage is substantially the same as the maximum voltage level of the driving signal of the driving stage. The gate drive circuit according to claim 1, wherein the gate drive circuit is controlled to have a size.

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