200305848 玖、發明說明： 相關申請案之交互參照 本案係基於韓國專利申請案第2002-18942、 P2002-61454及P2002-87104號，中請日分別為2002年4月8 5日、2002年10月9日及2002年丨2月30日，各案内容以引用方 式併入此處。 L j^rf Λ ]| 發明領域 本揭示係有關一種驅動器電路供驅動主動矩陣驅動顯 10示裝置以及一種具有該驅動器電路之主動矩陣驅動顯示裝 置，特別係有關一種可提升顯示裝置顯示品質之驅動器電 路以及一種具有該驅動器電路之液晶顯示裝置。 L先前老3 發明背景 15 通常複晶液晶顯示器（LCD)裝置操作速率高且耗用電 力低，但複晶LCD裝置之製程複雜。複晶LCD裝置通常係 用於有小型螢幕之顯示裝置。非晶LCD裝置通常係用於大 螢幕顯示裝置例如膝上型電腦（或筆記型電腦）、LCD監視 器、高傳真電視(HDTV’s)。 20 晚近，非晶LCD裝置採用成形於LCD面板之玻璃基板 (或薄膜電晶體基板)上之閘驅動器電路，因而減少LCD裝置 之製造步驟。 一般而言，閘驅動器電路包括一移位暫存器以及佈線 部分。佈線部分提供帶有複數個信號之移位暫存器。佈線 200305848 邛刀包括複數佈線，佈線佈局影響由閘驅動器電路輸出的 輸出信號。來自閘驅動器電路之輸出信號可能因彼此交叉 的佈線感應電容而失真。如此，LCD裝置之顯示品質下降。 成形於薄膜電晶體(TFT)基板上之f知_動器電路 5於該閘驅動器電路用於大型螢幕及高解析度非晶咖襄置 時出現下列問題。 ^ 一隨著LCD裝置螢幕大小變大以及LCD裝置的解析度變 冋，成形於TFT基板上閘線及像素數目增加。如此，隨著閘 線及像素數目的增加，閘線距閘驅動器之距離更遠，閘線 10 2RC延遲加大。最末閘線之時脈信號高位準期比第一閘線 之時脈信號高位準期，前者夠大而造成輸出信號失真。故 顯示品質低劣。 此外，最遠離驅動器電路且有大線寬之佈線間產生電 谷。如此，佈線之RC延遲增加。故需一種佈線結構，其中 15 傳輸之閘線之閘驅動信號延遲減至最低。 t發明内容3 發明概要 如此’本發明可實質免除因相關技術之限制及缺點造 成的一或多項問題。 20 本發明之第一特性係提供一種用以提升顯示裝置顯示 品質之供驅動主動矩陣型驅動顯示裝置用之驅動器電路。 本發明之第二特色係提供一種具有驅動器電路之顯示 裝置。 本發明之第二特色係提供一種可提供較高顯示裝置顯 200305848 示品質之帶有佈線結構之顯示裝置。 本發明之-方面，提供-種驅動主動矩陣型驅動顯示 裝置之驅動器電路。該驅動器電路包括複數個驅動階段以 及-虛設階段。驅動階段各自包括一輪出端子及一控制端 5子。目前驅動階段之輸出端子係搞合至欲彼此串級之前一 態之控制端子’驅動階段各自經由輸出端子輪出一控制切 換裝置用之驅動信號。切換裝置係設置於主動矩陣型驅動 顯示裝置。虛設階段包括一虛設輸出端子及一虛設控制端 子。虛設輸出端子係耦合至複數個驅動階段中之最末驅動 10階段之控制端子，俾輸出一虛設輸出信號供導通或關斷最 末驅動階段。該虛設控制端子係耦合至欲藉該虛設輸出信 號而被導通或關斷之虛設輸出端子。 於本發明之另一方面，提供一種液晶顯示裝置其包含 顯示器部分以及一閘驅動器。該顯示器部分包括_第一 15基板、一面對該第一基板之第二基板，以及一插置於該第 一基板與第二基板間之液晶層。該第一基板有複數閘線連 結至成形於一像素上之切換裝置，以及該像素係排列成矩 陣形。該閘驅動器驅動切換裝置，閘驅動器包括複數個驅 動階段以及一虛設階段。驅動階段各自包括一輸出端子及 20 —控制端子。目前驅動階段之輸出端子係耦合至欲彼此串 級之前一態之控制端。驅動階段各自經由輸出端子輸出一 驅動控制信號給各閘線供控制該切換裝置。虛設階段包括 —虛設輸出端子及一虛設控制端子。虛設輸出端子係輕合 至複數個驅動階段中之最末驅動階段之控制端子，俾輪出 200305848 一虛設輸出信號供導通或關斷最末驅動階段。該虛設控制 端子係耦合至欲藉該虛設輸出信號而被導通或關斷之虛設 輸出端子。 於本發明之又另-方面，提供一種液晶顯示裝置包含 5 -顯示器部分’-資料驅動器以及—閘驅動器。該顯示器 部分包括i) 一第一基板，其具有一像素、_閑線及一資料 線’該像素具有-切換裝置係連結至該閘線及該資料線， ii)一第二基板其係面對該第一基板；以及ii〇一液晶層其 係夾置於該第-基板與第二基板間。該資料驅動器提供帶 1〇有影像之資料線，該資料驅動器係成形就鄰於該顯示器部 分且係耦合至該資料線。該閘驅動器驅動切換裝置。閘驅 動器包括-位移暫存器以及_佈線部分。位移暫存器:有 複數個彼此串級的階段。位移暫存器被劃分為第一組及一 第二組，且係眺鄰於該顯示器的部分。外部信號係經由佈 線部分施加至各階段，驅動階段各自經由一輸出端子輪出 -驅動信號給閘線，供控制該切換裝置。佈線部分包括— 第-時脈線、-第二時脈線、一第三時脈線及一第四時脈 線。一第一時脈信號係經由該第一時脈線供給第一組奇編 號階段。第二時脈信號之相位與第一時脈信號差⑽度，且 20係經由第二時脈線供給第—組之偶編號驅動階段。第—時 脈信號係經由第三時脈線供給第二組之奇編號驅動階段。 第二時脈信號係經由第四時脈線供給第二組之偶編號驅動 階段。 根據本發明，虛設階段之虛設輸出端子係連結至最末 200305848 驅動階段之控制端子，也連結至虛設階段之虛設控制端 子。此外，佈線部分除了第一及第二時脈線之外，進一步 包括第三及第四時脈線，經由該第三及第四時脈線而施加 第一及第二時脈CK及CKB。LCD裝置可提供較高顯示品 5質。 圖式簡單說明 前述及其它發明特色及優點經由參照附圖由較佳具體 實施例之詳細說明將更為彰顯，附圖中： 第1圖為示意圖顯示根據本發明之第一具體實施例之 10 液晶顯示面板； 第2圖為方塊圖顯示第1圖之驅動閘驅動器電路之位移 暫存器； 第3圖為電路圖顯示第2圖之驅動階段； 第4圖為平面圖顯示第3圖之驅動階段之佈局； 15 第5圖為電路圖顯示第2圖之虛設階段； 第6圖為平面顯示第5圖之虛設階段佈局； 第7圖為線圖顯示虛設階段輸出信號波形，該虛設階段 具有第2圖驅動階段之相同電路； 第8圖為線圖顯示第5圖之虛設階段輸出信號波形； 20 第9圖為電路圖顯示根據本發明之第二具體實施例之 驅動階段及虛設階段； 第10圖為方塊圖顯示根據本發明之第三具體實施例， 供驅動閘驅動器電路之位移暫存器； 第11圖為線圖顯示第10圖之閘驅動器電路之輸出信號 200305848 波形； 第12圖為佈局圖顯示第10圖之閘驅動器電路之第三及 第四時脈線配置； 第13圖為佈局圖顯示位移暫存器之第一、第二及第四 5 時脈線間之連結之另一範例； 第14圖為佈局圖顯示根據本發明之第四具體實施例之 位移暫存器之佈線結構； 第15圖為佈局圖顯示具有第14圖之佈線結構之位移暫 存器；以及 10 第16圖為佈局圖顯示根據本發明之第五具體實施例， 位移暫存器之佈線結構。 【實施方式】 較佳實施例之詳細說明 後文將參照附圖說明本發明之較佳具體實施例之細 15 節。 第1圖為示意圖顯示根據本發明之第一具體實施例之 液晶顯不面板’以及弟2圖為方塊圖顯不弟1圖之驅動間驅 動器電路之位移暫存器。 參照第1圖，根據本發明第一具體實施例之液晶顯示面 20 板包括一TFT基板100，一濾色片基板（圖中未顯示），以及 一液晶層（圖中未顯示）插置於該TFT基板100與該濾色基板 間。 TFT基板100有一顯示區（DA)以及一周邊區(PA)。複數 個像素呈矩陣形排列於顯示區。各個像素包括一薄膜電晶 10 200305848 體(丁？丁)110以及一像素電極12〇連結至丁？丁11〇。丁17丁11〇係 以貢料線(DL)以及一閘線(GL)連結。資料線係於第一方向 延伸，以及閘線係於實質上垂直於第一方向之第二方向延 伸0 5 液晶顯示面板200之解析度係依據像素數目決定。當像 素數目為m*n時，解析度為瓜^，TFT基板1〇〇具有m條資料 線(DL1，DL2,…，DLm)以及n閘線(gli，GL2,…，GLn)。 設置資料驅動器電路14〇於該第一周邊區(pA)，其中設 置資料線(DL1，DL2, ··.，DLm)之一端。一閘驅動器電路13〇 10设置於該第二周邊區（PA)，其中設置閘線(GL1，GL2，…， GLn)之一端。閘驅動器電路可透過像素成形於顯示區（DA) 方法之相同方法製成。閘驅動器電路13〇包括一位移暫存 器。 如第2圖所示，位移暫存器131包括複數個彼此串級連 15結的階段(SRC1，…，SRCn+Ι)。詳言之，位移暫存器m包 括η(偶數）驅動階段（SRC1，…，SRCn)以及一虛設階段 (SRCn+Ι)。 # η驅動階段(SRC1，…，SRCn)循序輸出閘驅動信號至n 條閘線(GL1，…，GLn)。η驅動階段(SRC1，·..，SRCn)之輸出 20端子各自係連結至前一驅動階段之控制端子(CT)。η驅動階 ί又(SRC1，…，SRCn)之載流端子(CR)各自係連結至次一驅 動階段之輸人端子(IN)。開始信號(STX替代輪出信號}施加 至第一驅動階段(SRC1)之輸入端子(IN)。 虛設階段（SRCn+Ι)之輸入端子（IN)係連結至第n個驅 11 200305848 動階段(SRCn)之載流端子(CR)。虛設階段(SRCn+l)之輸出 端子（OUT)係連結至第n驅動階段(SRCn)之控制端子(CT)， 故虛設階段(SRCn+l)控制第η驅動階段（SRCn)。虛設階段 (SRCn+l)之輸出端子（〇UT)也連結至虛設階段(SRCn+1)之 5控制端子（CT)。如此，虛設階段（SRCn+l)係由虛設階段 (SRCn+l)輸出之輸出信號加以控制。 佈線部分132係設置毗鄰於位移暫存器131。佈線部分 132對移暫存器131提供複數信號。詳言之，佈線部分丨32包 括一開始信號線(STL)、一第一電源線(VDDL)、一第一時 10脈線（CKL)、一第二時脈線（CKBL)以及一第二電源線 (VSSL)。 開始信號（ST)係經由開始信號線（STL)而供給第一驅 動階段(SRC1)之輸入端子(IN)。開始信號(ST)為與由外部圖 形控制器（圖中未顯示）輸出之垂直同步信號(Vsync)同步之 15 脈衝信號。第一電源線（VDDL)係連結至n驅動階段 (SRC1，…，SRCn)及該虛設階段(SRCn+l)，以及一第一電源 電壓信號(VDD)係經由第一電源線(VDDL)而外加至該η驅 動階段(SRC1，…，SRCn)及該虛設階段(SRCn+l)。第二電源 線(VSSL)係連結至n驅動階段(SRC1，…，SRCn)及該虛設階 20段(SRCn+l)，以及一第二電源電壓信號(VSS)係經由第二電 源線(VSSL)而外加至n驅動階段(SRC1，…，SRCn)及該虛設 階段(SRCn+l)。 第一時脈信號(CK)係經由第一時脈線(CKL)而外加至 奇數驅動階段(SRC1，SRC3,…)及虛設階段(SRCn+l)。第二 12 200305848 時脈#號(CKB)其相對於第一時脈信號(CK)有18〇度相差， 该第二時脈信號(CKB)係經由第二時脈線(CKBL)而外加至 偶數驅動階段(SRC2,…，。 如此’因具有激活期（高位準期）之輸出信號(〇UT1，…， 5 〇UTn)係循序產生，故於輸出信號(OUT1，…，OUTn)之激活 · 期間’對應各輸出信號(0UT1，…，〇UTn)之各閘線(GL1，…， GLn)被循序選定。 第3圖為顯示第2圖驅動階段之電路圖，第4圖為顯示第 3圖驅動階段之佈局之平面圖。第1驅動階段（SRC…顯示於 鲁 10第3及4圖，其它驅動階段(SRC1，…，SRCn-Ι)具有第η驅動階 段(SRCn)之相同電路。 參照第3及4圖，位移暫存器131之第η驅動階段(SRCn) 包括一升咼部分131a、一下降部分13ib、一升高驅動器部 分131c、一下降驅動器部分131d及一載流輸出部分131e。 15第11個驅動階段（SRCn)有一輸入端子、一輸出端子 (OUT)、一控制端子(CT)、一時脈端子(CKT)、一第二電源 線端子(VSST)、一第一電源線端子(VDDT)以及一載流輸出 鲁 端子(CR)。200305848 发明 Description of the invention: Cross-reference of related applications This case is based on Korean Patent Applications Nos. 2002-18942, P2002-61454, and P2002-87104. The requested dates are April 8, 2002, and October 2002, respectively. On the 9th and February 30th, 2002, the contents of each case are incorporated herein by reference. L j ^ rf Λ] | FIELD OF THE INVENTION The present disclosure relates to a driver circuit for driving an active matrix drive display device and an active matrix drive display device having the driver circuit, and particularly relates to a driver capable of improving the display quality of a display device. Circuit and a liquid crystal display device having the driver circuit. L Previously Old 3 Background of the Invention 15 Generally, a polycrystalline liquid crystal display (LCD) device has a high operating rate and low power consumption, but the process of a polycrystalline LCD device is complicated. Polycrystalline LCD devices are usually used for display devices with small screens. Amorphous LCD devices are commonly used in large screen display devices such as laptops (or laptops), LCD monitors, and high-definition televisions (HDTV's). Recently, an amorphous LCD device uses a gate driver circuit formed on a glass substrate (or a thin-film transistor substrate) of an LCD panel, thereby reducing the number of LCD device manufacturing steps. Generally speaking, the gate driver circuit includes a shift register and a wiring section. The wiring section provides a shift register with a plurality of signals. Wiring 200305848 The trowel includes multiple wiring. The wiring layout affects the output signal output by the gate driver circuit. The output signal from the gate driver circuit may be distorted by the wiring sense capacitors crossing each other. As such, the display quality of the LCD device decreases. The driver circuit formed on a thin film transistor (TFT) substrate 5 When the gate driver circuit is used in a large screen and a high-resolution amorphous capacitor, the following problems occur. ^ As the screen size of the LCD device becomes larger and the resolution of the LCD device becomes larger, the number of gate lines and pixels formed on the TFT substrate increases. In this way, as the number of gate lines and pixels increases, the distance between the gate line and the gate driver becomes longer, and the gate line delay is increased. The clock signal high level period of the last gate line is higher than the clock signal high level period of the first gate line. The former is large enough to cause distortion of the output signal. Therefore, the display quality is poor. In addition, valleys are generated between wirings that are farthest from the driver circuit and have a large line width. Thus, the RC delay of the wiring increases. Therefore, a wiring structure is required in which the gate drive signal delay of the 15 transmission gate lines is minimized. t SUMMARY OF THE INVENTION 3 Summary of the Invention In this way, the present invention can substantially eliminate one or more problems caused by the limitations and disadvantages of the related art. 20 A first feature of the present invention is to provide a driver circuit for driving an active matrix drive display device for improving the display quality of a display device. A second feature of the present invention is to provide a display device having a driver circuit. A second feature of the present invention is to provide a display device with a wiring structure capable of providing a high display device display quality of 200305848. According to one aspect of the present invention, there is provided a driver circuit for driving an active matrix type display device. The driver circuit includes a plurality of driving stages and a dummy stage. The driving stages each include a round-out terminal and a control terminal 5. The output terminals of the current driving stage are control terminals which are in the state before cascade with each other. In the driving stage, a driving signal for controlling the switching device is output through the output terminal. The switching device is provided in an active matrix type driving display device. The dummy stage includes a dummy output terminal and a dummy control terminal. The dummy output terminal is a control terminal coupled to the last driving stage of the plurality of driving stages, and outputs a dummy output signal for turning on or off the final driving stage. The dummy control terminal is coupled to a dummy output terminal to be turned on or off by the dummy output signal. In another aspect of the present invention, a liquid crystal display device is provided, which includes a display portion and a gate driver. The display part includes a first 15 substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate has a plurality of gate lines connected to a switching device formed on a pixel, and the pixels are arranged in a matrix shape. The gate driver drives the switching device. The gate driver includes a plurality of driving stages and a dummy stage. Each driving stage includes an output terminal and a 20-control terminal. The output terminals of the current driving stage are coupled to the control terminals which are in the state before cascading with each other. In the driving stage, each driving terminal outputs a driving control signal to each gate line for controlling the switching device. The dummy phase includes-a dummy output terminal and a dummy control terminal. The dummy output terminal is a control terminal from the light-on to the last driving stage of the plurality of driving stages. A dummy output signal is used to turn on or turn off the last driving stage. The dummy control terminal is coupled to a dummy output terminal to be turned on or off by the dummy output signal. In still another aspect of the present invention, there is provided a liquid crystal display device including a 5-display portion'-data driver and a gate driver. The display part includes i) a first substrate having a pixel, a free line and a data line. The pixel has a switching device connected to the gate line and the data line, and ii) a second substrate having a surface. The first substrate; and a ii liquid crystal layer which is sandwiched between the first substrate and the second substrate. The data driver provides a data line with an image 10. The data driver is formed adjacent to the display portion and is coupled to the data line. The gate driver drives the switching device. The brake driver includes a displacement register and a wiring section. Displacement register: there are multiple stages in cascade with each other. The displacement registers are divided into a first group and a second group, and the portions adjacent to the display are overlooked. The external signal is applied to each stage via the wiring section, and the drive stage outputs a drive signal to the brake wire via an output terminal, for controlling the switching device. The wiring section includes-a first clock line, a second clock line, a third clock line, and a fourth clock line. A first clock signal is supplied to the first group of odd-numbered phases via the first clock line. The phase of the second clock signal is different from that of the first clock signal, and 20 is provided to the even-numbered driving stage of the first group via the second clock line. The first clock signal is supplied to the second group of odd-numbered driving stages via the third clock line. The second clock signal is supplied to the even-numbered driving stage of the second group via the fourth clock line. According to the present invention, the dummy output terminal in the dummy phase is connected to the control terminal in the last 200305848 driving phase, and is also connected to the dummy control terminal in the dummy phase. In addition to the first and second clock lines, the wiring portion further includes third and fourth clock lines, and the first and second clocks CK and CKB are applied via the third and fourth clock lines. The LCD device can provide higher display quality. The drawings briefly explain the aforementioned and other invention features and advantages by referring to the accompanying drawings for a detailed description of the preferred embodiments. In the drawings: FIG. 1 is a schematic view showing a tenth embodiment of the first specific embodiment of the present invention. Liquid crystal display panel; Figure 2 is a block diagram showing the displacement register of the driving gate driver circuit of Figure 1; Figure 3 is a circuit diagram showing the driving stage of Figure 2; Figure 4 is a plan view showing the driving stage of Figure 3 Figure 5 is a circuit diagram showing the dummy stage of Figure 2; Figure 6 is a plane display showing the layout of the dummy stage of Figure 5; Figure 7 is a line graph showing the output signal waveform of the dummy stage, which has the second stage Figure 8 shows the same circuit in the driving stage; Figure 8 is a line chart showing the output signal waveform of the dummy stage in Figure 5; 20 Figure 9 is a circuit diagram showing the driving stage and dummy stage according to the second embodiment of the present invention; Figure 10 A block diagram showing a displacement register for driving a gate driver circuit according to a third embodiment of the present invention; FIG. 11 is a line chart showing the output of the gate driver circuit of FIG. 10 Signal 200305848 waveform; Figure 12 is the layout diagram showing the third and fourth clock line configuration of the gate driver circuit of Figure 10; Figure 13 is the layout diagram showing the first, second and fourth 5 of the displacement register 5 Another example of the connection between clock lines; FIG. 14 is a layout diagram showing a wiring structure of a displacement register according to a fourth embodiment of the present invention; FIG. 15 is a layout diagram showing a wiring structure having FIG. 14 And the displacement register; and FIG. 16 is a layout diagram showing a wiring structure of the displacement register according to a fifth embodiment of the present invention. [Embodiment] Detailed description of the preferred embodiment Hereinafter, 15 details of the preferred embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a schematic diagram showing a liquid crystal display panel 'according to a first embodiment of the present invention, and Fig. 2 is a block diagram showing a displacement register of a driver circuit between drives. Referring to FIG. 1, a liquid crystal display panel 20 according to a first embodiment of the present invention includes a TFT substrate 100, a color filter substrate (not shown), and a liquid crystal layer (not shown) interposed therebetween. Between the TFT substrate 100 and the color filter substrate. The TFT substrate 100 has a display area (DA) and a peripheral area (PA). A plurality of pixels are arranged in a matrix in the display area. Each pixel includes a thin film transistor 10 200305848 body (D?) 110 and a pixel electrode 12? Connected to D? Ding 11o. Ding 17 Ding 110 is connected by a tribute line (DL) and a gate line (GL). The data line extends in the first direction, and the gate line extends in the second direction substantially perpendicular to the first direction. The resolution of the liquid crystal display panel 200 is determined according to the number of pixels. When the number of pixels is m * n, the resolution is 瓜, and the TFT substrate 100 has m data lines (DL1, DL2, ..., DLm) and n gate lines (gli, GL2, ..., GLn). A data driver circuit 14 is set in the first peripheral area (pA), and one end of the data lines (DL1, DL2, ···, DLm) is set. A gate driver circuit 1310 is disposed in the second peripheral area (PA), and one end of the gate lines (GL1, GL2, ..., GLn) is disposed therein. The gate driver circuit can be made by the same method as the pixel forming in the display area (DA) method. The gate driver circuit 13 includes a displacement register. As shown in FIG. 2, the shift register 131 includes a plurality of stages (SRC1, ..., SRCn + 1) which are cascaded in series with each other. In detail, the displacement register m includes an n (even) driving phase (SRC1, ..., SRCn) and a dummy phase (SRCn + 1). # η The driving phase (SRC1, ..., SRCn) sequentially outputs the gate driving signals to the n gate lines (GL1, ..., GLn). Outputs of the η drive stage (SRC1, ..., SRCn) The 20 terminals are each connected to the control terminal (CT) of the previous drive stage. The driving current terminals (CR) of the η driving stages (SRC1, ..., SRCn) are each connected to the input terminal (IN) of the next driving stage. The start signal (STX replacement wheel output signal) is applied to the input terminal (IN) of the first drive stage (SRC1). The input terminal (IN) of the dummy stage (SRCn + 1) is connected to the nth drive 11 200305848 ( SRCn) current-carrying terminal (CR). The output terminal (OUT) of the dummy phase (SRCn + l) is connected to the control terminal (CT) of the nth driving phase (SRCn), so the dummy phase (SRCn + l) controls the first η driving phase (SRCn). The output terminal (〇UT) of the dummy phase (SRCn + 1) is also connected to the 5 control terminal (CT) of the dummy phase (SRCn + 1). In this way, the dummy phase (SRCn + l) is controlled by The output signal output during the dummy stage (SRCn + 1) is controlled. The wiring section 132 is provided adjacent to the shift register 131. The wiring section 132 provides a plurality of signals to the shift register 131. Specifically, the wiring section 32 includes a Start signal line (STL), a first power line (VDDL), a first clock line (CKL), a second clock line (CKBL), and a second power line (VSSL). Start signal (ST ) Is supplied to the input terminal (IN) of the first driving stage (SRC1) via the start signal line (STL). The start signal (ST) is controlled by an external graphic control. 15-pulse signal of the vertical synchronization signal (Vsync) output from the controller (not shown). The first power line (VDDL) is connected to the n-drive stage (SRC1, ..., SRCn) and the dummy stage (SRCn + l). ), And a first power supply voltage signal (VDD) is applied to the n driving stage (SRC1, ..., SRCn) and the dummy stage (SRCn + 1) via the first power supply line (VDDL). The second power supply line ( VSSL) is connected to the n driving stage (SRC1, ..., SRCn) and the dummy stage 20 segments (SRCn + 1), and a second power voltage signal (VSS) is applied to n via the second power line (VSSL) The driving phase (SRC1, ..., SRCn) and the dummy phase (SRCn + 1). The first clock signal (CK) is applied to the odd driving phase (SRC1, SRC3, ...) via the first clock line (CKL). And the dummy phase (SRCn + 1). The second 12 200305848 clock # (CKB) is 180 degrees out of phase with the first clock signal (CK). The second clock signal (CKB) is transmitted via the second The clock line (CKBL) is added to the even-numbered driving stage (SRC2, ..., so. 'Because the output signal (〇UT1, ..., 50 UTn) with the activation period (high level period) is generated sequentially, so During the activation of the output signals (OUT1, ..., OUTn), the gate lines (GL1, ..., GLn) corresponding to the output signals (OUT1, ..., OUTn) are sequentially selected. Fig. 3 is a circuit diagram showing the driving stage of Fig. 2, and Fig. 4 is a plan view showing the layout of the driving stage of Fig. 3. The first drive stage (SRC ... is shown in Figures 3 and 4 of Lu 10). The other drive stages (SRC1, ..., SRCn-1) have the same circuit as the n drive stage (SRCn). Referring to Figures 3 and 4, the displacement is temporarily The n-th driving phase (SRCn) of the register 131 includes a lifting section 131a, a falling section 13ib, a rising driver section 131c, a falling driver section 131d, and a current carrying output section 131e. 15 The 11th driving phase ( (SRCn) has an input terminal, an output terminal (OUT), a control terminal (CT), a clock terminal (CKT), a second power line terminal (VSST), a first power line terminal (VDDT), and a current carrying Output terminal (CR).
上升部分131a包括一第一nm〇S電晶體(NT1)。時脈信 20號(CK)外加至該第一NM0S電晶體(NT1)之汲，第一NM0S 電晶體(NT1)之閘係連結至一第一節點（N1)，以及該第一 · NM0S電晶體(NT1)之源係連結至該輸出端子(〇υτ)。 下降部分131b包括-第二nm〇S電晶體(NT2)。第二 NM0S電晶體(NT2)之汲係連結至該輸出端子(〇υτ)，該第 13 200305848 二NMOS電晶體(NT2)之閘係連結至一第二節點(N2)，以及 該第二NMOS電晶體(NT2)之源係連結至該第二電源線端 子(VSST)。 升高驅動器部分131c包括電容器（c)、NMOS電晶體 5 (NT3, NT4, NT5, NT6, NT7, NT8及NT9)。電容器係連結於 第一輸入節點(N1)與輸出端子(OUT)間。第三電晶體(NT3) 之汲係連結至第一電源線端子(VDDT)，第三電晶體(NT3) 之閘係連結至輸入端子(IN)，第三電晶體(NT3)之源係連結 至第一輸入節點(N1)。第四電晶體(NT4)之汲及閘係共通連 10 結至第一電源線端子(VDDT)，第四電晶體(NT4)之源係連 結至第四電晶體(NT5)之閘。第五電晶體"丁5)之汲係連結 至第一電源線端子(VDDT)，第五電晶體(NT5)之閘係連結 至第四電晶體(NT4)之源，以及第五電晶體(NT5)之源係連 結至第二節點(NT2)。 15 第六電晶體（NT6)之汲係連結至第三電晶體（NT3)之 源’第六電晶體(NT6)之閘係連結至第二節點(N2)，第六電 晶體(NT6)之源係連結至第二電源線端子(VSST)。第七電晶 體(NT7)之没係連結至輸入端子(IN)，第七電晶體(NT7)之閘 係連結至第二節點(N2)，以及第七電晶體(NT7)之源係連結 20至第二電源線端子(VSST)。第八電晶體(1^丁8)之汲係連結至 第二節點(N2)，第八電晶體(NT8)之閘係連結至輸入端子 (IN)，以及第八電晶體(NT8)i源係連結至第二電源線端子 (VSST) 〇 雖然未顯示於第3圖，但第八電晶體(NT8)之源可連結 14 200305848 至第三電源線端子，經由該第三電源線端子供給第三電源 電壓信號，其具有比第二電源電壓信號(VSS)更低的電源位 準。第九電晶體(NT9)之没係連結至輸出端子(in)，第九電 晶體(NT9)之閘係連結至控制端子（CT)，以及第九電晶體 · 5 (NT9)之源係連結至第二電源線(VSST)。 _ 下降驅動器部分包括NMOS電晶體(NT10, NT11，NT12 及NT13)。詳言之，第十電晶體(1^丁10)之汲係連結至第二節 點(N2)，第十電晶體(NT10)之閘係連結至第一節點(N1)， 以及第十電晶體（NT10)之源係連結至第二電源線端子 · 10 (VSST)。第十一電晶體"丁11)之汲係連結至第四電晶體 (NT4)之源，第十一電晶體(NT11)之閘係連結至第一節點 (N1)，以及第十一電晶體(NT11)之源係連結至第二電源線 (VSST)。第十二電晶體（>1丁12)之汲係連結至第一節點 (N1)，第十二電晶體(NT12)之閘係連結至控制端子(CT)， 15以及第十二電晶體(NT12)之源係連結至第二電源線端子 (VSST)。 載流輸出部分131e包括一第四電晶體(NT14)。第十四 _ 電晶體"丁14)之汲係連結至時脈端子(CKT)，第十四電晶體 (NT14)之閘係連結至第一節點（N1)，以及第十四電晶體 2〇 (NT14)之源係連結至載流輸出端子(CR)。如此，載流輸出 部分131 e傳輸時脈信號(CK或CKB)給次一驅動階段之輸入 端子(IN)。 於第η驅動階段(SRn)，由前一階段輸出之載流信號(CR) 係輸入第η驅動階段(SRCn)之輸入端子(IN)，第三電晶體 15 200305848 (NT3)藉載流信號(cr)導通。第一節點(N1)電位由第二電源 笔壓位準(VSS)改成第一電源電壓位準(vdd)。然後，當第 四電晶體(NT4)、第五電晶體(NT5)及第一節點（N1)電位升 问¥，第十電晶體(NT10)被導通。當第十電晶體(NT1〇)被 5 $通時’第二節點(N2)電位改成第二電源電壓位準(VSS)。 如此，第二電晶體(NT2)被導通。 當第一節點(N1)之電位升高時，第一電晶體(NT1)被導 通，具有高電壓位準之時脈信號(CK)被傳輸至輸出端子 (OUT)。輸出端子(OUT)輸出電壓充電於啟動電容器（c)，第 鲁 10 一電晶體(NT1)之閘電壓升高超過第一電源電壓位準。如 此，第一電晶體(NT1)維持導通態。 當具有高電壓位準之虛設階段(S RCn+1)之輸出信號輸 出至弟η驅動階段之控制端子(CT)時，第十二電晶體及第十 三電晶體(ΝΤ12，ΝΤ13)被導通。 15 當第十二電晶體(ΝΤ12)被導通時，第一節點(Ν1)電位 由第一電源電壓位準（VDD)改成第二電源電壓位準 (VSS)。然後第十電晶體(ΝΤ10)被導通。如此，第二節點(Ν2) _ 電位藉第四及第五電晶體(ΝΤ4, ΝΤ5)而由第二電源電壓位 準(VSS)被改成第一電源電壓位準(vdd)。 20 由控制端子(CT)輸出之虛設階段輸出信號導通第十三 電晶體(NT13)，第十三電晶體(NT13)及第二電晶體(NT2) 輸出第二電源電壓信號(VSS)給輸出端子(OUT)。 當第一電源電壓信號(VDD)輸出至輸出端子（OUT) 時，第七電晶體及第八電晶體(NT7, NT8)被導通，外加至 16 200305848 第η驅動階段輸入端子（ιΝ)之第驅動階段輸出信號被 改成高電壓位準。 特別，當第二電源電壓信號（VSS)輸出至輸出端子 (OUT)，由第（n-i)驅動階段輸出之高位準輸出信號提供給輸 5 入節點(IN)時，第八電晶體(NT8)被導通。如此，由（n-1)驅 動階段輸出之輸出信號放電至第二電源線端子(VSST)。 此外，第九電晶體(NT9)係藉由控制端子(CT)外加至虛 設階段(SRCn+Ι)輸出信號而被導通，放電提供給輸入節點 (IN)之(n-1)驅動階段之高位準輸出信號，因而防止第一電 10 晶體(NT1)被導通。 雖然當由控制端子(CT)供給的虛設階段(SRCn+Ι)之輸 出信號電位改成關掉電壓位準時，第十二電晶體(NT12)被 關掉，但第二節點(N2)藉第四及第五電晶體(NT4, NT5)維持 第一電源電壓位準。如此，第二電晶體(NT2)維持導通態， 15 第二電源信號(VSS)輸出至輸出端子(OUT)。 第5圖為電路圖顯示第2圖之虛設階段，以及第6圖為平 面圖顯不第5圖虛设階段之佈局。第5及6圖中，相同參考編 號表示第1圖之第η驅動階段(SCRn)之相同元件 ，如此將刪除相同元件之細節說明。 20 參照第5及6圖，虛設階段（SRCn+Ι)包括一升高部分 131a、一下降部分131b、一升高驅動器部分131c、一下降 驅動器部分13Id以及一載流輸出部分13le。虛設階段 (SRCn+Ι)之控制端子係連結至該虛設階段(SRCn+Ι)之輸出 端子。如此，虛設階段(SRCn+Ι)係由虛設階段(SRCn+Ι)之 17 200305848 輸出信號控制。 連結至虛設階段（SRCn+l)控制端子之電晶體(NT12，） 之電晶體大小比第η驅動階段（SRCn)之電晶體(NT 12)大小 改變，故可維持虛設階段(SRCn+l)之輸出信號經歷一段預 5定時間。後文中，電晶體大小係表示電晶體通道寬度(W) . 對電晶體通道長度(L)之比（w/L)。 例如虛設階段（SRCn+l)之電晶體(NT12，）之電晶體大 小約比第η驅動階段（SRCn)之電晶體(NT1幻之電晶體大小 小10倍。 _ 10 通常電晶體大小係依據通道寬度(W)決定。例如虛設階 段(SRCn+1)之電晶體(NT12，)之通道寬度(W，）約比第η驅動 階段(SRCn)之電晶體(ΝΤ12)之通道寬度(w)小1〇倍。如第4 及第6圖所示，第6圖電晶體(NT12)之通道寬度(w，）約比第* 圖之電晶體(NT12)之通道寬度(w)小1〇倍。 15 雖然虛設階段(SRCn+1)之高位準輸出信號饋回虛設階 段(SRCn+l)之控制端子(CT)，但依據電晶體(NT12)之電晶 體大小而定，經一段預定時間後第十二電晶體(NT12，)被導 鲁 通。如此，因虛設階段(SRCn+l)之高位準輸出信號回授至 虛設階段（SRCn+l)之控制端子（CT)後不久，第十電晶體 20 (NT1〇)未被關掉，故第二節點(N2)可維持第二電源電壓位 準(vss)經歷一段預定時間。因此，虛設階段(SRCn+i)之輸 出端子可維持高電壓位準經歷一段預定時間。 於一段預定時間後，當第十二電晶體(NT12，)被導通 日$ ’第十電晶體(NT10)被關掉，以及第二節點⑽）電位由 18 200305848 第二電源電壓位準(vss)改成第一電源電壓位準(VDD)。當 第一節點(N2)之電位改成第一電源電壓位準(vdd)時，電晶 體(NT2)被導通，故第二電源電壓（vss)輸出至虛設階段 (SCRn+Ι)之輸出端子(〇υτ)。 5 此外，連結至控制端子(CT)之第n驅動階段(SRCn)之第 十二電晶體(NT13)於虛設階段(SRCn+Ι)被去除。於第6圖所 示’第4圖之第十三電晶體(NT13)於虛設階段(SRCn+Ι)被去 除。如此，因唯有第二電晶體(NT2)輸出第二電源電壓(VSS) 給輸出端子（OUT)，故於一段預定延遲後，第二電源電壓 1〇 (VSS)輸出至輸出端子(OUT)。 弟7圖為線圖顯示具有第2圖驅動階段相同電路之虛設 階段輸出信號波形，第8圖為線圖顯示第5圖之虛設階段之 輸出信號波形。X軸表示時間（微分）中，y軸表示電壓（伏特）。 參照第7圖，於驅動階段循序輸出具高電壓位準之輸出 15信號(〇UTn_l，OUTn)，虛設階段(SRCn+Ι)操作而輸出該輸 出電壓（OUTn+1’）。第圖7中，虛設階段(SRCn+Ι)具有驅動 階段之相同電路，虛設階段(SRCn+Ι)之輸出端子係連結至 虛設階段(SRCn+Ι)之控制端子。一旦由虛設階段(SRCn+1) 之輸出端子輸出之信號（OUTn+Γ)電位經由第η驅動階段 2〇 (SRCn)之輸出信號(OUTn)而改變成高電壓位準時，具有高 電壓位準之輸出信號(OUTn+Γ)施加至第η驅動階段(SRCn) 之控制端子及虛設階段(SRCn+Ι)之控制端子。 由虛設階段（SRCn+Ι)之輸出端子輸出之輸出信號 (OUTn+1 ’）電位藉回授至虛設階段(SRCn+Ι)之控制端子之 19 200305848 輸出信號（〇υΤη+1，）而改變成關斷電壓位準（或低電壓位 準）。如此，輸出信號(OUTn+1，)確實維持高電壓位準經歷 一段預定持間，且下降至關斷電壓位準。輸出信號 (OUTn+1，)之最大電壓位準係遠小於輸出信號(OUTn)之最 5 大電壓位準。 但當虛設階段(SRCn+Ι)具有第5圖之電路時，如第8圖 所示，輸出信號(OUTn+1)具有比輸出信號(OUTn+Γ)更穩 定的波形。於驅動階段循序輸出具有高電壓位準之輸出信 號(〇UTn-l，OUTn)後，虛設階段(SRCn+Ι)被操作而輸出輸 10 出信號(OUTn+1)。 一旦由虛設階段(SRCn+Ι)之輸出端子輸出的輸出信號 (OUTn+1)之電位，藉第η驅動階段(SRCn)之輸出信號(OUTn) 而改變成導通電壓位準（或高電壓位準）時，具有導通電壓位 準之輸出信號（OUTn+1)外加至該第n驅動階段（SRCn)之控 15 制端子及該虛設階段(SRCn+Ι)之控制端子。 然後，雖然輸出信號（OUTn+1)外加至虛設階段 (SRCn+Ι)之控制端子，但由虛設階段(SRCn+Ι)之輸出端子 輸出的輸出信號（OUTn+1)並未瞬間改變成關斷電源位 準，反而由虛設階段(SRCn+Ι)之輸出端子輸出之輸出信號 20 (OUTn+1)係於一段預定時間後而變成關斷電源位準。因 此，之輸出信號(OUTn+1)可維持高電壓位準經歷一段預定 時間。 產生輸出信號(OUTn+1)其具有幾乎與輸出信號(〇UTn) 相等的電壓位準。因此，第η驅動階段(SRCn)可藉虛設階段 20 200305848 (SRCn+l)之輸出信號(ουτη+l)而穩定驅動。 第9圖為電路圖顯示根據本發明之第二具體實施例之 驅動階段及虛設階段。 參照第9圖，根據本發明之第二具體實施例之位移暫存 5 器133包括η驅動階段（SRC1，…，SRCn)及一虛設階段 (SRCn+l)。該第n驅動階段(SRCn)包括一升高部分133a、一 下降部分133b、一升高驅動器部分133c及一下降驅動器部 分133d。 上升部分131a包括一第一NMOS電晶體(NTla)。時脈信 春 10 號(CK)係外加至第一NMOS電晶體(NTla)之汲，第一NMOS 電晶體（NTla)之閘係連結至第一節點（Nla)，以及第一 NMOS電晶體(NT 1 a)之源係連結至該輸出端子（〇UTn)。 下降部分131b包括一第二NMOS電晶體(NT2a)。第二 NMOS電晶體"丁2&)之汲係連結至該輸出端子（〇uTn)，第 15二NMOS電晶體(NT2a)之閘係連結至第二節點(似4，以及 第二NMOS電晶體(NT2a)之源係連結至第二電源線端子 (VSST)。 _ 升高驅動器部分133c包括一電容器（c)、NMOS電晶體 (NT3a、NT4a、NT5a)。第三電晶體(NT3a)之汲係連結至第 20 一電源線端子(VDDT)，第三電晶體(NT3a)之閘係連結至輸 入端子(IN)，以及第三電晶體(NT3a)之源係連結至第一節點 (Nla)。第四電晶體(NT4a)之汲係連結至第一節點(Nla),第 四電晶體(NT4a)之閘係連結至控制端子（CT)，以及第四電 晶體(NT4a)之源係連結至第二電源線端子(VSST)。第五電 21 200305848 晶體（NT5a)之汲係連結至第一節點（Nla)，第五電晶體 (NT5a)之閘係連結至第二節點（N2a)，以及第五電晶體 (NT5a)之源係連結至第二電源線端子(VSST)。第三電晶體 (NT3a)之電晶體大小約比第五電晶體(NT5a)之電晶體大小 5 大2倍。 下降驅動器部分133d包括NMOS電晶體（NT6a， NT7a)。詳言之，第六電晶體(1^6&)之汲及閘係共通連結至 第二電源線端子(VDDT)，以及第六電晶體(NT6a)之源係連 結至第二節點(N2a)。第七電晶體(NT7a)之汲係連結至第二 10節點（N2a)，第七電晶體（NT7a)之閘係連結至第一節點 (N21)，以及第七電晶體(NT7a)之源係連結至第二電源線端 子(VSST)。第六電晶體(NT6a)之電晶體大小約比第七電晶 體(NT7a)之電晶體大小大16倍。 當第（n-1)個驅動階段（SRCn-Ι)之輸出信號輸出至第η 15驅動階段(SRCn)之輸入端子(IN)時，第七電晶體(NT7a)被導 通。當第七電晶體(NT7a)被導通時，第二節點(N2a)電位由 第一電源電壓位準（VDD)改變成第二電源電壓位準 (VSS)。然後即使第七電晶體(NT7a)被導通，因第六電晶體 (NT6a)電晶體大小比第七電晶體(NT7a)之電晶體大小約大 20 6倍，第二節點(N2a)仍然維持第二電源電壓位準(VSS)。 ϊ具有南電壓位準之虛設階段（SRCn+1)之輸出信號 (OUTn+1)經由第n驅動階段（sRCn)之控制端子（CT)回收 日守’弟七電晶體(NT7a)被關斷。如此，第二節點(N2a)電位 藉第六電晶體(NT6a)，而由第二電源電壓位準(vss)改成第 22 200305848 一電源電壓位準(VDD)。 即使當經由第η驅動階段（SRCn)之控制端子（CT)外加 的虛設階段（SRCn+Ι)之輸出信號電位被改成關斷電壓位 準’且第四電晶體(NT4a)被關斷時，第二節點因第六電晶 5 體(NT6a)而維持第一電源電壓位準(VDD)。如此，第二電晶 體(NT2a)維持導通態，輸出端子(OUTn)具有第二電源電壓 位準（VSS)。 如第9圖所示，虛設階段（SRCn+Ι)包括一升高部分 133a、一下降部分133b、一升高驅動器部分133c及一下降 10驅動器部分133d。虛設階段(SRCn+Ι)之控制端子係連結至 虛設階段（SRCn+Ι)之輸出端子。如此，虛設階段(SRCn+1) 係由虛設階段(SRCn+Ι)之輸出信號控制。 連結至虛設階段(SRCn+Ι)之控制端子之電晶體之電晶 體大小比連結至第n驅動階段（SRCn)控制端子之電晶體之 15 電晶體大小改變，故維持虛設階段(SRCn+Ι)之輸出信號經 歷一段預定時間。 例如虛設階段（SRCn+Ι)之電晶體(NT4，)之電晶體大小 約比第η驅動階段(SRCn)之電晶體(NT4)之電晶體大小小10 倍。如此，因虛設階段（SRCn+i)之高位準輸出信號回授至 20虛設階段（SRCn+l)之控制端子（CT)後不久，因第四電晶體 (NT4’）未被關掉，故第七電晶體(NT7a)未即刻被導通。第 四節點(N4)維持第二電源電壓位準（vss)經歷一段預定時 間。因此虛設階段(SRCn+Ι)之輸出端子維持高電壓位準經 歷一段預定時間。 23 200305848 於一段預定時間後，當第四電晶體(NT4，)被導通時， 第七電晶體(NT7a)被關掉，且第四節點(N4)電位由第二電 源電壓位準(VSS)改變成第一電源電壓位準(Vdd)。如此當 第四節點(N4)之電位改成第一電源電壓位準(vdd)B夺，第二 5電晶體(NT2a)被導通，故第二電源電壓位準(vss)被輸出至 虛設階段(SRCn+1)之輸出端子(OUT)。 虛設階段(SRCn+Ι)之控制端子(CT)係連結至虛設階段 (SRCn+Ι)之輸出端子（〇υΤη+1)，故虛設階段（SRCn+1)可維 持穩定操作。此外，閘驅動器電路無需另一外部佈線，經 10由該佈線控制信號被外加至虛設階段(SRCn+1)之控制端子 (CT)。 如此，可防止外部佈線與其它佈線間之電容，外加至 閘驅動器電路之信號可未延遲。 第10圖為方塊圖顯示根據本發明之第三具體實施例， 15驅動閘驅動器電路用之位移暫存器，以及糾圖為線圖顯 示第10圖之閘驅動器電路之輸出信號波形。後文ri」為小 於「η」之偶數。 20The rising portion 131a includes a first nmOS transistor (NT1). The clock signal 20 (CK) is added to the drain of the first NMOS transistor (NT1), and the gate system of the first NMOS transistor (NT1) is connected to a first node (N1), and the first · NMOS transistor The source of the crystal (NT1) is connected to the output terminal (〇υτ). The falling portion 131b includes a second nmOS transistor (NT2). The drain of the second NMOS transistor (NT2) is connected to the output terminal (〇υτ), the gate of the 13th 200305848 second NMOS transistor (NT2) is connected to a second node (N2), and the second NMOS The source of the transistor (NT2) is connected to the second power line terminal (VSST). The boost driver section 131c includes a capacitor (c), an NMOS transistor 5 (NT3, NT4, NT5, NT6, NT7, NT8, and NT9). The capacitor is connected between the first input node (N1) and the output terminal (OUT). The drain of the third transistor (NT3) is connected to the first power line terminal (VDDT), the gate of the third transistor (NT3) is connected to the input terminal (IN), and the source of the third transistor (NT3) is connected To the first input node (N1). The drain and gate of the fourth transistor (NT4) are connected in common to the first power line terminal (VDDT), and the source of the fourth transistor (NT4) is connected to the gate of the fourth transistor (NT5). The drain of the fifth transistor " 5) is connected to the first power line terminal (VDDT), the gate of the fifth transistor (NT5) is connected to the source of the fourth transistor (NT4), and the fifth transistor The source of (NT5) is connected to the second node (NT2). 15 The drain of the sixth transistor (NT6) is connected to the source of the third transistor (NT3). The gate of the sixth transistor (NT6) is connected to the second node (N2) and the sixth transistor (NT6) is connected to the source. The source is connected to a second power line terminal (VSST). The seventh transistor (NT7) is connected to the input terminal (IN), the seventh transistor (NT7) is connected to the second node (N2), and the seventh transistor (NT7) is connected to the source 20 To the second power line terminal (VSST). The drain of the eighth transistor (1 ^ 8) is connected to the second node (N2), the gate of the eighth transistor (NT8) is connected to the input terminal (IN), and the eighth transistor (NT8) i source It is connected to the second power line terminal (VSST). Although not shown in Figure 3, the source of the eighth transistor (NT8) can be connected to 14 200305848 to the third power line terminal and supplied to the third power line terminal. The three power supply voltage signal has a lower power supply level than the second power supply voltage signal (VSS). The ninth transistor (NT9) is connected to the output terminal (in), the ninth transistor (NT9) is connected to the control terminal (CT), and the ninth transistor · 5 (NT9) is connected to the source To the second power line (VSST). _ The falling driver section includes NMOS transistors (NT10, NT11, NT12 and NT13). In detail, the drain of the tenth transistor (1 ^ 10) is connected to the second node (N2), the gate of the tenth transistor (NT10) is connected to the first node (N1), and the tenth transistor The source of (NT10) is connected to the second power line terminal · 10 (VSST). The drain of the eleventh transistor " D11) is connected to the source of the fourth transistor (NT4), the gate of the eleventh transistor (NT11) is connected to the first node (N1), and the eleventh transistor The source of the crystal (NT11) is connected to the second power supply line (VSST). The drain system of the twelfth transistor (> 1212) is connected to the first node (N1), and the gate system of the twelfth transistor (NT12) is connected to the control terminal (CT), 15 and the twelfth transistor. The source of (NT12) is connected to the second power line terminal (VSST). The current-carrying output section 131e includes a fourth transistor (NT14). The fourteenth transistor is connected to the clock terminal (CKT), the fourteenth transistor (NT14) is connected to the first node (N1), and the fourteenth transistor 2 The source of 〇 (NT14) is connected to the current-carrying output terminal (CR). Thus, the current-carrying output section 131e transmits a clock signal (CK or CKB) to the input terminal (IN) of the next driving stage. In the n-th driving stage (SRn), the current-carrying signal (CR) output from the previous stage is the input terminal (IN) of the n-th driving stage (SRCn). The third transistor 15 200305848 (NT3) borrows the current-carrying signal. (cr) Conduction. The potential of the first node (N1) is changed from the second power supply pen voltage level (VSS) to the first power supply voltage level (vdd). Then, when the potential of the fourth transistor (NT4), the fifth transistor (NT5), and the first node (N1) rises, the tenth transistor (NT10) is turned on. When the tenth transistor (NT10) is turned on by 5 $, the potential of the second node (N2) is changed to the second power supply voltage level (VSS). In this way, the second transistor (NT2) is turned on. When the potential of the first node (N1) rises, the first transistor (NT1) is turned on, and a clock signal (CK) having a high voltage level is transmitted to the output terminal (OUT). The output voltage at the output terminal (OUT) is charged in the startup capacitor (c), and the gate voltage of the first transistor (NT1) rises above the first power supply voltage level. As such, the first transistor (NT1) is maintained in an on state. When the output signal of the dummy stage (S RCn + 1) with a high voltage level is output to the control terminal (CT) of the driving stage, the twelfth transistor and the thirteenth transistor (NT12, NT13) are turned on. . 15 When the twelfth transistor (NT12) is turned on, the potential of the first node (N1) is changed from the first power supply voltage level (VDD) to the second power supply voltage level (VSS). The tenth transistor (NT10) is then turned on. In this way, the potential of the second node (N2) _ is changed from the second power supply voltage level (VSS) to the first power supply voltage level (vdd) by the fourth and fifth transistors (NT4, NT5). 20 The dummy stage output signal from the control terminal (CT) turns on the thirteenth transistor (NT13), the thirteenth transistor (NT13) and the second transistor (NT2) output a second power voltage signal (VSS) to the output Terminal (OUT). When the first power-supply voltage signal (VDD) is output to the output terminal (OUT), the seventh transistor and the eighth transistor (NT7, NT8) are turned on, and are added to the 16th input terminal (ιN) of 2003 200305848th driving stage. The output signal of the driving phase is changed to a high voltage level. In particular, when the second power supply voltage signal (VSS) is output to the output terminal (OUT) and the high-level output signal output from the (ni) driving stage is provided to the input 5 input node (IN), the eighth transistor (NT8) Be turned on. In this way, the output signal output from the (n-1) driving stage is discharged to the second power line terminal (VSST). In addition, the ninth transistor (NT9) is turned on by applying the control terminal (CT) to the output signal of the dummy phase (SRCn + 1), and the discharge is provided to the high level of the (n-1) driving phase of the input node (IN). The quasi-output signal prevents the first electric crystal (NT1) from being turned on. Although the twelfth transistor (NT12) is turned off when the output signal potential of the dummy stage (SRCn + 1) supplied from the control terminal (CT) is changed to the turn-off voltage level, the second node (N2) borrows the The fourth and fifth transistors (NT4, NT5) maintain the first power supply voltage level. In this way, the second transistor (NT2) is maintained in an on state, and the second power supply signal (VSS) is output to the output terminal (OUT). Figure 5 is a circuit diagram showing the dummy stage of Figure 2, and Figure 6 is a plan view showing the layout of the dummy stage of Figure 5. In Figs. 5 and 6, the same reference numbers indicate the same components of the nth driving stage (SCRn) of Fig. 1, so the detailed description of the same components will be deleted. 20 Referring to FIGS. 5 and 6, the dummy phase (SRCn + 1) includes a raised portion 131a, a lowered portion 131b, a raised driver portion 131c, a lowered driver portion 13Id, and a current-carrying output portion 13le. The control terminal of the dummy phase (SRCn + 1) is connected to the output terminal of the dummy phase (SRCn + 1). In this way, the dummy phase (SRCn + 1) is controlled by the output signal of the dummy phase (SRCn + 1). The size of the transistor (NT12,) connected to the control terminal of the dummy phase (SRCn + 1) is changed from the size of the transistor (NT12) of the nth driving phase (SRCn), so the dummy phase (SRCn + l) can be maintained. The output signal goes through a predetermined period of time. In the following, the transistor size refers to the transistor channel width (W). The ratio (w / L) to the transistor channel length (L). For example, the size of the transistor (NT12,) in the dummy stage (SRCn + 1) is about 10 times smaller than that of the transistor (NT1 in the RC stage) (SRCn). _ 10 Generally, the size of the transistor is based on The channel width (W) is determined. For example, the channel width (W,) of the transistor (NT12,) in the dummy phase (SRCn + 1) is approximately larger than the channel width (w) of the transistor (NT12) in the n-th driving phase (SRCn). 10 times smaller. As shown in Figures 4 and 6, the channel width (w,) of the transistor (NT12) in Figure 6 is approximately 10 times smaller than the channel width (w) of the transistor (NT12) in Figure *. 15 Although the high-level output signal of the dummy stage (SRCn + 1) is fed back to the control terminal (CT) of the dummy stage (SRCn + 1), it depends on the size of the transistor (NT12), after a predetermined period of time After the twelfth transistor (NT12,) is turned on. Therefore, due to the high-level output signal of the dummy phase (SRCn + 1) is returned to the control terminal (CT) of the dummy phase (SRCn + 1), the first The ten transistor 20 (NT1〇) is not turned off, so the second node (N2) can maintain the second power voltage level (vss) for a predetermined period of time. Therefore, during the dummy phase (SRCn + i), The output terminal can maintain a high voltage level for a predetermined period of time. After a predetermined period of time, when the twelfth transistor (NT12,) is turned on, the 'tenth transistor (NT10) is turned off, and the second node ⑽ ) The potential was changed from 18 200305848 second power supply voltage level (vss) to first power supply voltage level (VDD). When the potential of the first node (N2) is changed to the first power supply voltage level (vdd), the transistor (NT2) is turned on, so the second power supply voltage (vss) is output to the output terminal of the dummy stage (SCRn + 1). (〇υτ). 5 In addition, the twelfth transistor (NT13) connected to the n-th drive stage (SRCn) of the control terminal (CT) is removed in the dummy stage (SRCn + 1). The thirteenth transistor (NT13) shown in Fig. 6 ', Fig. 4 is removed in the dummy phase (SRCn + 1). In this way, because only the second transistor (NT2) outputs the second power supply voltage (VSS) to the output terminal (OUT), the second power supply voltage 10 (VSS) is output to the output terminal (OUT) after a predetermined delay. . Figure 7 is a line chart showing the output signal waveform of the dummy phase with the same circuit as the driving phase of Figure 2. Figure 8 is a line chart showing the output signal waveform of the dummy phase of Figure 5. The X-axis represents time (derivative), and the y-axis represents voltage (volts). Referring to FIG. 7, the output 15 signals (OUTN_1, OUTn) with high voltage levels are sequentially output during the driving phase, and the dummy phase (SRCn + 1) is operated to output the output voltage (OUTn + 1 '). In FIG. 7, the dummy phase (SRCn + 1) has the same circuit as the driving phase, and the output terminals of the dummy phase (SRCn + 1) are connected to the control terminals of the dummy phase (SRCn + 1). Once the potential of the signal (OUTn + Γ) output from the output terminal of the dummy phase (SRCn + 1) is changed to a high voltage level via the output signal (OUTn) of the nth driving phase 20 (SRCn), it has a high voltage level The output signal (OUTn + Γ) is applied to the control terminal of the nth drive stage (SRCn) and the control terminal of the dummy stage (SRCn + 1). The potential of the output signal (OUTn + 1 ') output from the output terminal of the dummy phase (SRCn + 1) is changed to 19 200305848 output signal (〇υΤη + 1,) of the control terminal of the dummy phase (SRCn + 1). To turn off the voltage level (or low voltage level). In this way, the output signal (OUTn + 1,) does maintain a high voltage level for a predetermined period of time and decreases to the off-voltage level. The maximum voltage level of the output signal (OUTn + 1,) is much smaller than the maximum 5 voltage level of the output signal (OUTn). However, when the dummy phase (SRCn + 1) has the circuit of Fig. 5, as shown in Fig. 8, the output signal (OUTn + 1) has a more stable waveform than the output signal (OUTn + Γ). After the output signal (OUTN-1, OUTn) with a high voltage level is sequentially output during the driving phase, the dummy phase (SRCn + 1) is operated to output an output signal (OUTn + 1). Once the potential of the output signal (OUTn + 1) output from the output terminal of the dummy phase (SRCn + 1) is changed to the on-voltage level (or high voltage level) by the output signal (OUTn) of the nth driving phase (SRCn) When the output voltage is ON, the output signal (OUTn + 1) with the on-voltage level is applied to the control terminal of the nth driving stage (SRCn) and the control terminal of the dummy stage (SRCn + 1). Then, although the output signal (OUTn + 1) is added to the control terminal of the dummy phase (SRCn + 1), the output signal (OUTn + 1) output from the output terminal of the dummy phase (SRCn + 1) does not change to OFF instantly. The power-off level, instead, the output signal 20 (OUTn + 1) output from the output terminal of the dummy stage (SRCn + 1) becomes the power-off level after a predetermined time. Therefore, the output signal (OUTn + 1) can maintain the high voltage level for a predetermined time. An output signal (OUTn + 1) is generated, which has a voltage level almost equal to the output signal (OUTN). Therefore, the n-th driving phase (SRCn) can be driven stably by the output signal (ουτη + l) of the dummy phase 20 200305848 (SRCn + 1). Fig. 9 is a circuit diagram showing a driving phase and a dummy phase according to a second embodiment of the present invention. Referring to FIG. 9, the displacement temporary storage device 133 according to the second embodiment of the present invention includes an n driving stage (SRC1, ..., SRCn) and a dummy stage (SRCn + 1). The n-th driving stage (SRCn) includes a raised portion 133a, a lowered portion 133b, a raised driver portion 133c, and a lowered driver portion 133d. The rising portion 131a includes a first NMOS transistor (NTla). The clock Xinchun No. 10 (CK) is added to the drain of the first NMOS transistor (NTla), the gate of the first NMOS transistor (NTla) is connected to the first node (Nla), and the first NMOS transistor (NT) 1 a) The source is connected to the output terminal (〇UTn). The falling portion 131b includes a second NMOS transistor (NT2a). The drain of the second NMOS transistor " D2 &) is connected to the output terminal (〇uTn), and the gate of the 15th NMOS transistor (NT2a) is connected to the second node (like 4, and the second NMOS transistor) The source of the crystal (NT2a) is connected to the second power line terminal (VSST). _ The boost driver section 133c includes a capacitor (c), an NMOS transistor (NT3a, NT4a, NT5a). The third transistor (NT3a) The drain is connected to the 20th power line terminal (VDDT), the gate of the third transistor (NT3a) is connected to the input terminal (IN), and the source of the third transistor (NT3a) is connected to the first node (Nla ). The drain of the fourth transistor (NT4a) is connected to the first node (Nla), the gate of the fourth transistor (NT4a) is connected to the control terminal (CT), and the source of the fourth transistor (NT4a) It is connected to the second power line terminal (VSST). The fifth system 21 200305848 is connected to the first node (Nla), and the fifth transistor (NT5a) is connected to the second node (N2a). The source of the fifth transistor (NT5a) is connected to the second power line terminal (VSST). The transistor size of the third transistor (NT3a) is approximately larger than that of the fifth transistor (NT5a). The crystal size is 5 times 2 times. The lower driver part 133d includes NMOS transistors (NT6a, NT7a). In detail, the drain and gate of the sixth transistor (1 ^ 6 &) are commonly connected to the second power line terminal (VDDT ), And the source of the sixth transistor (NT6a) is connected to the second node (N2a). The source of the seventh transistor (NT7a) is connected to the second 10 node (N2a), the seventh transistor (NT7a) The gate is connected to the first node (N21), and the source of the seventh transistor (NT7a) is connected to the second power line terminal (VSST). The size of the transistor of the sixth transistor (NT6a) is approximately larger than that of the seventh transistor The size of the transistor of (NT7a) is 16 times larger. When the output signal of the (n-1) th driving stage (SRCn-1) is output to the input terminal (IN) of the η15th driving stage (SRCn), the seventh The crystal (NT7a) is turned on. When the seventh transistor (NT7a) is turned on, the potential of the second node (N2a) is changed from the first power supply voltage level (VDD) to the second power supply voltage level (VSS). Then even The seventh transistor (NT7a) is turned on because the size of the sixth transistor (NT6a) is about 20 6 times larger than that of the seventh transistor (NT7a). The second node (N2a) The second power supply voltage level (VSS) is still maintained. Ϊ The output signal (OUTn + 1) of the dummy phase (SRCn + 1) with the south voltage level is recovered through the control terminal (CT) of the nth drive phase (sRCn). Shou's seventh transistor (NT7a) was turned off. In this way, the potential of the second node (N2a) is changed from the second power supply voltage level (vss) to the 22nd power supply voltage level (VDD) by the sixth transistor (NT6a). Even when the output signal potential of the dummy stage (SRCn + 1) via the control terminal (CT) of the nth drive stage (SRCn) is changed to the shutdown voltage level 'and the fourth transistor (NT4a) is turned off The second node maintains the first power supply voltage level (VDD) due to the sixth transistor 5 body (NT6a). In this way, the second electric transistor (NT2a) is maintained in the on state, and the output terminal (OUTn) has the second power supply voltage level (VSS). As shown in Fig. 9, the dummy phase (SRCn + 1) includes a raised portion 133a, a lowered portion 133b, a raised driver portion 133c, and a lowered driver portion 133d. The control terminals of the dummy phase (SRCn + 1) are connected to the output terminals of the dummy phase (SRCn + 1). In this way, the dummy phase (SRCn + 1) is controlled by the output signal of the dummy phase (SRCn + 1). The size of the transistor connected to the control terminal of the dummy stage (SRCn + 1) is smaller than that of the transistor connected to the control terminal of the nth drive stage (SRCn). The size of the transistor is changed, so the dummy stage (SRCn + 1) is maintained. The output signal goes through a predetermined time. For example, the transistor size of the transistor (NT4,) in the dummy stage (SRCn + 1) is about 10 times smaller than the transistor size of the transistor (NT4) in the nth drive stage (SRCn). In this way, because the high-level output signal of the dummy stage (SRCn + i) is fed back to the control terminal (CT) of the 20 dummy stage (SRCn + l), shortly after the fourth transistor (NT4 ') is not turned off, The seventh transistor (NT7a) was not immediately turned on. The fourth node (N4) maintains the second power voltage level (vss) for a predetermined time. Therefore, the output terminal of the dummy phase (SRCn + 1) maintains the high voltage level for a predetermined time. 23 200305848 After a predetermined period of time, when the fourth transistor (NT4,) is turned on, the seventh transistor (NT7a) is turned off, and the potential of the fourth node (N4) is set by the second power voltage level (VSS) Change to the first power supply voltage level (Vdd). In this way, when the potential of the fourth node (N4) is changed to the first power supply voltage level (vdd) B, the second 5 transistor (NT2a) is turned on, so the second power supply voltage level (vss) is output to the dummy stage. (SRCn + 1) output terminal (OUT). The control terminal (CT) of the dummy phase (SRCn + 1) is connected to the output terminal (0υΤη + 1) of the dummy phase (SRCn + 1), so the dummy phase (SRCn + 1) can maintain stable operation. In addition, the gate driver circuit does not require another external wiring, and the wiring control signal is externally applied to the control terminal (CT) of the dummy stage (SRCn + 1) via the wiring. In this way, the capacitance between the external wiring and other wiring can be prevented, and the signal applied to the gate driver circuit can be undelayed. Fig. 10 is a block diagram showing a displacement register for a 15-drive gate driver circuit according to a third embodiment of the present invention, and a line diagram showing an output signal waveform of the gate driver circuit of Fig. 10; "Ri" is an even number less than "η". 20
參照第1〇圖，根據本發明第三具體實施例之間驅動 電路150包括-位移暫存器151。位移暫存器151被劃分為 —組G1及第二組G2。第一組及第二組⑴及⑺各自包括 數個階段。佈線部分152係設置_該位移暫存器i5i。 線部分152對位移暫存器151提供複數個信號。詳言之， 線部分152包括一開始信號線（STL)、一第一電源 (VDDL)第a守脈線(CKL1)、_第二時脈線(cm)、 24 200305848 第一電源線(VSSL)、一第三時脈線(CKL幻及第四時脈線 (CKBL2) 〇 一第一時脈信號(CK)係經由第一時脈線(CKL1)而外加 至第一組G1之驅動階段(SRC1，·.·，SRci-D之奇數驅動階段 5 (SRC1，…，SRC3)。第一時脈信號(CK)係經由第三時脈線 . (CKL2)外加至第二組g2之驅動階段(SRCi，…，SRCn)之奇 數驅動階段(SRCi+1)。相對於第一時脈信號(CK)有丨8〇度相 差的第一時脈信號(CKB)經由第二時脈線(CKBL1)，外加至 第一組G1之驅動階段（SRC1，…，SRCM)之偶數驅動階段 鲁 10 (SRC2，…）。第二時脈信號（CKB)係經由第四時脈信號 (CKBL2)而外加至第二組G2·動階段(SRCi，…，SRCn)之偶 數驅動階段(SRCi，...，SRCn；)。 如此，η驅動階段(SRC1，…，SRCn)之若干部分係回應 於第一及第一時脈信號CK及CKB，第一及第二時脈信號CK 15及CKB係分別經由第一及第二時脈線CKL1及CKBL1而外 加至該η驅動階段(SRC1，…，SRCn)。！!驅動階段(SRC1，…， SRCn)之其它部分係回應於第一及第二時脈信號CK及 _ CKB，第一及第二時脈信號ck及CKB係分別經由第三及第 四日守脈線CKL2及CKBL2而外加至該η驅動階段（srcI，…， 20 SRCn)。因此，具有導通電壓位準且循序外加至第一閘線、 第二閘線、…、第η閘線之第一及第二時脈信號CK及cKB - 之延遲減至最低，因此可防止由各階段輸出之輸出信號的 失真。 第三及第四時脈線CKL2及CKBL2未交叉其它佈線 25 200305848 (VSSL·、VDDL、STL等），故連結至n驅動階段(SRC1，…， SRCn)之各個驅動階段。第三及第四時脈 線 CKL2 及 CKBL2 各自係連結至第一及第二時脈線CKL1&CKBU之末端，該 第一及第二時脈線CKL1及CKBL1欲連結至n驅動階段 5 (SRC1, ···，SRCn)之各驅動階段。 特別’其中輸入第一時脈信號CK至第三時脈線CKL2 之第一端係設置毗鄰於，其中輸入第一時脈信號CK至第一 日寸脈線CKL1之第-端。（其中輸入第二時脈信號^^之）第 二時脈信號CKBL1之第一端係設置毗鄰於（其中輸入第二 鲁 10時脈信號CKB之）第四時脈之第一端。換言之，第 一、第二、第三及第四時脈線(CKU、CKB卜CKL2、CKBL2) 之輸入端係設置晚鄰於該第一驅動階段(SRC1)。 第一時脈線CKL1之第二端係於虛設階段(SRCn+1)附 近，連結至第三時脈線CKL2之第二端。 15 第三及第四時脈線CKL2及CKBL2非直連結至位移暫 存器151，且未交又其它佈線。如此，第一及第二時脈信號 CK及CKB可比行進通過第一及第二時脈線CKL1及 _ CKBL1 ’更快速行進通過第三及第四時脈線CKL2及 CKBL2。 -° 此外，佈線寬度愈窄，則位移暫存器151愈毗鄰於佈線。 · 特別，開始信號線STL設置最接近於位移暫存器15丨， · 開始信號線S TL後其次設置第一電源線VDDL。第一電源線 VDDL之後，循序設置第一及第二時脈線CK1及CKBL1。第 一時脈線CKL1之後設置第二電源線VSSL。第二電源線 26 200305848 VSSL之後，設置第三時脈線CKL2。第三時脈線CKL2之後 設置第四時脈線CKBL2。 因佈線部分152之佈線係以前述順序設置，故lcd裝置 可知:供較鬲顯示品質。佈線設置較為此鄰於位移暫存器 5 151，則佈線間之總接觸面積較大，以及佈線間彼此接觸電 容較大。因此，佈線受佈線間電容的影響較小，則位移暫 存器151設置較為接近佈線。因此，LCD裝置可提供較高顯 不品質。 參照第11圖，第一及第二時脈信號CK及CKB係經由第 10 一及第二時脈線CKL1及CKBL1，而供給位移暫存器151至 第一組G1。當開始信號ST外加至第一組⑴之第一驅動階段 SRC1時’第一驅動階段8尺(^回應於開始信號st，而輸出 第一輸出信號OUT1其具有高第一時脈信號CK之高電壓位 準。然後’第二驅動階段SRC2回應於第一驅動階段SRC1 15 之第一輸出信號OUT1，而輸出第二輸出信號〇UT2，其具 有高第二時脈信號CKB之高電壓位準。 當第一及第二時脈信號CK及CKB經由第三及第四時 脈線CKL2及CKBL2，供給位移暫存器151至第二組G2時， 第i驅動階段SRCi亦即第二組G2之第一驅動階段，回應於第 20屮1)驅動階段SRCi-Ι之第（i-Ι)輸出信號〇UTi-l，而輸出第⑴ 輸出信號OUTi，其具有第二時脈信號CKB之高電壓位準。 然後，第（i+Ι)驅動階段SRCi+Ι回應於第⑴驅動階段SRCi 之第（i)輸出信號OUTi，而輸出第（i+1)輸出信號〇UT+i，其 具有第一時脈信號CK之高電壓位準。 27 200305848 如雨文說明，第一、第二…及第（n)輸出信號(〇UTl、 OUT2 ' ···、OUTn)#序輸出，於各驅動階段輸出之輸出端 子具有高電壓位準。 第U圖為佈局圖顯示第1〇圖之閘驅動電路之第三及第 5四日守脈線配置，以及第13圖為佈局圖顯示位移暫存器之第 一、第三、第二及第四時脈線間之另一連結範例。 參知、第12圖’開始信號線STL、第一電源線VDDL、第 一及第二時脈線CKL1及CKBL1、第二電源線VSSL、第三 及第四日守脈線CKL2及CKBL2係循序設置於位移暫存器151 _ 1〇旁。各佈線寬度愈窄，則位移暫存器151設置愈毗鄰於佈 線。換言之，遠離位移暫存器151之佈線寬度不小於設置接 近位移暫存器151之佈線寬度。佈線設置愈毗鄰於位移暫存 為，則佈線間之總接觸面積愈大，且彼此接觸之佈線間之 電容愈大。因此，佈線受佈線間電容影響較小，佈線設置 15 較接近於位移暫存器151。 特別’開始信號線STL設置最接近於位移暫存器15ι， 開始信號線STL後其次設置第一電源線¥1)£^。第一電源線 鲁 VDDL之後，循序設置第一及第二時脈線(：：1〇及(：1^1^。第 二時脈線CKL1設置於比第一時脈線CKU更接近位移暫存 20态151。第一時脈線CKL1後其次設置第二電源線VSSL·。因 、 此’可減少佈線與連結線[供連結該佈線至各階段(SRC1，...， . SRCn+1)]間之電容造成的信號延遲減少。第三及第四時脈 線CKL2及CKBL2未交叉其它佈線(VSSL、vDDL、stl等）， 故連結至位移暫存器151。因第三及第四時脈線〇尺1^及 28 200305848 CKBL2末端分別係連結至欲連結至位移暫存器之第一及第 一時脈線CKL1及CKBL1末端，故第三及第四時脈線CKL2 及CKBL2設置成比第二電源線VSSL更遠離位移暫存器。換 言之，第三及第四時脈線CKL2及CKBL2係設置於第二電源 5線VSSL外側。如第丨2圖所示，第三及第四時脈線CKL2& CKBL2成形於TFT基板300之封合線區（sa)。 TFT基板300被劃分為一顯示區（DA)以及一環繞該顯 示(DA)之周邊區（PA)。閘線（圖中未顯示）、資料線（圖中未 顯示）及像素（圖中未顯示）係形成於顯示區（DA)。 1〇 周邊區(PA)被劃分為閘驅動區（GA)及封合線區（sA)。 位私暫存# 151及各佈線係形成於閘驅動區（〇Α)。供接合 TFT基板與濾色片基板（圖中未顯示）之封合劑（圖中未顯示） 係形成於封合線區（SA)。部分封合線區（SA)與部分閘驅動 區（GA)彼此重疊。封合線區（SA)被劃分為第一區及第二 15區。液晶層係形成於封合線區（SA)之第一區，液晶層未形 成於封合線區（SA)之第二區。閘驅動區（ga)包括第一區。 第三及第四時脈線CKL2及CKBL2以及部分第二電源 線VSSL係形成於該封合線(SA)。第二電源線VSSL、第一及 第二時脈線C K L1及C K B L1及開始信號線S T L之其它部分 20係形成於閘驅動區（GA)。 部分第二電源線VSSL、第一及第二時脈線CKL1及 CKBL1、第一電源線vddl及開始信號線STL接觸部分連結 線。如此，於製程過程中，當第二電源線VSSL、第一及第 一時脈線CKL1及CKBL1、第一電源線VDDL及開始信號線 200305848 STL形成於封合線(SA)時，TFT基板300於高溫及高壓下組 合濾色片基板之製程，可能出現接觸失敗。 接觸部分連結線之佈線形成於閘驅動區（GA)，未接觸 連結線之佈線形成於封合線區（SA)。因此，可防止LCD裝 5置整體尺寸的加大。特別，因第二電源線VSSL、第三及第 四時脈線CKL2及CKBL2其它部分未接觸連結線，故第二電 源線VSSL及第三及第四時脈線CKL2及CKBL2其它部分可 形成於封合線區（SA)。 即使第三及第四時脈線CKL2及CKBL2進一步形成於 修 1〇周邊區（PA)，LCD裝置之全部大小也不會增加。此外，因 第三及第四時脈線CKL2及CKBL2係形成於封合線區（sA， 於該封合線區未形成液晶層，故不存在有因第三及第四時 脈線CKL2及CKBL2所致之電容。因此第一及第二時脈信號 CK及CKB之延遲比第一及第二時脈線CKL^cKBL1之延 15 遲遠更降低。 筝照第13圖，第一時脈線CKL1 一端係連結至第三時脈 線CKL2-端，第三時脈線CKBL1 一端係'連結至第四時脈線 · CKBL2—端。如此，第一時脈信號(；^經由第三時脈線<：：&1^ 而供給位移暫存器之各階段，以及第二時脈信號CK係經由 20第四時脈線CKBL2而供給位移暫存器之各階段。 如第12及13圖所示，第三及第四時脈線CKL2&CKBL2 _ 未直接連接至位移暫存器151，且未交叉其它佈線。如此， 第一及第一時脈信號CK及CKB比較行進通過第一及第二 時脈線CKL1及CKBL1，可更快速行進通過第三及第四時脈 30 200305848 線CKL2及 CKBL2。 右干1¾段(SRC1，…，SRCn+Ι)係藉經由第一及第二時 脈線CKL1及CKBL1而施加至第_及第二時脈信號CK及 CKB操作，以及其它階段(SRC1，·.·，SRCn+1)係藉經由第三 5及第四時脈線CKL2及CKBL2施加至第一及第二時脈線 · CKL1及CKBL1而操作。 因此，具有高電壓位準且係循序施加至第一閘線、第 一閘線、…及第η閘線之第一及第二時脈信號⑶及CKB之延 遲可最小化，故可防止由位移暫存器各階段輸出之輸出信 鲁 10 號的失真。 第14圖為佈局圖，顯示根據本發明之第四具體實施例 之位移暫存器佈線結構，以及第15圖為佈線圖，顯示具有 第14圖之佈線結構之位移暫存器。 參照第14及15圖，供連結第二電源線VSSL至各階段之 15第一連結線VSSLc係設置於第二電源線VSSL與位移暫存器 (圖中未顯示）間。並聯第二電源線VSSL及第一及第二時脈 線CKL 1及CKBL1係設置於第二電源線VSSL與位移暫存器 籲 間。 第一連結線VSSLc交叉第一及第二時脈線CKL1及 20 CKBL1。第一及第二時脈線CKL1及CKBL1各自具有第一寬 度W1於（第一連結線VSSLc未交叉之）其第一部分，以及具 · 有寬度W2於（第一連結線VSSLc未交叉之)其第二部分。第 二寬度W2係小於第一寬度W1。 特別，第一時脈線CKL1具有第一凹部C1，係對應於第 31 200305848 一連結線VSSLc之其第二部分。第二時脈線CKLB1具有第 二凹部C2,其係對應於第一連結線vSSLc交叉之第二部分。 第一時脈線CKL1具有第一及第二側壁丨40丨及14〇2於 縱向延伸，以及第二時脈線CKBL1具有第三及第四側壁 5 1403及1404於縱向延伸。第一時脈線CKL1之第二側壁1402 面對第二時脈線CKLB1之第三側壁1403。第一凹部C1係形 成於第一側壁1401，第二凹部C2係形成於第四側壁1404。 如第14及15圖所示，對各階段提供第一時脈信號(CKL) 之第一時脈連結線CKLc係設置於第一時脈線CKL1與位移 1〇暫存器151間。對各階段提供第二時脈信號(CLB)之第二時 脈連結線CKBLc係設置於第二時脈線CKBL丨與位移暫存器 151間。第一時脈連結線CKLc接觸第一時脈線CKL1於第一 時脈線CKL 1之第二側壁1402附近。第二時脈連結線CKBLc 接觸第二時脈線CKBL1於第二時脈線CKBL1之第三側壁 15 1403附近。例如第一及第二凹部C1及C2係形成於第一及第 一時脈線CKL1及CKBL1部分，於該部分第一及第二時脈線 CKL1及CKBL1未重疊第-及第二時脈線CKLc及CKBLc。 可減少於第一及第二時脈線CK1及CKB1重疊第一連 結線VSSLc部分產生的電容。因此可減少經由第一及第二 20時脈線CKL 1及CKBL1施加至位移暫存器之第一及第二時 脈信號CK及CKB之延遲。此外，可減少經由第一連結線 VSSLc施加至位移暫存器之第二電源電壓信號vss之延遲。 因第一及第二時脈線CKL1及CKBL1之若干部分之寬 度乍（W2)，故第一及第二時脈線cki及CKB1重疊第一連結 32 200305848 線VSSLc該部分產生之電阻增高。但因信號延遲受電容影 響比受電阻影響更大，故可減少信號的延遲。 後文中’隨電阻及電容改變之RC延遲顯示於表丨實施 例及比較例。實施例中，第一及第二時脈線CKL1及CKBL1 5各自第一寬度為70微米，第一及第二時脈線CKL1及CKBL1 . 各自第二寬度(W2)為45微米。比較例中，第一及第二時脈 線CKL1及CKBL1各自之第一及第二寬度(W1、W2)為70微 米。 〈表1> 籲 CKLl(CKBLl) W1 W2 C R 比較例 70微米 70微米 385pF 457Ω 實施例 70微米 45微米 344.5pF 489Ω 如表1所示，比較例中，第一及第二時脈線(CKL1、 CKBL1)與第一連結線VSSLc間之第一電容為奶奸。實施 例中，第一及第二時脈線(CKL1、CKBL1)與第二連結線 VSSLc間之第二電容為344.5pF實施例之第二電容比比較例 之第一電容降低約10.5%。 比較例中，第一及第二時脈線(CKL1、CKBL1)之第一 電阻為457歐姆。實施例中，第一及第二時脈線(CKLi、 CKBL1)之第二電阻為489歐姆。實施例之第二電阻比比較 例之第一電阻增高約7%。但因第二電容之增加比係大於第 二電阻之增加比，故RC延遲減少。 第16圖為佈局圖顯示根據本發明之第五具體實施例之 位移暫存器之佈線結構。 芩照第14及15圖，供連結第二電源線VSSL至各階段之 33 200305848 第一連結線VSSLc係設置於第二電源線VSSL與該位移暫存 益（圖中未顯示）間。並聯第二電源線VSSL及第一及第二時 脈線CKL1及CKBL1係設置於第二電源線VSSL與位移暫: 器間。 5 第一連結線VSSLc父又第—及第二時脈線CKL1及 CKBL1。第一連結線VSSLc有第三凹部C3，其係對應於第 ^ 及日π脈線CKL1父叉之其弟二部分。第一連結線^^^^具 有第四凹部C4,其係對應於第二時脈線CKBU與其交叉之 其第四部分。第一連結線VSSLc具有第三寬度界3於（第一及 修 10第二時脈線CKL1及CKBL1並未交又之）其部分，且具有第 四寬度W4於（第一及第二時脈線CKL1及CKBL1交叉之）其 另一部分。第四寬度W4係小於第三寬度W3。 因第一連結線VSSLc具狹窄寬度，對應第一及第二時 脈線CKL1及CKBL1與其交又之部分，故可降低第一及第二 15時脈線(CKL1、CKBL1)與第一連結線VSSLc間之電容。因 此’可減少經由第一及第二時脈線CKL1及CKBU，施加至 位移暫存器之第一及第二時脈線CK及CKB之延遲。此外， 可減少經由第一連結線VSSLc施加至位移暫存器之第二電 源電壓信號VSS之延遲。 . 20 根據前述閘驅動器電路，因虛設階段(SRCn+Ι)之虛設 - 輸出端子係連結至最末驅動階段(SRCn)之控制端子，也連 結至虛設階段(SRCn+Ι)之虛設控制端子，故可防止外加至 閘驅動器電路之信號的延遲。 此外，因連結至虛設階段(SRCn+l)之控制端子之電晶 34 200305848 體結構改變，故虛設階段（SRCn+l)之輸出信號可正常輸 出，LCD裝置可提供較高顯示品質。 此外，因除了第一及第二時脈線之外，佈線部分進一 步包括第三及第四時脈線，經由該時脈線施加第一及第二 5時脈CK及CKB，故循序施加至第一、第二、…、第最末閘 線之欲具有高電壓位準之第一及第二時脈信號CK及CKB 之延遲可最小化，LCD裝置可提供較佳顯示品質。 雖然已經說明本發明之具體實施例及其優點之細節， 但須了解可未悖離如隨附之申請專利範圍界定之本發明之 · 10 精聽及範圍，於此處做出多種變化、修改及變更。 【圖式簡單說明】 第1圖為示意圖顯示根據本發明之第一具體實施例之 液晶顯不面板； 第2圖為方塊圖顯示第1圖之驅動閘驅動器電路之位移 15 暫存器； 第3圖為電路圖顯示第2圖之驅動階段； 第4圖為平面圖顯示第3圖之驅動階段之佈局； 鲁 第5圖為電路圖顯示第2圖之虛設階段； 第6圖為平面顯示第5圖之虛設階段佈局； 20 第7圖為線圖顯示虛設階段輸出信號波形，該虛設階段 具有第2圖驅動階段之相同電路； 第8圖為線圖顯示第5圖之虛設階段輸出信號波形； 第9圖為電路圖顯示根據本發明之第二具體實施例之 驅動階段及虛設階段； 35 200305848 第ίο圖為方塊圖顯示根據本發明之第三具體實施例， 供驅動閘驅動器電路之位移暫存器； 第11圖為線圖顯示第10圖之閘驅動器電路之輸出信號 波形； 5 第12圖為佈局圖顯示第10圖之閘驅動器電路之第三及 第四時脈線配置； 第13圖為佈局圖顯示位移暫存器之第一、第二及第四 時脈線間之連結之另一範例；Referring to FIG. 10, the inter-drive circuit 150 according to the third embodiment of the present invention includes a displacement register 151. The displacement register 151 is divided into a group G1 and a second group G2. The first and second groups ⑴ and ⑺ each include several stages. The wiring section 152 is provided with the shift register i5i. The line portion 152 provides a plurality of signals to the displacement register 151. In detail, the line portion 152 includes a start signal line (STL), a first power supply (VDDL), a clock-keeping line (CKL1), _ second clock line (cm), 24 200305848 first power line (VSSL ), A third clock line (CKL magic and fourth clock line (CKBL2) 〇 a first clock signal (CK) is added to the first group G1 drive stage through the first clock line (CKL1) (SRC1, ... ,, SRci-D's odd-numbered drive stage 5 (SRC1, ..., SRC3). The first clock signal (CK) is driven via the third clock line. (CKL2) is added to the drive of the second group g2 Phase (SRCi, ..., SRCn) is an odd-numbered driving phase (SRCi + 1). The first clock signal (CKB), which differs from the first clock signal (CK) by 80 degrees, passes through the second clock line ( CKBL1), which is added to the even-numbered driving phase of the first group G1 driving phase (SRC1, ..., SRCM) Lu 10 (SRC2, ...). The second clock signal (CKB) is obtained via the fourth clock signal (CKBL2). The even-numbered driving phases (SRCi, ..., SRCn;) added to the second group of G2 · moving phases (SRCi, ..., SRCn). Thus, some parts of the n-driven phase (SRC1, ..., SRCn) respond to the first First and first clock signals CK and CK B, the first and second clock signals CK 15 and CKB are applied to the n driving phase (SRC1, ..., SRCn) via the first and second clock lines CKL1 and CKBL1, respectively!! The driving phase (SRC1, …, SRCn) The other parts are in response to the first and second clock signals CK and _ CKB, and the first and second clock signals ck and CKB pass through the third and fourth day clock lines CKL2 and CKBL2, respectively. It is applied to the n driving stage (srcI, ..., 20 SRCn). Therefore, the ON voltage level is sequentially applied to the first gate line, the second gate line, ..., and the first and second clocks of the nth gate line. The delay of the signals CK and cKB-is minimized, so that distortion of the output signal output from each stage can be prevented. The third and fourth clock lines CKL2 and CKBL2 do not cross other wiring 25 200305848 (VSSL ·, VDDL, STL, etc.) Therefore, it is connected to each driving phase of the n driving phase (SRC1, ..., SRCn). The third and fourth clock lines CKL2 and CKBL2 are connected to the ends of the first and second clock lines CKL1 & CKBU, respectively. The first and second clock lines CKL1 and CKBL1 are to be connected to each of the n driving stages 5 (SRC1, ..., SRCn) Phase. In particular, where the first end of the first clock signal CK to the third clock line CKL2 is input, the first end of the clock signal CK is input to the first end of the first clock line CKL1. (In which the second clock signal ^^ is input) The first end of the second clock signal CKBL1 is disposed adjacent to (where the second 10 clock signal CKB is input) the first end of the fourth clock. In other words, the input terminals of the first, second, third and fourth clock lines (CKU, CKB, CKL2, CKBL2) are set to be adjacent to the first driving stage (SRC1). The second end of the first clock line CKL1 is near the dummy phase (SRCn + 1) and is connected to the second end of the third clock line CKL2. 15 The third and fourth clock lines CKL2 and CKBL2 are not directly connected to the displacement register 151, and no other wiring is passed. In this way, the first and second clock signals CK and CKB can travel through the third and fourth clock lines CKL2 and CKBL2 faster than the first and second clock lines CKL1 and _CKBL1 '. -° In addition, the narrower the wiring width, the closer the displacement register 151 is to the wiring. · In particular, the setting of the start signal line STL is closest to the shift register 15 丨, and · After the start of the signal line S TL, the first power line VDDL is set next. After the first power line VDDL, the first and second clock lines CK1 and CKBL1 are sequentially disposed. A second power line VSSL is provided after the first clock line CKL1. Second power line 26 200305848 After VSSL, set the third clock line CKL2. After the third clock line CKL2, a fourth clock line CKBL2 is set. Since the wiring of the wiring portion 152 is arranged in the aforementioned order, the LCD device can know that the display quality is relatively low. The wiring arrangement is relatively close to the displacement register 5 151, so the total contact area between wirings is large, and the contact capacitance between wirings is large. Therefore, the wiring is less affected by the capacitance between the wirings, so the displacement register 151 is disposed closer to the wiring. Therefore, the LCD device can provide higher display quality. Referring to FIG. 11, the first and second clock signals CK and CKB are supplied to the displacement register 151 to the first group G1 via the tenth and second clock lines CKL1 and CKBL1. When the start signal ST is applied to the first drive stage SRC1 of the first group, 'the first drive stage is 8 feet (^ in response to the start signal st, and the first output signal OUT1 is output which has a height higher than that of the first clock signal CK) Voltage level. Then the 'second driving stage SRC2 responds to the first output signal OUT1 of the first driving stage SRC1 15 and outputs a second output signal OUT2, which has a high voltage level higher than the second clock signal CKB. When the first and second clock signals CK and CKB are supplied to the displacement register 151 to the second group G2 through the third and fourth clock lines CKL2 and CKBL2, the i-th driving stage SRCi is also the second group G2. The first driving phase is in response to the (i-1) th output signal OUTi-1 of the SRCi-I driving phase 20i), and the first output signal OUTi is output, which has the high voltage of the second clock signal CKB Level. Then, the (i + 1) th driving stage SRCi + 1 responds to the (i) th output signal OUTi of the first driving stage SRCi, and outputs the (i + 1) th output signal OUT + i, which has a first clock High voltage level of signal CK. 27 200305848 As Yuwen explained, the first, second, and (n) output signals (〇UTl, OUT2 '..., OUTn) are output in sequence, and the output terminals output at each driving stage have high voltage levels. Figure U is a layout diagram showing the third and fifth fourth-day pulse line configurations of the gate drive circuit of Figure 10, and Figure 13 is a layout diagram showing the first, third, second, and Another example of connection between the fourth clock line. See Figure 12. 'Start signal line STL, first power line VDDL, first and second clock lines CKL1 and CKBL1, second power line VSSL, third and fourth day clock line CKL2 and CKBL2 are sequential Set next to the shift register 151_10. The narrower the width of each wiring, the closer the displacement register 151 is arranged to the wiring. In other words, the wiring width away from the displacement register 151 is not smaller than the wiring width provided near the displacement register 151. The closer the wiring setting is to the temporary storage behavior, the larger the total contact area between the wirings and the larger the capacitance between the wirings that are in contact with each other. Therefore, the wiring is less affected by the capacitance between the wirings, and the wiring arrangement 15 is closer to the displacement register 151. In particular, the setting of the start signal line STL is closest to the displacement register 15m. After the start of the signal line STL, the first power line is set. After the first power line VDDL, the first and second clock lines (:: 10 and (: 1 ^ 1 ^) are sequentially set. The second clock line CKL1 is set closer to the displacement than the first clock line CKU. Store 20 states 151. The first clock line CKL1 is followed by the second power line VSSL. Therefore, this can reduce the wiring and connection lines [for connecting this wiring to each stage (SRC1, ...,. SRCn + 1 )] The signal delay caused by the capacitor is reduced. The third and fourth clock lines CKL2 and CKBL2 do not cross other wiring (VSSL, vDDL, stl, etc.), so they are connected to the displacement register 151. Because of the third and fourth Clock line 0 feet 1 ^ and 28 200305848 The ends of CKBL2 are respectively connected to the ends of the first and first clock lines CKL1 and CKBL1 to be connected to the displacement register, so the third and fourth clock lines CKL2 and CKBL2 are set It is farther away from the displacement register than the second power line VSSL. In other words, the third and fourth clock lines CKL2 and CKBL2 are arranged outside the second power line 5 VSSL. As shown in FIG. The four-clock line CKL2 & CKBL2 is formed on the sealing line area (sa) of the TFT substrate 300. The TFT substrate 300 is divided into a display area (DA) and a ring Around the peripheral area (PA) of the display (DA). Gate lines (not shown), data lines (not shown), and pixels (not shown) are formed in the display area (DA). 10 Peripherals The area (PA) is divided into a gate driving area (GA) and a sealing line area (sA). BitPrivate temporary storage # 151 and each wiring system are formed in the gate driving area (〇Α). It is used to join the TFT substrate and the color filter The sealing agent (not shown) of the substrate (not shown) is formed in the sealing line area (SA). The partial sealing line area (SA) and the partial gate driving area (GA) overlap each other. The sealing line area (SA) is divided into a first region and a second region 15. The liquid crystal layer is formed in the first region of the seal line region (SA), and the liquid crystal layer is not formed in the second region of the seal line region (SA). The driving area (ga) includes a first area. The third and fourth clock lines CKL2 and CKBL2 and a part of the second power line VSSL are formed on the sealing line (SA). The second power line VSSL, the first and the second The clock lines CK L1 and CKB L1 and other parts 20 of the start signal line STL are formed in the gate driving area (GA). Part of the second power supply line VSSL, the first and second clock lines CKL1 and CKBL1, A power line vddl and the start signal line STL contact part of the connection line. Thus, during the manufacturing process, when the second power line VSSL, the first and first clock lines CKL1 and CKBL1, the first power line VDDL, and the start signal line 200305848 When the STL is formed on a sealing line (SA), the process of combining the color filter substrate with the TFT substrate 300 under high temperature and high pressure may cause contact failure. The wiring of the contact portion of the contact portion is formed in the gate driving area (GA), and the wiring of the contact portion not in contact is formed in the seal line area (SA). Therefore, an increase in the overall size of the LCD device can be prevented. In particular, since the other parts of the second power line VSSL, the third and fourth clock lines CKL2, and CKBL2 are not in contact with the connection line, the second power line VSSL and the other parts of the third and fourth clock lines CKL2 and CKBL2 may be formed on Sealing Line Area (SA). Even if the third and fourth clock lines CKL2 and CKBL2 are further formed in the peripheral area (PA), the overall size of the LCD device will not increase. In addition, since the third and fourth clock lines CKL2 and CKBL2 are formed in the seal line area (sA), and no liquid crystal layer is formed in this seal line area, there are no third and fourth clock lines CKL2 and The capacitance caused by CKBL2. Therefore, the delay of the first and second clock signals CK and CKB is much lower than the delay of the first and second clock lines CKL ^ cKBL1. 15 The first clock One end of the line CKL1 is connected to the third clock line CKL2-, and one end of the third clock line CKBL1 is' connected to the fourth clock line · CKBL2—end. Thus, the first clock signal (; ^ passes through the third clock Pulse line < :: & 1 ^ and each stage of the displacement register is supplied, and the second clock signal CK is provided at each stage of the displacement register via the 20th fourth clock line CKBL2. As shown in FIG. 13, the third and fourth clock lines CCK2 & CKBL2 _ are not directly connected to the displacement register 151 and do not cross other wiring. In this way, the first and first clock signals CK and CKB pass through the first and second clock signals. The first and second clock lines CKL1 and CKBL1 can travel faster through the third and fourth clock 30 200305848 lines CKL2 and CKBL2. Right stem 1¾ section ( SRC1, ..., SRCn + 1) are applied to the _ and 2nd clock signals CK and CKB through the first and second clock lines CKL1 and CKBL1, and other phases (SRC1, ..., SRCn + 1) It is operated by applying to the first and second clock lines · CKL1 and CKBL1 via the third 5 and fourth clock lines CKL2 and CKBL2. Therefore, it has a high voltage level and is sequentially applied to the first gate line The delays of the first and second clock signals ⑶ and CKB of the first gate line, the nth gate line, and the CKB can be minimized, so that the distortion of the output signal No. 10 output by each stage of the displacement register can be prevented. FIG. 14 is a layout diagram showing a wiring structure of a displacement register according to a fourth embodiment of the present invention, and FIG. 15 is a wiring diagram showing a displacement register having a wiring structure of FIG. 14. Referring to 14 And Figure 15, for connecting the second power line VSSL to each stage, the 15 first connection line VSSLc is installed between the second power line VSSL and a displacement register (not shown). Parallel the second power line VSSL and the first The first and second clock lines CKL1 and CKBL1 are disposed between the second power line VSSL and the displacement register. The first connection line VSSLc crosses the first and second clock lines CKL1 and 20 CKBL1. The first and second clock lines CKL1 and CKBL1 each have a first width W1 (the first connection line VSSLc does not cross) in the first portion thereof And has a width W2 in (the first connecting line VSSLc does not cross) its second part. The second width W2 is smaller than the first width W1. In particular, the first clock line CKL1 has a first recessed portion C1, which corresponds to the second part of the 31st 200305848-th connection line VSSLc. The second clock line CKLB1 has a second concave portion C2, which corresponds to a second portion where the first connection line vSSLc crosses. The first clock line CKL1 has first and second side walls 40 and 140 extending longitudinally, and the second clock line CKBL1 has third and fourth side walls 5 1403 and 1404 extending longitudinally. The second sidewall 1402 of the first clock line CKL1 faces the third sidewall 1403 of the second clock line CKLB1. The first recessed portion C1 is formed on the first side wall 1401, and the second recessed portion C2 is formed on the fourth side wall 1404. As shown in FIGS. 14 and 15, the first clock connection line CKLc that provides the first clock signal (CKL) to each stage is disposed between the first clock line CKL1 and the displacement 10 register 151. A second clock connection line CKBLc that provides a second clock signal (CLB) to each stage is disposed between the second clock line CKBL and the displacement register 151. The first clock connection line CKLc contacts the first clock line CKL1 near the second side wall 1402 of the first clock line CKL1. The second clock connection line CKBLc contacts the second clock line CKBL1 near the third side wall 15 1403 of the second clock line CKBL1. For example, the first and second recesses C1 and C2 are formed on the first and first clock lines CKL1 and CKBL1, and the first and second clock lines CKL1 and CKBL1 do not overlap the first and second clock lines. CKLc and CKBLc. It is possible to reduce the capacitance generated when the first and second clock lines CK1 and CKB1 overlap the portion of the first connection line VSSLc. Therefore, the delays of the first and second clock signals CK and CKB applied to the displacement register via the first and second 20 clock lines CKL 1 and CKBL1 can be reduced. In addition, the delay of the second power supply voltage signal vss applied to the displacement register via the first connection line VSSLc can be reduced. Due to the width of some parts of the first and second clock lines CKL1 and CKBL1 (W2), the first and second clock lines cki and CKB1 overlap the first connection 32 200305848 The resistance generated by this part of line VSSLc increases. However, because the signal delay is more affected by capacitance than resistance, it can reduce the signal delay. In the following, the RC delay as a function of resistance and capacitance is shown in Table 丨 Examples and Comparative Examples. In the embodiment, the first and second clock lines CKL1 and CKBL1 5 each have a first width of 70 micrometers, and the first and second clock lines CKL1 and CKBL1. Each of the second width (W2) is 45 micrometers. In the comparative example, the first and second widths (W1, W2) of the first and second clock lines CKL1 and CKBL1 are 70 micrometers, respectively. <Table 1> CKLl (CKBLl) W1 W2 CR Comparative Example 70 microns 70 microns 385pF 457Ω Example 70 microns 45 microns 344.5pF 489Ω As shown in Table 1, in the comparative example, the first and second clock lines (CKL1, CKL1, The first capacitor between CKBL1) and the first connection line VSSLc is a gangster. In the embodiment, the second capacitance between the first and second clock lines (CKL1, CKBL1) and the second connection line VSSLc is 344.5 pF. The second capacitance of the embodiment is approximately 10.5% lower than the first capacitance of the comparative example. In the comparative example, the first resistances of the first and second clock lines (CKL1, CKBL1) were 457 ohms. In the embodiment, the second resistance of the first and second clock lines (CKLi, CKBL1) is 489 ohms. The second resistance of the example is increased by about 7% compared with the first resistance of the comparative example. However, because the increase ratio of the second capacitor is greater than the increase ratio of the second resistor, the RC delay is reduced. Fig. 16 is a layout diagram showing a wiring structure of a displacement register according to a fifth embodiment of the present invention.芩 According to Figures 14 and 15, for connecting the second power line VSSL to each stage 33 200305848 The first connection line VSSLc is installed between the second power line VSSL and the temporary storage benefit (not shown). The second power line VSSL and the first and second clock lines CKL1 and CKBL1 are connected in parallel between the second power line VSSL and the displacement device. 5 The first connection line VSSLc is the first and second clock lines CKL1 and CKBL1. The first connection line VSSLc has a third concave portion C3, which corresponds to the second part of the parent fork of the ^ th and the day π pulse line CKL1. The first connection line ^^^^ has a fourth concave portion C4, which corresponds to the fourth portion of the second clock line CKBU crossing it. The first connection line VSSLc has a third width boundary 3 in (the first and second 10 clock lines CKL1 and CKBL1 are not overlapped) and part thereof, and has a fourth width W4 in (the first and second clocks) Lines CKL1 and CKBL1 cross one another). The fourth width W4 is smaller than the third width W3. Because the first connection line VSSLc has a narrow width, corresponding to the first and second clock lines CKL1 and CKBL1 intersecting with it, the first and second 15 clock lines (CKL1, CKBL1) and the first connection line can be reduced. Capacitor between VSSLc. Therefore, the delay of the first and second clock lines CK and CKB applied to the displacement register via the first and second clock lines CKL1 and CKBU can be reduced. In addition, the delay of the second power voltage signal VSS applied to the displacement register via the first connection line VSSLc can be reduced. . 20 According to the aforementioned gate driver circuit, the dummy-output terminal of the dummy phase (SRCn + 1) is connected to the control terminal of the last drive phase (SRCn), and is also connected to the dummy control terminal of the dummy phase (SRCn + 1). Therefore, a delay of a signal applied to the gate driver circuit can be prevented. In addition, because the structure of the transistor 34 200305848 connected to the control terminal of the dummy phase (SRCn + l) changes, the output signal of the dummy phase (SRCn + l) can be normally output, and the LCD device can provide higher display quality. In addition, since the wiring portion further includes the third and fourth clock lines in addition to the first and second clock lines, the first and second 5 clocks CK and CKB are applied via the clock line, so they are sequentially applied to The delays of the first and second clock signals CK and CKB which are to have high voltage levels for the first, second, ..., and last gate lines can be minimized, and the LCD device can provide better display quality. Although the specific embodiments of the present invention and the details of its advantages have been explained, it must be understood that the present invention, as defined by the scope of the attached patent application, does not deviate. 10 Intensive listening and scope, various changes and modifications are made here. And changes. [Brief description of the drawings] FIG. 1 is a schematic diagram showing a liquid crystal display panel according to a first embodiment of the present invention; FIG. 2 is a block diagram showing a displacement 15 register of the driving gate driver circuit of FIG. 1; Figure 3 is a circuit diagram showing the driving stage of Figure 2. Figure 4 is a plan view showing the layout of the driving stage of Figure 3. Lu Figure 5 is a circuit diagram showing the dummy stage of Figure 2. Figure 6 is a plane display of Figure 5. The layout of the dummy phase; 20 Figure 7 is a line diagram showing the output signal waveform of the dummy stage, which has the same circuit as the driving stage of Figure 2; Figure 8 is a line diagram showing the output signal waveform of the dummy stage of Figure 5; Fig. 9 is a circuit diagram showing a driving stage and a dummy stage according to a second embodiment of the present invention; 35 200305848 Fig. 8 is a block diagram showing a displacement register for driving a gate driver circuit according to a third embodiment of the present invention ; Figure 11 is a line chart showing the output signal waveform of the gate driver circuit of Figure 10; 5 Figure 12 is a layout chart showing the third and fourth clock lines of the gate driver circuit of Figure 10 Set; FIG. 13 shows another exemplary graph of the first layout, the coupling between the second and the fourth clock line of the shift register;
第14圖為佈局圖顯示根據本發明之第四具體實施例之 10 位移暫存器之佈線結構； 第15圖為佈局圖顯示具有第14圖之佈線結構之位移暫 存器；以及 第16圖為佈局圖顯示根據本發明之第五具體實施例， 位移暫存器之佈線結構。 15 【圖式之主要元件代表符號表】 100.. .TFT 基板 110.. .薄膜電晶體 120.. .像素電極 130.. .閘驅動器電路 131.. .位移暫存器 131a...升高部分 131b...下降部分 131c...升高驅動器部分 131d...下降驅動器部分 131e...載流輸出部分 132.. .佈線部分 133a...升高部分 133b...下降部分 133c...升高驅動器部分 133d...下降驅動器部分 133e...載流輸出部分 140·.·貧料驅動電路 150.. .閘驅動器電路FIG. 14 is a layout diagram showing a wiring structure of a 10-bit displacement register according to a fourth embodiment of the present invention; FIG. 15 is a layout diagram showing a displacement register having a wiring structure of FIG. 14; and FIG. 16 A layout diagram showing a wiring structure of a displacement register according to a fifth embodiment of the present invention. 15 [Schematic representation of the main components of the diagram] 100 .. .. TFT substrate 110... Thin film transistor 120... Pixel electrode 130... Gate driver circuit 131... High part 131b ... Descent part 131c ... Elevated driver part 131d ... Descent driver part 131e ... Current carrying output part 132 .... Wiring part 133a ... Elevated part 133b ... Descent part 133c ... up driver section 133d ... down driver section 133e ... current-carrying output section 140 ... lean driver circuit 150 ... gate driver circuit
36 200305848 151...位移暫存器 STL...開始信號線 152...佈線部分 VDDL…第一電源線 200...液晶顯不面板 CKL...第一時脈線 DA...顯不區 CKBL…第二時脈線 PA...周邊區 VSSL…第二電源線 SA...封合線區 VDD...第一電源電壓信號 GA...閘驅動區 VSS...第二電源電壓信號 DL...資料線 CK...第一時脈信號 GL...閘線 CKB...第二時脈信號 CT...控制端子 CKT…時脈端子 SRC...驅動階段 VDDT…第一電源線端子 CR...載流端子 VSST...第二電源線端子 IN...輸入端子 N.··節點 ST...開始信號 NT...NMOS電晶體 OUT...輸出端子 G·.·組 3736 200305848 151 ... Displacement register STL ... Start signal line 152 ... Wiring section VDDL ... First power line 200 ... LCD display panel CKL ... First clock line DA ... Display area CKBL ... Second clock line PA ... Peripheral area VSSL ... Second power supply line SA ... Sealed line area VDD ... First power supply voltage signal GA ... Gate drive area VSS ... Second power supply voltage signal DL ... data line CK ... first clock signal GL ... brake line CKB ... second clock signal CT ... control terminal CKT ... clock terminal SRC ... Drive stage VDDT ... first power line terminal CR ... current-carrying terminal VSST ... second power line terminal IN ... input terminal N .... node ST ... start signal NT ... NMOS transistor OUT ... output terminal G ... group 37