TWI420452B - Shift register for display panel - Google Patents

Description

Shift register for display panel

The present invention relates to a driving circuit, and more particularly to a shift register for a display panel.

Referring to Figure 1, there is shown a conventional shift register for a liquid crystal display. The shift register 9 includes a plurality of serially connected driver stages 91; each of the driver stages 91 has an input and an output, and the output of each driver stage 91 is coupled to the input of its next driver stage and A scan line of a liquid crystal display. Each driver stage 91 further receives two clock signals having phase differences generated by a clock generator, and each driver stage 91 and its adjacent driver stages receive different sets of clock signals.

Please refer to Figures 2 and 3 at the same time. Figure 2 shows the circuit diagram of the one-stage driver stage of the shift register of Figure 1, and Figure 3 shows the operation timing diagram of the one-level driver stage of Figure 2. The first stage driver stage 91 will be described below.

During the first period t ₁ , a high level input signal Input is input to the input terminal to turn on the switching elements SW ₃ and SW ₆ , the potential of the node P is charged to a high level, and the switching element SW ₁ is turned on to couple the clock signal CLK. _{From 1} to output 1, since the clock signal CLK ₁ is at a low level, the potential of the output terminal 1 is at a low level. During the first period t ₁ , since the clock signal CLK ₃ is at a high level and the switching element SW ₅ is turned on, the current will flow from the power source V _DD to the power source Vss to consume unnecessary current; here, the switching element SW ₆ is It is designed to be much larger than the switching element SW ₅ , so that the potential of the node P ' can be discharged to a low level to turn off the switching elements SW ₂ and SW ₄ .

During the second period t ₂ , the input terminal is switched to the low level and the switching elements SW ₃ and SW ₆ are turned off. The clock signal CLK _{3 is} switched to a low level to turn off the switching element SW ₅ . The node P ' is not charged, so its potential remains at a low level and the switching elements SW ₂ and SW ₄ are turned off. The clock signal CLK _{1 is} converted to a high level, and the potential of the node P is increased by the coupling effect of the clock signal CLK ₁ and the stray capacitance (about 90% of the potential change of the clock signal CLK ₁ ); therefore, the node P remains the high level and turns on the switch element SW _1, the clock signal CLK of _a high level is coupled to the output of an output terminal outputting an output signal of a high level in this period.

During the third period t ₃ , the input terminals are still at a low level such that the switching elements SW ₃ and SW ₆ remain off. The clock signal CLK _{3 is} still at a low level while maintaining the off state of the switching element SW ₅ . The potential of the node P ' remains at the low level and the switching elements SW ₂ and SW ₄ are turned off. When the clock signal CLK ₁ is converted to the low level and the potential of the node P (about 90% change in the potential of the clock signal CLK ₁₎ down through the coupling effect of the clock signal CLK _1, but no node P through the discharge path while still others The switching element SW ₁ is turned on while maintaining the high level, and the low level of the clock signal CLK ₁ is coupled to the output terminal 1.

During the fourth period t ₄ , the input terminal is maintained at a low level to turn off the switching elements SW ₃ and SW ₆ and the switching element SW ₅ is turned on because the clock signal CLK _{3 is} again converted to a high level, and the node P ′ is converted to the high level. The switching elements SW ₂ and SW ₄ are turned on; therefore, both the node P and the output 1 are coupled to the power source Vss and discharged to a low level.

Then, in each period after the fourth period t ₄ , the clock signals CLK ₁ to CLK ₃ are sequentially converted into high-level pulses in the continuous period, as shown in FIG. 3 . When the power supply V _{DD is} converted to the high level at the input end, the clock signal CLK ₃ is coupled to the power supply Vss via the node P ′ , and the output terminal 1 is not connected to any power supply, which causes the output potential to float and is prone to occur. The situation of malfunction.

In view of the above, it is necessary to propose a new shift register for a display panel to solve or reduce the problem of floating at the output and consuming extra power in the conventional circuit.

The invention provides a shift register for a display panel, the output end of the shift register has a short floating time, and the shift register can effectively reduce the chopping of the output signal.

The invention proposes a shift register for a display panel comprising a plurality of serially connected driver stages. Each driver stage includes an input terminal, an output terminal, a charging unit, a discharge unit, and a charging driving unit. The charging unit charges a first clock signal to the output terminal according to a potential of the first node. The discharge unit is based on a second The clock signal simultaneously discharges the first node and the output and discharges the output according to a third clock signal. The charging driving unit controls the potential of the first node according to the input terminal and the potential of the third clock signal.

Each of the driving stages of the shift register of the present invention further includes a compensation unit coupled between the first clock signal, the first node, the charging unit and the output terminal for use in the driving stage When the output terminal is at a low level and the first clock signal is at a high level, the continuous wave of the output terminal is reduced.

The invention further provides a shift register for a display panel comprising a plurality of serially connected driving stages, each driving stage comprising an input end, an output end, a first switch, a second switch, and a third switch a fourth switch, a fifth switch and a sixth switch. The first switch has a first end coupled to a second node, a second end coupled to the output end and a control end coupled to the first node. The second switch has a first end and a control end coupled to the input end and a second end coupled to the first node. The third switch has a first end coupled to the output end, a second end coupled to a power source, and a control end receiving a second clock signal. The fourth switch has a first end coupled to the first node, a second end coupled to the power source, and a control end receiving the second clock signal. The fifth switch has a first end coupled to the output end, a second end coupled to the power source, and a control end receiving a third clock signal. The sixth switch has a first end coupled to the input The second end is coupled to the first node and the control end receives the third clock signal.

In another embodiment of the present invention, the shift register for the display panel further includes a seventh switch and an eighth switch. The seventh switch has a first end receiving the first clock signal, a second end coupled to the second node, and a control end coupled to the first node. The eighth switch has a first end coupled to the first node, a second end coupled to the output end, and a control end receiving the first clock signal.

The invention further provides a shift register for a display panel comprising a plurality of serially connected driving stages, each driving stage comprising an input end, an output end, a charging unit, a discharge unit, a charging driving unit and a Compensation unit. The charging unit is configured to cause a second node to charge the output terminal according to a potential of the first node. The discharge unit is configured to discharge the first node and the output end according to at least one clock signal. The charging driving unit is configured to control the potential of the first node according to the input end and the potential of the clock signal. The compensation unit is coupled between the first clock signal, the first node, the second node, and the output end; the compensation unit includes a seventh switch and an eighth switch, wherein the seventh switch has a first end receives a first clock signal, a second end is coupled to the second node, and a control end is coupled to the first node; the eighth switch has a first end coupled to the first node, and a first end The second terminal is connected to the output end and the control end receives the first clock signal; wherein the second section of each driver stage The point is coupled to the input of the next driver stage.

In the shift register of the display panel of the present invention, when each driver stage receives three clock signals having a phase difference, the output terminal is only about 33.3% of the time is floating; when each driver stage receives When two clock signals with phase difference are used, the output is only about 50% of the time is floating. The present invention also incorporates a compensation unit at each driver stage to eliminate the problem of floating output signals.

The above and other objects, features, and advantages of the present invention will become more apparent from the accompanying drawings. In the description of the present invention, the same components are denoted by the same reference numerals and will be described in the foregoing.

Referring to FIG. 4, there is shown a shift register for a display panel according to a first embodiment of the present invention. The shift register 10 includes a plurality of drive stages 11 that are serially connected and substantially identical. Each of the driver stages 11 includes an input terminal 111 and an output terminal 112 for receiving an input signal INPUT. The output terminal 112 is configured to output an output signal OUTPUT to a display panel (not shown). The scan line is coupled to the input terminal 111 of the next driver stage 11, that is, the output signal OUTPUT outputted by each driver stage 11 is simultaneously used as the scan signal and the input signal INPUT of the next driver stage. Each driver stage 11 receives three clock signals CLK ₁ ~ CLK ₃ with phase differences. The first to third clock signals CLK ₁ to CLK ₃ are provided by a clock generator 20, which may or may not be included in the shift register 10. Further, in the description of the present invention, the high level may be, for example, 15 volts, and the low level may be, for example, -10 volts, but the present invention is not limited thereto.

Referring to FIG. 5, there is shown a circuit diagram of the first stage driver stage 11 of the shift register for a display panel of the present invention. The driving stage 11 includes an input end 111, an output end 112, a charging unit 113, a charging driving unit 114 and a discharging unit 115.

The charging unit 113 is configured to charge the output terminal 112 by a clock signal according to the potential of a node to output an output signal of a high level. The charging unit 113 includes a first switch T ₁ and a first capacitor C ₁ ; the first switch T ₁ has a first end receiving a first clock signal CLK ₁ and a second end coupled to the output end 112 And a control end coupled to the first node P ₁ . When the first node P ₁ is at a high level and the first switch T _{1 is} turned on, if the first clock signal CLK _{1 is} simultaneously at a high level, the potential of the output terminal 112 will be charged to a high level. The first capacitor C _{1 is} coupled between the control end and the second end of the first switch T ₁ for reducing the ripple caused by the coupling effect when the output signal OUTPUT is outputted at the low level of the driving stage 11 . It must be emphasized that the first capacitance C ₁ can be omitted according to different embodiments.

The charging driving unit 114 is configured to control the potential of the first node P ₁ to drive the charging unit 113 according to the potential of the input terminal 111 and a third clock signal CLK ₃ . The charging driving unit 114 has a first node P _{1 for} controlling the opening or closing of the first switch T ₁ in the charging unit 113. The charging driving unit 114 includes a second switch T ₂ and a sixth switch T ₆ . The second switch T ₂ has a first end and a control end coupled to the input end 111 and a second end coupled to the first node P ₁ . T ₆ of the sixth switch having a first terminal coupled to the input terminal 111, a second terminal coupled to the first points P _1, and a control terminal receiving the third clock signal CLK _3.

The discharge unit 115 is configured to discharge the first node P ₁ and the output terminal 112 according to a second clock signal CLK ₂ and the third clock signal CLK ₃ to eliminate the first node P ₁ and the output end. 112 is a floating condition when the first clock signal CLK ₁ is at a low level. The discharge unit 115 includes a third switch T ₃ , a fourth switch T _{4 ,} and a fifth switch T ₅ . The first end and the second end of the third switch T ₃ are respectively coupled to the first end and the second end of the fifth switch T ₅ , and the first ends of the third switch T ₃ and the fifth switch T ₅ are coupled the output terminal 112, a second terminal coupled to a power supply Vss; the third switch control terminal T ₃ of the second received clock signal CLK _2, the control terminal of the fifth switch _{T. 5} receives the third clock signal CLK ₃ . The fourth switch T ₄ has a first end coupled to the first node P ₁ , a second end coupled to the power source Vss , and a control terminal receiving the second clock signal CLK ₂ . The power supply Vss such as, but not limited to, may be -10 volts, which for the first points P ₁ and the output port 112 to the discharge.

The first to sixth switches T ₁ to T ₆ may be, for example, thin film transistors (TFTs) and have the same conductivity type (for example, an N-type transistor). The first to sixth switches T ₁ to T ₆ can be directly formed on a glass substrate by using an amorphous silicon thin film transistor process.

Please refer to FIG. 6 and FIG. 7 at the same time, FIG. 6 shows an operation timing diagram of the shift register; FIG. 7 shows an operation diagram of the one-stage driver stage of the shift register.

During the first period t ₁ , the charging driving unit 114 receives a high-level pulse of the input signal INPUT from the input terminal 111 and receives the third clock signal CLK ₃ through the control terminal of the sixth switch T ₆ . High level pulse. At this time, the switches T ₂ and T _{6 of} the charging driving unit 114 are all turned ON, and the potential of the first node P ₁ is charged to a high level to turn on the first switch T _{1 of} the charging unit 113. The third clock signal CLK ₃ simultaneously turns on the fifth switch T _{5 of} the discharge unit 115 to couple the output terminal 112 to the power source Vss. The potential of the first clock signal CLK ₁ is at a low level, so the potential of the output terminal 112 is at a low level during this period. In addition, the third switch T ₃ and the fourth switch T _{4 are} kept off (OFF) because the second clock signal CLK ₂ is at a low level.

During the second period t ₂ , both the input signal INPUT and the third clock signal CLK ₃ are converted to a low level to turn off the switches T ₂ , T _{6 of} the charging driving unit 114 and the fifth switch T _{5 of} the discharging unit 115. The second clock signal CLK _{2 is} still maintained at a low level to turn off the switches T ₃ , T _{4 of} the discharge unit 115. The first clock signal CLK _{1 is} converted to a high level at this time, causing the potential of the first node P ₁ to be further pulled up by the coupling effect of the first clock signal CLK ₁ and the stray capacitance to be maintained at the high standard. The first switch T _{1 is} turned on, so that the output terminal 112 is charged to the high level by the first clock signal CLK ₁ and outputs a high-level output pulse signal to scan a display panel (not shown). Line or input 111 of the next driver stage 11.

During the third period t ₃ , the input signal INPUT and the third clock signal CLK ₃ remain at the low level to turn off the switches T ₂ and T _{6 of} the charging driving unit 114 and the fifth switch T _{5 of} the discharging unit 115. The second clock signal CLK _{2 is} converted to a high level to turn on the switches T ₃ , T _{4 of} the discharge unit 115 such that the first node P ₁ and the output terminal 112 are coupled to the power source V _SS . Thus, the output signal 112 outputs the low level of the output terminal; the charge driving unit 114 of the first node P ₁ is discharged to the low level to close the first switch T _1.

During the fourth period t ₄ , the input signal INPUT remains at the low level and the second switch T _{2 of} the charging drive unit 114 is turned off. The second clock signal CLK _{2 is} converted to a low level to turn off the switches T ₃ , T _{4 of} the discharge unit 115. The third clock signal CLK _{3 is} converted to a high level to turn on the sixth switch T _{6 of} the charging driving unit 114 such that the first node P ₁ remains at a low level and the first switch T _{1 is} turned off; The third clock signal CLK ₃ simultaneously turns on the fifth switch T _{5 of} the discharge unit 115 such that the output terminal 112 is coupled to the power source Vss.

During the fifth period t ₅ , the input signal INPUT remains at the low level and the second switch T _{2 of} the charging drive unit 114 is turned off. The second clock signal CLK _{2 is} still maintained at a low level to turn off the switches T ₃ , T _{4 of} the discharge unit 115. The third clock signal CLK _{3 is} switched to a low level to turn off the sixth switch T _{6 of} the charging driving unit 114 and the fifth switch T _{5 of} the discharging unit 115. The first clock signal CLK _{1 is} converted to a high level, and the first node P ₁ is chopped by the coupling effect of the first clock signal CLK ₁ and the stray capacitance to turn on the first switch T ₁ , thereby causing the The output 112 also exhibits chopping as shown in FIG. As described above, the chopping of the first node P ₁ can be reduced by coupling the first capacitor C ₁ of a large capacitance value.

The sixth period t ₆ and the seventh period t ₇ are the same as the third period t ₃ and the fourth period t ₄ , respectively, and thus will not be described again.

Referring to FIG. 8, there is shown a circuit diagram of a one-stage driving stage of a shift register for a display panel according to a second embodiment of the present invention. The driving stage 11 ′ includes a charging unit 113 , a charging driving unit 114 , a discharging unit 115 and a compensation unit 116 . The configuration of the charging unit 113, the charging driving unit 114, and the discharging unit 115 is the same as that of the fifth embodiment of the first embodiment, and thus will not be described again. The compensation unit 116 is configured to reduce the output when the output terminal 112 of a driving stage outputs a low level signal and the first clock signal CLK ₁ is at a high level (as in the fifth period t _{5 of} FIG. 6) The chopping of 112 can be used to drive the next level of driver stage.

The compensation unit 116 includes a seventh switch T ₇ , an eighth switch T ₈ and a second capacitor C ₂ . The seventh switch T ₇ has a first end receiving the first clock signal CLK ₁ and a second end coupled to the first end of the first switch T ₁ of the charging unit 113 through a second node P ₂ and a first end The control terminal is coupled to the first node P ₁ of the charging driving unit 114. The eighth switch T ₈ has a first end coupled to the first node P ₁ of the charging driving unit 114, a second end coupled to the output end 112, and a control terminal receiving the first clock signal CLK ₁ ; During the transient period in which the first clock signal CLK ₁ is converted from the low level to the high level, the eighth switch T ₈ is turned on and the charge of the first node P ₁ of the charging driving unit 114 is discharged to The output 112. Ripple whereby, when the driving stage 11 'to the output during the low level, the first node can be reduced by the points P ₁ when the coupling effect _a conversion to a high level of the first clock signal CLK generated. One end of the second capacitor C ₂ is coupled to the first node P ₁ of the charging driving unit 114 , and the other end is coupled between the second node P ₂ and the first node P ₁ . (For example, the electric potential V _1), coupled to the first node P ₁ of the potential Vp can be represented by _a formula (1) when the first clock signal when the CLK transitions high level _1: Vp ₁ = V ₁ × [ Cgs ₇ /(Cgs ₇ +Cgd ₇ +Cgs ₁ +C ₂ )]+Vp ₂ ×[(Cgd ₇ +Cgs ₁ +C ₂ )/(Cgd ₇ +Cgs ₁ +C ₂ +Cgd ₁ +C ₁ )] (1)

Wherein, Cgs ₇ Cgd ₇ respectively and for the gate electrode of the seventh _{switch. 7} T - between the source and the gate - a stray capacitance between the drain; ₁ Cgs and Cgd is _a gate switch T, respectively, for the first electrode ₁ - Stray capacitance between source and gate-drain. When the driving stage 11 'is output to the high level, the larger Vp ₁ can be _{improved. 1} the first switch and the seventh switch T T ₇ of the charging capacity; conversely, when the driving stage 11' to output a low level The smaller Vp ₁ can reduce the chopping of the output 112. In one embodiment, to reduce the area occupied by the capacitor during fabrication, only the second capacitor C ₂ can be fabricated and the first capacitor C ₁ can be omitted. In addition, in FIG. 8, the output terminal 112 is equivalently driven by the second node P ₂ , so the potential swing of the second node P ₂ is higher than the potential change of the output terminal 112, so as to improve the drive stage 11 'of the driving capability of a driver stage, optionally the second node P ₂ is coupled to the input of a driver stage 111 for driving the lower drive stage one.

Therefore, the shift register for the display panel of the second embodiment of the present invention can be displayed as shown in FIG. 9, wherein the output of the second node P ₂ of a driver stage 11 ' is used as the next driver stage. input signal. In addition, the connection manner of other members is the same as that shown in FIG. 4, and thus will not be described again.

Please refer to FIG. 8 to FIG. 10 at the same time. FIG. 10 is an operation timing chart of the one-stage driving stage 11 ′ of FIG. 8 , which differs from FIG. 6 mainly in the second period t ₂ and the fifth period t ₅ .

During the first period t ₁ , the charging driving unit 114 receives a high level pulse of the input signal INPUT from the input terminal 111 and receives the high level of the third clock signal CLK ₃ through the control terminal of the sixth switch T ₆ . Bit pulse. At this time, the switches T ₂ and T _{6 of} the charging driving unit 114 are both turned on and the potential of the first node P ₁ is charged to a high level, the first switch T _{1 of} the charging unit 113 and the seventh of the compensation unit 116 T ₇ is opened and the switch coupled to the first clock signal CLK ₁ to the second point P ₂ and the output terminal 112. The third clock signal CLK ₃ simultaneously turns on the fifth switch T _{5 of} the discharge unit 115 to couple the output terminal 112 to the power source Vss. The potential of the first clock signal CLK ₁ is at a low level to turn off the eighth switch T ₈ , and the potentials of the second node P ₂ and the output terminal 112 are all low levels during this period. In addition, the third switch T ₃ and the fourth switch T ₄ are turned off because the second clock signal CLK ₂ is at a low level.

During the second period t ₂ , both the input signal INPUT and the third clock signal CLK ₃ are converted to a low level to turn off the switches T ₂ , T _{6 of} the charging driving unit 114 and the fifth switch T _{5 of} the discharging unit 115. The second clock signal CLK _{2 is} still maintained at a low level to turn off the switches T ₃ , T _{4 of} the discharge unit 115. The first clock signal CLK _{1 is} converted to a high level at this time. During the transient period, the first clock signal CLK ₁ first turns on the eighth switch T _{8 of} the compensation unit 116 and the first of the charging driving unit 114 a portion of the charge of a node P ₁ is discharged to the output terminal 112; then during the steady state, the potential of the first node P ₁ is again pulled up according to the coupling effect of the equation (1) while still maintaining the high level and turning on the Switches T ₁ , T ₇ . It should be understood that since the charge portion of the first node P ₁ has been discharged to the output terminal 112 and the voltage of the first clock signal CLK ₁ is received by the switches T ₇ , T ₁ and the capacitors C ₂ , C ₁ Sharing, the voltage at which the first node P ₁ is pulled up due to the coupling effect is less than that revealed by the second period t _{2 of} FIG. Therefore, the second node P ₂ and the output terminal 112 are charged to the high level by the first clock signal CLK ₁ , whereby the output terminal 112 outputs a high-level output pulse signal to one of the display lines of the display panel; The second node P ₂ outputs a high level pulse signal to the input terminal 111 of the next driver stage 11.

During the third period t ₃ and the fourth period t ₄ , the first node P _{1 of} the charging driving unit 114 is discharged to a low level and the first clock signal CLK ₁ is also at a low level, so the compensation unit 116 No action. The drive stage 11 'in this period is similar to the operation of the elements 6 and 7 in the fourth period t ₃ and t _4, therefore omitted herein during the third embodiment of the first embodiment.

During the fifth period t ₅ , the input signal INPUT remains at the low level and the second switch T _{2 of} the charging drive unit 114 is turned off. The second clock signal CLK _{2 is} still maintained at a low level to turn off the switches T ₃ , T _{4 of} the discharge unit 115. The third clock signal CLK _{3 is} switched to a low level to turn off the sixth switch T _{6 of} the charging driving unit 114 and the fifth switch T _{5 of} the discharging unit 115. The first clock signal CLK _{1 is} converted to a high level. During the transient period, the first clock signal CLK ₁ first turns on the eighth switch T _{8 of} the compensation unit 116 to the first node of the charging driving unit 114. a portion of the charge of P ₁ is discharged to the output terminal 112; then during the steady state, since the charge portion of the first node P ₁ has been discharged to the output terminal 112 and the voltage of the first clock signal CLK ₁ is subjected to the switches T ₇ , T ₁ and capacitors C ₂ and C ₁ share (Formula 1), so the voltage at which the first node P ₁ is pulled up by the coupling effect can be less than that disclosed in the fifth period t _{5 of} FIG. 6 . The potential disturbance of the output terminal 112 during this period is directly determined by the potential of the second node P ₂ of the compensation unit 116, and the voltage of the second node P ₂ is only a part of the first clock signal CLK ₁ Pressure. Thus, in FIG. 10, when during the driving stage 11 'to output a low level, since the potential of such nodes P P ₁ and less than ₂ of the first clock signal CLK ₁ of the voltage, and therefore the output terminal 112 of Chopping can be effectively reduced.

The sixth period t ₆ and the seventh period t ₇ are the same as the third period t ₃ and the fourth period t ₄ , respectively, and thus will not be described again.

In the second embodiment of the present invention, since the period of three clock signal (e.g., the third period t _3, t t _{5 4} during the fourth and fifth period) in the time period of two clock signals (e.g., first The three periods t ₃ and the fourth period t ₄ ) are all coupled to the power source Vss, so the time at which the output terminal 112 floats is only 33.3%. In addition, the driver stage 11 " is compensated by the compensation unit 116 at the output low level such that the output 112 has a lower chopping.

Referring to FIG. 11, there is shown a circuit diagram of a one-stage driving stage of a shift register for a display panel according to a third embodiment of the present invention, which is different from the second embodiment of the present invention in the third embodiment. Two clock signals, such as a clock signal CLK and an inverted clock signal CLKB, are used, and the clock signal CLK and the inverted clock signal CLKB are inverted from each other. The driving stage 11 ” also includes a charging unit 113 , a charging driving unit 114 , a discharging unit 115 and a compensation unit 116 ; wherein the charging unit 113 , the charging driving unit 114 and the compensation unit 116 are connected in a manner similar to the second embodiment of FIG. 8, and therefore omitted herein. the discharge unit 115 according to the inverted clock signal CLKB to cancel the output terminal 112, and _a floating low level when the first node P of the clock signal CLK is The discharge unit 115 includes a third switch T ₃ and a fourth switch T ₄ . The third switch T ₃ has a first end coupled to the output end 112 , a second end coupled to the power source Vss and when a control terminal receiving the inverted clock signal CLKB, when the inverted clock signal CLKB is high level, the output terminal of the third switch 112 and discharge through T ₃ to the power source Vss. the fourth switch T ₄ having a first terminal coupled to the charge driving unit 114 of the first node P _1, a second terminal coupled to the power supply Vss, and a control terminal coupled to the driver stage 11 "in the next drive stage of the second compensation unit 116 Node P ₂ ′ , when the potential of the second node P ₂ ′ is at a high level, the first node P _{1 is} discharged to the power source Vss through the fourth switch T ₄ .

Please refer to the 11th and 12th figures at the same time. Figure 12 shows the operation timing diagram of the first-level driver stage in Figure 11.

During the first period t ₁ , the charging driving unit 114 receives a high level pulse of the input signal INPUT from the input terminal 111 and receives the high level of the inverted clock signal CLKB through the control terminal of the sixth switch T ₆ . pulse. At this time, the switches T ₂ and T _{6 of} the charging driving unit 114 are both turned on and the potential of the first node P ₁ is charged to a high level, the first switch T _{1 of} the charging unit 113 and the seventh of the compensation unit 116 T ₇ is opened and the switch coupled to the clock signal CLK to the second point P ₂ and the output terminal 112. The potential of the clock signal CLK is at a low level to turn off the eighth switch T ₈ , and the potentials of the second node P ₂ and the output terminal 112 are all low levels during this period. In addition, the third switch T _{3 is} turned on because the inverted clock signal CLKB is at a high level, and the output terminal 112 is coupled to the power source Vss. In the first period t ₁ , the second node P ₂ ′ of the next driving stage is at a low level and the fourth switch T _{4 is} turned off.

During the second period t ₂ , the input signal INPUT and the inverted clock signal CLKB are both converted to a low level to turn off the switches T ₂ and T _{6 of} the charging driving unit 114 and the third switch T _{3 of} the discharging unit 115. The clock signal CLK is converted to a high level at this time. During the transient period, the clock signal CLK first turns on the eighth switch T _{8 of} the compensation unit 116 and the portion of the first node P ₁ of the charging driving unit 114. charge is discharged to the output terminal 112; during the next steady state, the coupling effect of the potential of the first node P ₁ of formula (1) once again pulled up while still maintaining the high level and turning on the switch T _1, T _7. It should be understood that since the charge portion of the first node P ₁ has been discharged to the output terminal 112 and the voltage of the clock signal CLK is shared by the switches T ₇ , T ₁ and the capacitors C ₂ , C ₁ , The voltage at which the first node P ₁ is pulled up by the coupling effect is less than that disclosed in the second period t ₂ of FIG. Therefore, the second node P ₂ and the output terminal 112 are charged to the high level by the clock signal CLK, whereby the output terminal 112 outputs a high level pulse signal to one of the display lines of the display panel; the second node P ₂ and outputs a high level pulse signal to the input terminal 111 of the next driver stage. In the second period t ₂ , the second node P ₂ ′ of the next driver stage is at a low level and the fourth switch T _{4 is} turned off.

During the third period t ₃ , the input signal INPUT is at a low level and the second switch T _{2 of} the charging drive unit 114 is turned off. The inverting clock signal CLKB is converted to a high level to turn on the switches T ₆ , T ₃ such that the output terminal 112 is coupled to the power source Vss through the first switch T ₃ to discharge to a low level. The third period T _3, the driving stage 11 "in the next drive stage of the second node P _2" is converted to a high level and turning on the fourth switch T ₄ such that the charge driving unit 114 of the first node P ₁ The switch T ₁ , T ₇ is turned off to be discharged to the low level, and the clock signal CLK is switched to the low level at this time to turn off the eighth switch T ₈ , so the compensation unit 116 does not operate.

During the fourth period t ₄ , the input signal INPUT remains at the low level and the second switch T _{2 of} the charging drive unit 114 is turned off. The inverted clock signal CLKB is converted to a low level to turn off the sixth switch T _{6 of} the charging driving unit 114 and the third switch T _{3 of} the discharging unit 115. The clock signal CLK is converted to a high level. During the transient period, the clock signal CLK first turns on the eighth switch T _{8 of} the compensation unit 116 to discharge a portion of the charge of the first node P ₁ of the charging driving unit 114. to the output terminal 112; then in a steady state, since the point P to the first part of the charge has been discharged to _a voltage of the output terminal 112 and the clock signal CLK by the switches T _7, T ₁ and a capacitor C ₂ C ₁ shares (Formula 1), so the voltage at which the first node P ₁ is pulled up by the coupling effect can be less than that disclosed in the fifth period t ₅ of FIG. 6 . The potential disturbance of the output terminal 112 during this period is directly determined by the potential of the second node P ₂ of the compensation unit 116, and the voltage of the second node P ₂ is only partial pressure of the clock signal CLK. Thus, FIG. 11, a period when "the low level to the output driver stage 11 stage, since the potential of such nodes P P ₁ and ₂ were less than the voltage level of the clock signal CLK, and therefore the output terminal 112 of Chopping can be effectively reduced.

The fifth period t ₅ and t ₇ is driven during the seventh stage 11 "is similar to the operation of each element of the third period t _3; t ₆ during the sixty-drive stage 11" during the operation of the various elements is similar to the fourth t _4, Therefore, it will not be repeated here.

The third embodiment in the present invention, during the two clock signals (e.g., the third period and the fourth period t ₃ t ₄₎ in a period when the clock signal (e.g., the third period t ₃₎ of the output The terminal 112 is coupled to the power source Vss, so the output terminal 112 floats for only 50% of the time. In addition, the driver stage 11 " is compensated by the compensation unit 116 when outputting a low level such that the output 112 has a lower chopping.

As described above, since the output terminal for the shift register of the display is long in floating time and the output voltage has a significant voltage fluctuation, it is liable to cause a malfunction of the device driven thereby. The present invention proposes another shift register for the display panel (Figs. 8 and 11), which can effectively reduce the chopping of the output potential by providing a compensation unit.

The present invention has been disclosed in the foregoing embodiments, and is not intended to limit the present invention. Any of the ordinary skill in the art to which the invention pertains can be modified and modified without departing from the spirit and scope of the invention. . Therefore, the scope of the invention is defined by the scope of the appended claims.

10,10 ' . . . Shift register

11, 11 ' , 11 '' . . . Primary driver level

111. . . Input

112. . . Output

113. . . Charging unit

114. . . Charging drive unit

115. . . Discharge unit

116. . . Compensation unit

20. . . Clock generator

CLK ₁ ~ CLK ₃ . . . Clock signal

T ₁ ~T ₈ . . . switch

t ₁ ~t ₇ . . . period

C ₁ , C ₂ . . . capacitance

P ₁ , P ₂ . . . node

INPUT. . . input signal

OUTPUT. . . output signal

CLK, CLKB. . . Clock signal

P ₂ ' . . . Second node of the next driver level

9. . . Shift register

91. . . Primary driver level

V _DD . . . Positive voltage source

Vss. . . power supply

SW ₁ ~SW ₆ . . . Switching element

P, P ' . . . node

Figure 1 shows a block diagram of a conventional shift register for a liquid crystal display.

Figure 2 shows the circuit diagram of the primary driver stage in Figure 1.

Figure 3 shows the timing diagram of the operation of the one-level driver stage of Figure 2.

Fig. 4 is a block diagram showing a shift register for a display panel in the first embodiment of the present invention.

Figure 5 shows the circuit diagram of the primary driver stage in Figure 4.

Fig. 6 is a timing chart showing the operation of the one-stage driver stage of Fig. 5.

Fig. 7 is a view showing the operation of the one-stage driving stage of Fig. 5.

Figure 8 is a circuit diagram showing a one-stage driving stage of a shift register for a display panel in accordance with a second embodiment of the present invention.

Figure 9 is a block diagram showing a shift register for a display panel in accordance with a second embodiment of the present invention.

Fig. 10 is a timing chart showing the operation of the one-stage driving stage of Fig. 8.

Figure 11 is a circuit diagram showing a one-stage driving stage of a shift register for a display panel in accordance with a third embodiment of the present invention.

Fig. 12 is a timing chart showing the operation of the one-stage driving stage of Fig. 11.

11 ' . . . Primary driver level

111. . . Input

112. . . Output

113. . . Charging unit

114. . . Charging drive unit

115. . . Discharge unit

116. . . Compensation unit

CLK ₁ ~ CLK ₃ . . . Clock signal

T ₁ ~T ₈ . . . switch

C ₁ , C ₂ . . . capacitance

P ₁ , P ₂ . . . node

INPUT. . . input signal

OUTPUT. . . output signal

Vss. . . power supply

Claims (21)

A shift register for a display panel, comprising a plurality of serially connected driving stages, wherein an input signal of each of the driving stages after the second driving stage is provided by a previous stage driving stage, each driving stage comprising: an input end An output unit for charging a first clock signal according to a potential of the first node; and a discharge unit for simultaneously the first node according to a second clock signal Discharging the output terminal and discharging the output terminal according to a third clock signal; and a charging driving unit configured to control the potential of the first node according to the input terminal and the potential of the third clock signal, wherein The first clock signal, the second clock signal, and the third clock signal are sequentially converted into high-level pulses. The shift register of claim 1, wherein the charging unit comprises a first switch, the first switch has a first end receiving the first clock signal, and a second end coupled to the output end And a control end coupled to the first node. According to the shift register of claim 2, the charging unit further includes a first capacitor coupled between the first node and the output, and the first, second and third clock signals There is a phase difference between each other. The shift register according to the first aspect of the patent application, wherein the discharge unit comprises a third switch, a fourth switch and a fifth switch; the third switch has a first end coupled to the output end, The second end is coupled to a power source and the control terminal receives the second clock signal; the fourth switch has a first end coupled to the first node, a second end coupled to the power source, and a control end receiving the first a second clock signal; the fifth switch has a first end coupled to the output end, a second end coupled to the power source, and a control end receiving the third clock signal; wherein when the second clock signal is high When the level is in position, the first node and the output end are respectively discharged to the power source through the fourth switch and the third switch. When the third clock signal is at a high level, the output end is transmitted through the fifth switch. The power supply is discharged. According to the shift register of claim 1, wherein the charging drive unit comprises a second switch and a sixth switch; the second switch has a first end and a control end coupled to the input end and a The second end is coupled to the first node; the sixth switch has a first end coupled to the input end, a second end coupled to the first node, and a control end receiving the third clock signal; When the input terminal and the potential of the third clock signal are both at a high level, the first node is charged to a high level, and when the input terminal is at a low level and the third clock signal is at a high level, the The first node is discharged to a low level. According to the shift register of claim 1, wherein the output of each driver stage is coupled to the input of its next driver stage. According to the shift register of claim 1, each driver stage further includes a compensation unit coupled between the first clock signal, the first node, the charging unit and the output end, for When the output of the driver stage is at a low level and the first clock signal is at a high level, the chopping of the output is reduced. The shift register according to claim 7 , wherein the compensation unit comprises a seventh switch, an eighth switch and a second capacitor; the seventh switch has a first end receiving the first clock signal The second end is coupled to the charging unit and coupled to the first node via a second node. The eighth switch has a first end coupled to the first node and a second end coupled to the output. The terminal and the control terminal receive the first clock signal; the second capacitor is coupled between the first node and the second node. According to the shift register of claim 8, wherein the second node of each drive unit is coupled to the input of the next drive stage. A shift register for a display panel, comprising a plurality of serially connected driving stages, wherein an input signal of each of the driving stages after the second driving stage is provided by a previous stage driving stage, each driving stage comprising: an input end An output terminal having a first switch receiving a first clock signal, a second end coupled to the output end and a control end coupled to a first node, and a second switch having a first switch The first end and a control end are coupled to the input end and a second end is coupled to the first node; a third switch having a first end coupled to the output end, a second end coupled to a power source, and a control end receiving a second clock signal; a fourth switch having a first end coupled to the first a second node is coupled to the power source and a control terminal receives the second clock signal; a fifth switch has a first end coupled to the output end, a second end coupled to the power source, and a control Receiving a third clock signal, and a sixth switch having a first end coupled to the input end, a second end coupled to the first node, and a control end receiving the third clock signal, wherein The first clock signal, the second clock signal, and the third clock signal are sequentially converted into high-level pulses; and the power source is configured to discharge the first node and the output end. The shift register according to claim 10, further comprising: a seventh switch having a first end receiving the first clock signal and a second end coupled to the first end of the first switch And a control end coupled to the first node; and an eighth switch having a first end coupled to the first node, a second end coupled to the output end, and a control end receiving the first clock signal; The first, second, and third clock signals have a phase difference from each other. A shift register according to claim 10, wherein the first to eighth switches are N-type thin film transistors. A shift register according to claim 10, wherein the first end of the first switch of each driver stage is coupled to the input of a next driver stage thereof. The shift register according to claim 10, further comprising a capacitor coupled between the first node and the first end of the first switch. A shift register for a display panel, comprising a plurality of serially connected driving stages, wherein an input signal of each of the driving stages after the second driving stage is provided by a previous stage driving stage, each driving stage comprising: an input end An output unit configured to charge a second node to the output terminal according to a potential of the first node; a discharge unit configured to discharge the first node and the output terminal according to the at least one clock signal a charging driving unit configured to control a potential of the first node according to the input end and a potential of the at least one clock signal; and a compensation unit coupled to the first clock signal, the first node, the first Between the two nodes and the output terminal, the compensation unit includes a seventh switch and an eighth switch, wherein the seventh switch has a first end receiving the first clock signal and a second end coupling the second end The first switch is coupled to the first node, and the first switch has a first end coupled to the first node, a second end coupled to the output end, and a control end receiving the first clock signal, where The first clock signal, the first The third clock signal and the clock signal are sequentially converted into a high level pulse. The shift register according to claim 15 , wherein the compensation unit further comprises a capacitor coupled between the first and second nodes. The shift register according to claim 15 , wherein the discharge unit comprises a third switch, a fourth switch and a fifth switch; the third switch has a first end coupled to the output end, The second end is coupled to a power supply and the control end receives a second clock signal. The fourth switch has a first end coupled to the first node, a second end coupled to the power source, and a control end receiving the first The second clock signal has a first end coupled to the output end, a second end coupled to the power source, and a control end receiving a third clock signal. A shift register according to claim 17 wherein the first, second and third clock signals have a phase difference from each other. The shift register according to claim 15 , wherein the discharge unit comprises a third switch and a fourth switch; the third switch has a first end coupled to the output end and a second end coupled A power supply and a control terminal receive an inverted clock signal. The fourth switch has a first end coupled to the first node, a second end coupled to the power source, and a control end coupled to the next driver stage. The second node. A shift register according to claim 19, wherein the first clock signal and the inverted clock signal have opposite phases. A shift register according to claim 15 wherein the second node of each driver stage is coupled to the input of the next driver stage.