KR100956748B1 - Level shifter for display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter for display that can secure excellent operating characteristics even for low voltage input signals when configuring a gate driver using an amorphous silicon thin film transistor (a-Si TFT). To this end, the first input unit for outputting a low voltage input signal supplied from the outside in accordance with the input clock signal, and the output voltage of the low voltage supplied from the outside in accordance with the inverted clock signal having a phase opposite to the clock signal; 2 an input unit, a low voltage driver for varying a voltage of an output signal according to charging / discharging of a signal input from the first input unit or a second input unit, and charging the high voltage to the low voltage driver in accordance with the inverted clock signal input from the outside. And a switching unit.

Gate Driver, Level Shifter, Amorphos, Low Voltage, Bootstrap

Description

LEVEL SHIFTER FOR DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter for displays that can ensure excellent operating characteristics even for low voltage input when configuring a gate driver using an amorphous silicon thin film transistor (a-Si TFT). .

In general, the voltage used in a semiconductor integrated circuit is a low voltage of 5V or less, but a voltage used for a display or a specific circuit uses a higher voltage.

For example, in a thin film transistor liquid crystal display using an amorphous-silicon thin film transistor, the pulse voltage supplied to the gate line requires a high voltage of about 20V or more. Therefore, if the output voltage of a conventional semiconductor integrated circuit using a low voltage of 5V or less is directly supplied to such a display or a circuit for driving the same, the low voltage must be converted to match the display or a circuit for driving the same. The circuit called level shifter is responsible for this function.

The level shifter has been applied to a gate driver mainly composed of a single crystal silicon wafer, a poly-silicon thin film transistor, or an amorphous-silicon thin film transistor. However, when a level shifter is constructed using an amorphous-silicon thin film transistor, a-Si is used. Due to the high threshold voltage of the thin film transistor, power consumption is large, so the practicality is somewhat reduced.

Disclosure of Invention An object of the present invention is for a display that can secure excellent operating characteristics even for a low voltage input signal when configuring a gate driver using a large-area amorphous silicon thin film transistor (a-Si TFT). To provide a level shifter.

Technical means of the present invention for achieving the above object, the first input unit for outputting an input signal of a low voltage supplied from the outside in accordance with the input clock signal; A second input unit configured to output a low voltage reference voltage supplied from an external device according to an inverted clock signal having a phase opposite to that of the clock signal; A low voltage driver configured to vary a voltage of an output signal according to charging / discharging of a signal input from the first input unit or the second input unit; A switching unit for charging a high voltage to the low voltage driver in response to the inverted clock signal input from the outside; A first inverter which opens and closes according to the charge / discharge voltage of the low voltage driver and outputs a high voltage pulse having a phase inverted from an input signal; And a second inverter that opens and closes according to the signal input from the first inverter and generates a high voltage pulse signal to an output terminal.

In detail, the first input unit includes a first transistor connected to a current path between the first input terminal and the first node to open and close according to a clock signal input from the outside to output a low voltage input signal supplied from the outside. The second input unit may include a second transistor configured to connect a current path between a second input terminal and the first node, open and close according to a clock signal input from the outside, and output a reference voltage supplied from the outside.

The input signal input to the first input unit is a low voltage lower than the threshold voltage of the amorphous silicon transistor, and the reference voltage supplied to the second input unit is lower than the maximum amplitude of the input signal.

The low voltage driver includes a first capacitor installed between the first node and the second node to charge / discharge the voltage supplied to the first node, based on the switching threshold voltage of the first inverter according to the charge / discharge. It is characterized by generating a pulse swinging with.

The switching unit may be connected to a current path between a second node and a third node of one side of the first capacitor to open and close according to an inverted clock signal identical to a clock signal input to the second transistor to charge the first capacitor. It is characterized by consisting of a third transistor.

As described above, according to the present invention, when the level shifter is formed using an amorphous-silicon thin film transistor, excellent operating characteristics can be obtained even for a low voltage input signal, thereby reducing power consumption and improving the power design of the gate driver. There is an advantage that can provide convenience.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram illustrating a configuration of a liquid crystal display to which the present invention is applied. As shown in FIG. 1, a liquid crystal display generates a high voltage pulse required for driving a liquid crystal panel by receiving a liquid crystal pixel array and a low voltage signal from the outside. A level shifter, a shift register for distributing the signal received from the level shifter sequentially or non-sequentially to each gate line, and converting the input digital video signal into an analog video signal (pixel voltage) to the source lines. And a timing controller for controlling the gate driver and the source driver and supplying the digital video signal to the source driver in accordance with a clock signal.

A plurality of source lines and a plurality of gate lines intersect each other in the pixel array, and thin film transistors for driving the liquid crystal cell are formed at each intersection thereof. The thin film transistor supplies a pixel voltage supplied through the source line to the liquid crystal cell in response to a scan signal from the gate line.

The level shifter may be directly mounted on a substrate of a liquid crystal panel together with a shift register. A thin film transistor (TFT) constituting the level shifter or the like is of an amorphous-silicon type.

At present, since all TFT LCD processes are of the amorphous-silicon type, panel makers prefer the amorphous-silicon method because there is no investment cost and no additional cost for the process.

The amorphous-silicon type has a simple process and well-processed conditions, and the TFT manufacturing cost is considerably lower than that of the poly-silicon method. TFT-LCDs are made of amorphous silicon, so circuits such as gate drivers must be made of the same amorphous silicon type to reduce process and cost.

Although the LCD panel is illustrated in FIG. 1, the level shifter according to the present invention may be applied to a display such as an OLED (Organic Light Emitting Display) as well as an LCD (Liquid Crystal Display) method.

2 is a circuit block diagram illustrating a level shifter according to the present invention. The level shifter 100 includes a first input unit 110, a second input unit 120, a low voltage driver 130, a switching unit 140, and a first unit. It includes an inverter 150 and a second inverter 160. And all transistors shown in FIG. 2 are amorphous-silicon thin film transistors.

The first input unit 110 includes a first transistor T1 that is opened and closed according to the input clock signal CLK and outputs a low voltage input signal supplied from the outside, and the second input unit 120. Is a second transistor T2 that is opened and closed in response to the inverted clock signal CLKB having a phase opposite to that of the clock signal CLK and outputs a reference voltage Vref supplied from the outside. The input signals Low Input (Vref) and the clock signals CLK and CLKB input to the first input unit 110 and the second input unit 120 are, for example, signals input from the timing controller of FIG. 1.

The first transistor T1 of the first input unit 110 is connected to a current path between the first input terminal and the first node Nd1 and opened and closed according to a clock signal CLK input from the outside to supply a low voltage. It is configured to output a low input signal.

The second transistor T2 of the second input unit 120 is connected to a current path between the second input terminal and the first node Nd1 and is opened and closed according to a clock signal CLK input from the outside to supply a low voltage. Is configured to output a reference voltage of Vref. Here, the first transistor T1 and the second transistor T2 are connected in parallel with each other with respect to the first node Nd1.

In addition, a low input signal input to the first input unit 110 is a low voltage lower than a threshold voltage of an amorphous-silicon thin film transistor, and a reference voltage Vref supplied to the second input unit 120 is an input signal. It is a DC voltage lower than the maximum amplitude of (Low Input). For example, a low input pulse supplied to the first transistor T1 is a low voltage pulse of 0 V to 1 V, and a reference voltage Vref supplied to the second transistor T2 is about 0.5 V DC. Corresponds to half the maximum amplitude of

The low voltage driver 130 includes a first capacitor C1 that varies a voltage of an output signal according to charging / discharging of a signal input from the first input unit 110 or the second input unit 120. The first capacitor C1 is connected between the first node Nd1 and the second node Nd2 to charge / discharge the voltage supplied to the first node Nd1 and to charge the capacitor C1. The potential on the second node Nd2 side is varied according to the / discharge.

The switching unit 140 includes a third transistor T3 that is opened and closed according to an inverted clock signal CLKB input from the outside to charge the low voltage driver 130 with a high voltage. The third transistor T3 includes a clock signal connected to a current path between the second node Nd2 and the third node Nd3, which are one side of the first capacitor C1, and input to the second transistor T2. It is configured to open and close according to the same inverted clock signal CLKB to charge the first capacitor C1.

The first inverter 150 is opened and closed according to the charge / discharge voltage of the low voltage driver 130 to output a plurality of transistors T4, T5, which output a high voltage pulse having a phase inverted with a first input signal. T6) and the second capacitor C2. That is, the first inverter 150 has a current path connected between the high potential Vdd and the fourth node Nd4 and is opened and closed according to the high voltage supplied from the high potential to output the supplied high voltage. And a fifth transistor T5 connected with a current path between the high potential Vdd and the third node Nd3 to open and close according to a signal supplied from a source of the fourth transistor T4 to output a high voltage. And a second capacitor C2 connected between the fourth node Nd4 and the third node Nd3 to bootstrapping the gate of the fifth transistor T5, and the third node Nd3. A sixth transistor T6 connected with a current path between the and the low potential to open and close according to a signal supplied from the second node Nd2, which is one side of the first capacitor C1, to pull down the voltage of the third node Nd3. Consists of

That is, the first capacitor C1 generates a pulse that swings based on the threshold voltage of the sixth transistor T6 according to the signal input through the first transistor T1, and the sixth transistor T6 generates the first pulse. Opening and closing according to the variable pulse of the first capacitor C1 pulls up the voltage of the third node Nd3 to a high potential or to a low potential.

The second inverter 160 is opened and closed according to the signal input from the first inverter 150 to generate a high voltage pulse signal to the output terminal (T7, T8, T9) and the third capacitor (C3). Consists of The second inverter 160 includes a seventh transistor T7 connected with a high current Vdd and a fifth node Nd5 to open and close according to a high voltage supplied from the high potential, and output a high voltage. An eighth transistor T8 is connected between the high potential Vdd and the output terminal, and is opened and closed according to a signal supplied from the fifth node Nd5 to output a high voltage to the output terminal. A third capacitor C3 connected between the fifth node Nd5 and the output terminal and bootstrapping the gate of the eighth transistor T8, and a current path is connected between the output terminal and the low potential Vss so that the third node ( And a ninth transistor T9 that opens and closes in response to a signal input from Nd3) to pull up or pull down the output terminal to high potential or low potential.

In the above description, each of the transistors T1 to T9 is an amorphous-silicon thin film transistor, and the threshold voltage is approximately high at about 3V. In addition, since the amorphous-silicon thin film transistor has a bidirectional characteristic in which current flows in either direction depending on the potential, the names of the drain and the source are named for convenience of description and are not significant.

The Amorphous-silicon type level shifter 100 configured as described above converts the input voltage to a higher voltage, and the threshold voltage of the Amorphous-silicon thin film transistor is used as the first transistor T1 of the first input unit 110. Even if a lower low voltage is supplied, it can be easily converted to a high voltage.

The overall operation of the level shifter configured as described above is as follows.

The first transistor T1 is opened and closed according to the first clock signal CLK of about 0 to 10V input from the outside, and a low input signal of about 0 to 1V supplied to the outside is supplied to the first node Nd1. When the second clock signal CLKB, which is charged to the first capacitor C1 and is out of phase with the first clock signal CLK, is input to the second transistor T2, the reference voltage Vref of about 0.5V DC is obtained. ) Is charged to the first capacitor C1 through the first node Nd1. Accordingly, as the second node Nd2 is charged / discharged by the third transistor T3, the voltage level of the second node Nd2 is higher than the threshold voltage of the sixth transistor T6. Swing with low voltage. Therefore, a pulse for repeating on and off is supplied to the second node Nd2 based on the threshold voltage of the sixth transistor T6.

That is, the low input signal is supplied through the first transistor T1 when the first clock signal CLK is at a high level as shown in FIG.

When the second clock signal CLKB has a high level, the second transistor T2 and the third transistor T3 are turned on, and the input reference voltage Vref, the second capacitor C2, and the fifth and the second clock signal CLKB are turned on. The voltage of the third node where the sixth transistors T5 and T6 meet is connected to the first capacitor C1. When the high level first clock signal CLK is input again and the low level second clock signal CLKB continues, the low voltage input signal of about 0 to 1 V is inputted to the first capacitor C1 so that the second node ( The voltage of Nd2) is shaken between 2.6V and 3.2V by the input signal as shown in FIG. 3A. Coupling occurs due to the charge conservation law with the first capacitor C1 interposed therebetween, so that the first node Cd and the third transistor T3 are connected to the second node Nd2 at a small input voltage. Coupling occurs to change into an AC waveform.

This voltage enables the operation of the sixth transistor T6 even with a small voltage while swinging the voltage level at which the sixth transistor T6 is turned on and off.

Accordingly, the sixth transistor T6 is driven by supplying a large pulse (approximately 0 to 4 V), or is driven with a pulse of about 1 V while adjusting the on / off level of the threshold voltage of the sixth transistor T6. Will have the same effect.

When the sixth transistor T6 is turned on due to the input signal supplied to the sixth transistor T6, the phase of the input signal is inverted due to the bootstrap inverter structures of the fourth and fifth transistors T4 and T5 and thus the third transistor is turned on. Output to node Nd3. That is, when the sixth transistor T6 is turned on, the potential of the third node Nd3 is pulled down to a low potential so that the first inverter 150 outputs a low voltage. At this time, due to the high voltage Vdd (approximately 25V) and the low voltage Vss (approximately -7V), the input signal of 0 to 1V is amplified by approximately -2 to 10V.

The amplified signal turns the ninth transistor T9 on or off. When the third node Nd3 is at low potential, the ninth transistor T9 is turned off, and thus the second inverter 160 is turned off. The eighth transistor T8 is turned on by bootstrapping of the third capacitor C3 to output a high voltage to the output terminal. For example, the pulse output from the second inverter 160 to the output terminal is amplified to approximately -4 to 23V.

On the other hand, when the sixth transistor T6 is turned on, the voltage of the third node Nd3 pulls down to the low potential Vss and eventually drops to the low voltage. Finally, the DC high voltage Vdd is applied according to the sixth transistor T6. Is converted into a pulse. In this case, the voltage of the third node Nd3, which is the output of the first inverter 150, has a level opposite to the second node Nd2, which is an input pulse of the sixth transistor T6. Although the output pulse of the third node Nd3 is 0 to 1V, the output pulse is amplified to approximately -2 to 5V as shown in FIG. 3B.

When the amplified signal is passed through the second inverter 160, the same pulse as the input pulse is generated, and as shown in FIG. 3B, a large output of about -4 to 23V can be made. The waveform thus amplified can be used for shift registers and other devices other than the digital clock signal (0 to 5V) in the display device.

The level shifter configured as described above can output about -4 to 23V as shown in FIG. 3B even when the input signal input to the first transistor T1 is at a low voltage of about 0 to 1V as shown in FIG. 3A. This means that the level shifter according to the present invention operates smoothly even with a low input signal.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit of the present invention. Therefore, such modifications, changes and additions should be determined not only by the claims below, but also by equivalents to those claims.

1 is a conceptual diagram showing the configuration of a liquid crystal display to which the present invention is applied.

2 is a circuit block diagram showing a level shifter according to the present invention.

3A and 3B are diagrams showing waveforms of signals appearing at each node in the circuit of FIG. 2, respectively.

* Explanation of symbols for the main parts of the drawings

100: level shifter 110: first input unit

120: second input unit 130: low voltage driver

140: switching unit 150: first inverter

160: second inverter

Claims (7)

A first input unit configured to output an input signal having a low voltage supplied from the outside according to the input clock signal; A second input unit configured to output a low voltage reference voltage supplied from an external device according to an inverted clock signal having a phase opposite to that of the clock signal; A low voltage driver configured to vary a voltage of an output signal according to charging / discharging of a signal input from the first input unit or the second input unit; A switching unit for charging a high voltage to the low voltage driver in response to the inverted clock signal input from the outside; A first inverter which opens and closes according to the charge / discharge voltage of the low voltage driver and outputs a high voltage pulse having a phase inverted from an input signal; And And a second inverter that opens and closes in response to a signal input from the first inverter to generate a high voltage pulse signal to an output terminal. The method according to claim 1, The first input unit includes a first transistor connected to a current path between the first input terminal and the first node to open and close according to a clock signal input from the outside, and output an input signal having a low voltage supplied from the outside. The second input unit is a display for the display, characterized in that the current path is connected between the second input terminal and the first node is opened and closed in response to an inverted clock signal input from the outside to output a reference voltage supplied from the outside. Level shifter. The method according to claim 2, The input signal input to the first input unit is a low voltage lower than the threshold voltage of the amorphous silicon transistor, and the reference voltage supplied to the second input unit is a DC voltage lower than the maximum amplitude of the input signal. Shifter. The method according to claim 2, The low voltage driver includes a first capacitor installed between the first node and the second node to charge / discharge the voltage supplied to the first node, based on the switching threshold voltage of the first inverter according to the charge / discharge. A level shifter for a display, characterized in that it generates a pulse that is swinged by. The method according to claim 4, The switching unit may include a current path connected between a second node and a third node, which is one side of the first capacitor, to open and close according to the same inverted clock signal as the clock signal input to the second transistor to charge the first capacitor. A level shifter for display, comprising three transistors. The method according to claim 5, The first inverter may include: a fourth transistor connected to a high potential and a fourth node to open and close a current according to a power supply voltage supplied from the high potential to output a high voltage; A fifth transistor connected between the high potential and a third node to open and close a current path according to a signal supplied from a source of a fourth transistor to output a high voltage; A second capacitor coupled between the fourth node and a third node to bootstrap a gate of a fifth transistor; And A sixth transistor connected to a current path between the third node and the low potential to open and close according to a signal supplied from a second node, which is one side of the first capacitor, to pull down the voltage of the third node; Dragon level shifter. The method according to claim 6, The second inverter includes: a seventh transistor connected to a high current path between a high potential and a fifth node to open and close according to a power supply voltage supplied from the high potential, and output a high voltage; An eighth transistor connected between the high potential and the output terminal to open and close according to a signal supplied from a fifth node to output a high voltage to the output terminal; A third capacitor coupled between the fifth node and an output terminal to bootstrap a gate of an eighth transistor; And And a ninth transistor connected to a current path between the output terminal and the low potential to open and close according to a signal input from a third node to pull up or pull down the output terminal to a high potential.

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